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[2a02:8440:6340:f287:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id cf16-20020a0564020b9000b0044fc3c0930csm20424246edb.16.2022.09.19.09.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Sep 2022 09:59:50 -0700 (PDT) From: Guillaume Ranquet Date: Mon, 19 Sep 2022 18:56:02 +0200 Subject: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220919-v1-4-4844816c9808@baylibre.com> References: <20220919-v1-0-4844816c9808@baylibre.com> In-Reply-To: <20220919-v1-0-4844816c9808@baylibre.com> To: Vinod Koul , Stephen Boyd , David Airlie , Rob Herring , Philipp Zabel , Krzysztof Kozlowski , Daniel Vetter , Chunfeng Yun , CK Hu , Jitao shi , Chun-Kuang Hu , Michael Turquette , Kishon Vijay Abraham I , Matthias Brugger Cc: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, Pablo Sun , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Mattijs Korpershoek , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Guillaume Ranquet , devicetree@vger.kernel.org X-Mailer: b4 0.10.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add mt8195 SoC bindings for hdmi and hdmi-ddc Make port1 optional for mt8195 as it only supports HDMI tx for now. Requires a ddc-i2c-bus phandle. Requires a power-domains phandle. Signed-off-by: Guillaume Ranquet diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hd= mi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.= yaml index bdaf0b51e68c..abb231a0694b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -21,6 +21,10 @@ properties: - mediatek,mt7623-hdmi - mediatek,mt8167-hdmi - mediatek,mt8173-hdmi + - mediatek,mt8195-hdmi + + clocks: true + clock-names: true =20 reg: maxItems: 1 @@ -28,20 +32,6 @@ properties: interrupts: maxItems: 1 =20 - clocks: - items: - - description: Pixel Clock - - description: HDMI PLL - - description: Bit Clock - - description: S/PDIF Clock - - clock-names: - items: - - const: pixel - - const: pll - - const: bclk - - const: spdif - phys: maxItems: 1 =20 @@ -58,6 +48,16 @@ properties: description: | phandle link and register offset to the system configuration registe= rs. =20 + ddc-i2c-bus: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: Phandle to the ddc-i2c device + + power-domains: + description: + A phandle and PM domain specifier as defined by bindings + of the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. + ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -76,7 +76,6 @@ properties: =20 required: - port@0 - - port@1 =20 required: - compatible @@ -86,9 +85,55 @@ required: - clock-names - phys - phy-names - - mediatek,syscon-hdmi - ports =20 +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-hdmi + then: + properties: + clocks: + items: + - description: APB + - description: HDCP + - description: HDCP 24M + - description: Split HDMI + clock-names: + items: + - const: hdmi_apb_sel + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + required: + - power-domains + - ddc-i2c-bus + else: + properties: + clocks: + items: + - description: Pixel Clock + - description: HDMI PLL + - description: Bit Clock + - description: S/PDIF Clock + + clock-names: + items: + - const: pixel + - const: pll + - const: bclk + - const: spdif + + ports: + required: + - port@1 + + required: + - mediatek,syscon-hdmi + additionalProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt= 8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/med= iatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..3c80bcebe6d3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hd= mi-ddc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-d= dc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + hdmiddc0: ddc_i2c { + compatible =3D "mediatek,mt8195-hdmi-ddc"; + clocks =3D <&clk26m>; + clock-names =3D "ddc-i2c"; + }; + +... --=20 b4 0.10.0-dev