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From: Guillaume Ranquet <granquet@baylibre.com>
Date: Mon, 19 Sep 2022 18:56:14 +0200
Subject: [PATCH v1 16/17] drm/mediatek: dpi: Add mt8195 hdmi to DPI driver
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To: Vinod Koul <vkoul@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
        David Airlie <airlied@linux.ie>,
        Rob Herring <robh+dt@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Daniel Vetter <daniel@ffwll.ch>,
        Chunfeng Yun <chunfeng.yun@mediatek.com>,
        CK Hu <ck.hu@mediatek.com>, Jitao shi <jitao.shi@mediatek.com>,
        Chun-Kuang Hu <chunkuang.hu@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-mediatek@lists.infradead.org,
        dri-devel@lists.freedesktop.org,
        Pablo Sun <pablo.sun@mediatek.com>, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Mattijs Korpershoek <mkorpershoek@baylibre.com>,
        linux-arm-kernel@lists.infradead.org,
        linux-phy@lists.infradead.org,
        Guillaume Ranquet <granquet@baylibre.com>,
        devicetree@vger.kernel.org
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Add the DPI1 hdmi path support in mtk dpi driver

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/=
mtk_dpi.c
index 630a4e301ef6..91212b7610e8 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -15,7 +15,10 @@
 #include <linux/of_graph.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_device.h>
+#include <linux/reset.h>
 #include <linux/types.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
=20
 #include <video/videomode.h>
=20
@@ -66,10 +69,14 @@ struct mtk_dpi {
 	struct drm_bridge *next_bridge;
 	struct drm_connector *connector;
 	void __iomem *regs;
+	struct reset_control *reset_ctl;
 	struct device *dev;
 	struct clk *engine_clk;
+	struct clk *dpi_ck_cg;
 	struct clk *pixel_clk;
+	struct clk *dpi_sel_clk;
 	struct clk *tvd_clk;
+	struct clk *hdmi_cg;
 	int irq;
 	struct drm_display_mode mode;
 	const struct mtk_dpi_conf *conf;
@@ -135,6 +142,7 @@ struct mtk_dpi_yc_limit {
  * @yuv422_en_bit: Enable bit of yuv422.
  * @csc_enable_bit: Enable bit of CSC.
  * @pixels_per_iter: Quantity of transferred pixels per iteration.
+ * @is_internal_hdmi: True if this DPI block is directly connected to SoC =
internal HDMI block
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -153,6 +161,7 @@ struct mtk_dpi_conf {
 	u32 yuv422_en_bit;
 	u32 csc_enable_bit;
 	u32 pixels_per_iter;
+	bool is_internal_hdmi;
 };
=20
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas=
k)
@@ -466,8 +475,15 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
 		pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
=20
 	mtk_dpi_disable(dpi);
+
+	reset_control_rearm(dpi->reset_ctl);
+
 	clk_disable_unprepare(dpi->pixel_clk);
 	clk_disable_unprepare(dpi->engine_clk);
+	clk_disable_unprepare(dpi->dpi_sel_clk);
+	clk_disable_unprepare(dpi->dpi_ck_cg);
+	clk_disable_unprepare(dpi->hdmi_cg);
+	clk_disable_unprepare(dpi->tvd_clk);
 }
=20
 static int mtk_dpi_power_on(struct mtk_dpi *dpi)
@@ -483,12 +499,44 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
 		goto err_refcount;
 	}
=20
+	ret =3D clk_prepare_enable(dpi->dpi_sel_clk);
+	if (ret) {
+		dev_err(dpi->dev, "failed to enable dpi_sel clock: %d\n", ret);
+		goto err_refcount;
+	}
+
+	ret =3D clk_prepare_enable(dpi->tvd_clk);
+	if (ret) {
+		dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret);
+		goto err_tvd;
+	}
+
+	ret =3D clk_prepare_enable(dpi->engine_clk);
+	if (ret) {
+		dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
+		goto err_engine;
+	}
+
+	ret =3D clk_prepare_enable(dpi->hdmi_cg);
+	if (ret) {
+		dev_err(dpi->dev, "Failed to enable hdmi_cg clock: %d\n", ret);
+		goto err_hdmi_cg;
+	}
+
+	ret =3D clk_prepare_enable(dpi->dpi_ck_cg);
+	if (ret) {
+		dev_err(dpi->dev, "Failed to enable dpi_ck_cg clock: %d\n", ret);
+		goto err_ck_cg;
+	}
+
 	ret =3D clk_prepare_enable(dpi->pixel_clk);
 	if (ret) {
 		dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
 		goto err_pixel;
 	}
=20
+	reset_control_reset(dpi->reset_ctl);
+
 	if (dpi->pinctrl && dpi->pins_dpi)
 		pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
=20
@@ -496,6 +544,15 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
=20
 err_pixel:
 	clk_disable_unprepare(dpi->engine_clk);
+	clk_disable_unprepare(dpi->dpi_ck_cg);
+err_ck_cg:
+	clk_disable_unprepare(dpi->hdmi_cg);
+err_hdmi_cg:
+	clk_disable_unprepare(dpi->engine_clk);
+err_engine:
+	clk_disable_unprepare(dpi->tvd_clk);
+err_tvd:
+	clk_disable_unprepare(dpi->dpi_sel_clk);
 err_refcount:
 	dpi->refcount--;
 	return ret;
@@ -539,7 +596,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	else
 		clk_set_rate(dpi->pixel_clk, vm.pixelclock);
=20
-
 	vm.pixelclock =3D clk_get_rate(dpi->pixel_clk);
=20
 	dev_dbg(dpi->dev, "Got  PLL %lu Hz, pixel clock %lu Hz\n",
@@ -606,7 +662,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp=
i,
 	if (dpi->conf->support_direct_pin) {
 		mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 		mtk_dpi_config_2n_h_fre(dpi);
-		mtk_dpi_dual_edge(dpi);
+		// DPI could be connecting to external bridge
+		// or internal HDMI encoder.
+		if (dpi->conf->is_internal_hdmi) {
+			mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN,
+				     DPI_OUTPUT_1T1P_EN);
+			mtk_dpi_mask(dpi, DPI_CON, DPI_INPUT_2P_EN,
+				     DPI_INPUT_2P_EN);
+		} else {
+			mtk_dpi_dual_edge(dpi);
+		}
 		mtk_dpi_config_disable_edge(dpi);
 	}
 	if (dpi->conf->input_2pixel) {
@@ -721,7 +786,10 @@ static void mtk_dpi_bridge_disable(struct drm_bridge *=
bridge)
 {
 	struct mtk_dpi *dpi =3D bridge_to_dpi(bridge);
=20
-	mtk_dpi_power_off(dpi);
+	if (dpi->conf->is_internal_hdmi)
+		mtk_dpi_power_off(dpi);
+	else
+		mtk_dpi_disable(dpi);
 }
=20
 static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
@@ -764,14 +832,16 @@ void mtk_dpi_start(struct device *dev)
 {
 	struct mtk_dpi *dpi =3D dev_get_drvdata(dev);
=20
-	mtk_dpi_power_on(dpi);
+	if (!dpi->conf->is_internal_hdmi)
+		mtk_dpi_power_on(dpi);
 }
=20
 void mtk_dpi_stop(struct device *dev)
 {
 	struct mtk_dpi *dpi =3D dev_get_drvdata(dev);
=20
-	mtk_dpi_power_off(dpi);
+	if (!dpi->conf->is_internal_hdmi)
+		mtk_dpi_power_off(dpi);
 }
=20
 static int mtk_dpi_bind(struct device *dev, struct device *master, void *d=
ata)
@@ -854,6 +924,11 @@ static unsigned int mt8183_calculate_factor(int clock)
 		return 2;
 }
=20
+static unsigned int mt8195_calculate_factor(int clock)
+{
+	return 1;
+}
+
 static unsigned int mt8195_dpintf_calculate_factor(int clock)
 {
 	if (clock < 70000)
@@ -947,6 +1022,24 @@ static const struct mtk_dpi_conf mt8192_conf =3D {
 	.csc_enable_bit =3D CSC_ENABLE,
 };
=20
+static const struct mtk_dpi_conf mt8195_conf =3D {
+	.cal_factor =3D mt8195_calculate_factor,
+	.max_clock_khz =3D 594000,
+	.reg_h_fre_con =3D 0xe0,
+	.output_fmts =3D mt8183_output_fmts,
+	.num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts),
+	.pixels_per_iter =3D 1,
+	.is_ck_de_pol =3D true,
+	.swap_input_support =3D true,
+	.dimension_mask =3D HPW_MASK,
+	.hvsize_mask =3D HSIZE_MASK,
+	.channel_swap_shift =3D CH_SWAP,
+	.yuv422_en_bit =3D YUV422_EN,
+	.csc_enable_bit =3D CSC_ENABLE,
+	.is_internal_hdmi =3D true,
+	.support_direct_pin =3D true,
+};
+
 static const struct mtk_dpi_conf mt8195_dpintf_conf =3D {
 	.cal_factor =3D mt8195_dpintf_calculate_factor,
 	.max_clock_khz =3D 600000,
@@ -1004,6 +1097,12 @@ static int mtk_dpi_probe(struct platform_device *pde=
v)
 		return ret;
 	}
=20
+	dpi->reset_ctl =3D devm_reset_control_get_optional_exclusive(dev, "dpi_on=
");
+	if (IS_ERR(dpi->reset_ctl)) {
+		dev_err(dev, "Failed to get reset_ctl: %ld\n", PTR_ERR(dpi->reset_ctl));
+		return PTR_ERR(dpi->reset_ctl);
+	}
+
 	dpi->engine_clk =3D devm_clk_get(dev, "engine");
 	if (IS_ERR(dpi->engine_clk)) {
 		ret =3D PTR_ERR(dpi->engine_clk);
@@ -1013,7 +1112,26 @@ static int mtk_dpi_probe(struct platform_device *pde=
v)
 		return ret;
 	}
=20
-	dpi->pixel_clk =3D devm_clk_get(dev, "pixel");
+	dpi->hdmi_cg =3D devm_clk_get_optional(dev, "hdmi_cg");
+	if (IS_ERR(dpi->hdmi_cg)) {
+		ret =3D PTR_ERR(dpi->hdmi_cg);
+		if (ret !=3D -EPROBE_DEFER)
+			dev_err(dev, "Failed to get hdmi_cg clock: %d\n", ret);
+
+		return ret;
+	}
+
+	dpi->dpi_ck_cg =3D devm_clk_get_optional(dev, "ck_cg");
+	if (IS_ERR(dpi->dpi_ck_cg)) {
+		ret =3D PTR_ERR(dpi->dpi_ck_cg);
+		if (ret !=3D -EPROBE_DEFER)
+			dev_err(dev, "Failed to get dpi ck cg clock: %d\n",
+				ret);
+
+		return ret;
+	}
+
+	dpi->pixel_clk =3D devm_clk_get_optional(dev, "pixel");
 	if (IS_ERR(dpi->pixel_clk)) {
 		ret =3D PTR_ERR(dpi->pixel_clk);
 		if (ret !=3D -EPROBE_DEFER)
@@ -1022,7 +1140,7 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 		return ret;
 	}
=20
-	dpi->tvd_clk =3D devm_clk_get(dev, "pll");
+	dpi->tvd_clk =3D devm_clk_get_optional(dev, "pll");
 	if (IS_ERR(dpi->tvd_clk)) {
 		ret =3D PTR_ERR(dpi->tvd_clk);
 		if (ret !=3D -EPROBE_DEFER)
@@ -1031,6 +1149,14 @@ static int mtk_dpi_probe(struct platform_device *pde=
v)
 		return ret;
 	}
=20
+	dpi->dpi_sel_clk =3D devm_clk_get_optional(dev, "dpi_sel");
+	if (IS_ERR(dpi->dpi_sel_clk)) {
+		ret =3D PTR_ERR(dpi->dpi_sel_clk);
+		dev_err_probe(dev, ret, "Failed to get dpi_Sel_clk clock: %d\n", ret);
+
+		return ret;
+	}
+
 	dpi->irq =3D platform_get_irq(pdev, 0);
 	if (dpi->irq <=3D 0)
 		return -EINVAL;
@@ -1086,6 +1212,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D=
 {
 	{ .compatible =3D "mediatek,mt8195-dp-intf",
 	  .data =3D &mt8195_dpintf_conf,
 	},
+	{ .compatible =3D "mediatek,mt8195-dpi",
+	  .data =3D &mt8195_conf,
+	},
 	{ },
 };
 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi=
atek/mtk_dpi_regs.h
index 62bd4931b344..653ef4b93a97 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -43,6 +43,11 @@
 #define DPINTF_YUV422_EN		BIT(24)
 #define DPINTF_CSC_ENABLE		BIT(26)
 #define DPINTF_INPUT_2P_EN		BIT(29)
+#define DPI_OUTPUT_1T1P_EN		BIT(24)
+#define DPI_INPUT_2P_EN			BIT(25)
+#define DPI_EXT_VSYNC_EN		BIT(26)
+#define DPI_RGB565_EN			BIT(27)
+#define DPI_RGB880_EN			BIT(28)
=20
 #define DPI_OUTPUT_SETTING	0x14
 #define CH_SWAP				0

--=20
b4 0.10.0-dev