From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 288B0C7EE23 for ; Mon, 22 May 2023 03:55:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231434AbjEVDyu (ORCPT ); Sun, 21 May 2023 23:54:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229600AbjEVDyk (ORCPT ); Sun, 21 May 2023 23:54:40 -0400 Received: from out30-112.freemail.mail.aliyun.com (out30-112.freemail.mail.aliyun.com [115.124.30.112]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33AFCBE; Sun, 21 May 2023 20:54:39 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R101e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045192;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=15;SR=0;TI=SMTPD_---0Vj6oJH4_1684727674; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vj6oJH4_1684727674) by smtp.aliyun-inc.com; Mon, 22 May 2023 11:54:35 +0800 From: Shuai Xue To: chengyou@linux.alibaba.com, kaishen@linux.alibaba.com, helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v5 1/4] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Date: Mon, 22 May 2023 11:54:25 +0800 Message-Id: <20230522035428.69441-2-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Alibaba's T-Head Yitan 710 SoC includes Synopsys' DesignWare Core PCIe controller which implements which implements PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue Reviewed-by: Baolin Wang --- .../admin-guide/perf/dwc_pcie_pmu.rst | 97 +++++++++++++++++++ Documentation/admin-guide/perf/index.rst | 1 + 2 files changed, 98 insertions(+) create mode 100644 Documentation/admin-guide/perf/dwc_pcie_pmu.rst diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentatio= n/admin-guide/perf/dwc_pcie_pmu.rst new file mode 100644 index 000000000000..c1f671cb64ec --- /dev/null +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst @@ -0,0 +1,97 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +DesignWare Cores (DWC) PCIe PMU +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + +The PMU is not a PCIe Root Complex integrated End Point (RCiEP) device but +only PCIe configuration space register block provided by each PCIe Root +Port in a Vendor-Specific Extended Capability named RAS DES (Debug, Error +injection, and Statistics). + +As the name indicated, the RAS DES capability supports system level +debugging, AER error injection, and collection of statistics. To facilitate +collection of statistics, Synopsys DesignWare Cores PCIe controller +provides the following two features: + +- Time Based Analysis (RX/TX data throughput and time spent in each + low-power LTSSM state) +- Lane Event counters (Error and Non-Error for lanes) + +Time Based Analysis +------------------- + +Using this feature you can obtain information regarding RX/TX data +throughput and time spent in each low-power LTSSM state by the controller. + +The counters are 64-bit width and measure data in two categories, + +- percentage of time does the controller stay in LTSSM state in a + configurable duration. The measurement range of each Event in Group#0. +- amount of data processed (Units of 16 bytes). The measurement range of + each Event in Group#1. + +Lane Event counters +------------------- + +Using this feature you can obtain Error and Non-Error information in +specific lane by the controller. + +The counters are 32-bit width and the measured event is select by: + +- Group i +- Event j within the Group i +- and Lane k + +Some of the event counters only exist for specific configurations. + +DesignWare Cores (DWC) PCIe PMU Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver add PMU devices for each PCIe Root Port. And the PMU device is +named based the BDF of Root Port. For example, + + 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) + +the PMU device name for this Root Port is dwc_rootport_3018. + +The DWC PCIe PMU driver registers a perf PMU driver, which provides +description of available events and configuration options in sysfs, see +/sys/bus/event_source/devices/dwc_rootport_{bdf}. + +The "format" directory describes format of the config, fields of the +perf_event_attr structure. The "events" directory provides configuration +templates for all documented events. For example, +"Rx_PCIe_TLP_Data_Payload" is an equivalent of "eventid=3D0x22,type=3D0x1". + +The "perf list" command shall list the available events from sysfs, e.g.:: + + $# perf list | grep dwc_rootport + <...> + dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ [Kernel PMU event] + <...> + dwc_rootport_3018/rx_memory_read,lane=3D?/ [Kernel PMU e= vent] + +Time Based Analysis Event Usage +------------------------------- + +Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: + + $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ + +The average RX/TX bandwidth can be calculated using the following formula: + + PCIe RX Bandwidth =3D PCIE_RX_DATA * 16B / Measure_Time_Window + PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window + +Lane Event Usage +------------------------------- + +Each lane has the same event set and to avoid generating a list of hundreds +of events, the user need to specify the lane ID explicitly, e.g.:: + + $# perf stat -a -e dwc_rootport_3018/rx_memory_read,lane=3D4/ + +The driver does not support sampling, therefore "perf record" will not +work. Per-task (without "-a") perf sessions are not supported. diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 9de64a40adab..11a80cd28a2e 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -19,5 +19,6 @@ Performance monitor support arm_dsu_pmu thunderx2-pmu alibaba_pmu + dwc_pcie_pmu nvidia-pmu meson-ddr-pmu --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BC80ECAAD3 for ; Sat, 17 Sep 2022 12:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229556AbiIQMKq (ORCPT ); Sat, 17 Sep 2022 08:10:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229494AbiIQMKp (ORCPT ); Sat, 17 Sep 2022 08:10:45 -0400 Received: from out30-43.freemail.mail.aliyun.com (out30-43.freemail.mail.aliyun.com [115.124.30.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C9A62B244 for ; Sat, 17 Sep 2022 05:10:43 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R111e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045170;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=10;SR=0;TI=SMTPD_---0VQ-l71H_1663416640; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VQ-l71H_1663416640) by smtp.aliyun-inc.com; Sat, 17 Sep 2022 20:10:41 +0800 From: Shuai Xue To: will@kernel.org, Jonathan.Cameron@Huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v1 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Date: Sat, 17 Sep 2022 20:10:34 +0800 Message-Id: <20220917121036.14864-2-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Alibaba's T-Head Yitan 710 SoC is built on Synopsys' widely deployed and silicon-proven DesignWare Core PCIe controller which implements PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue --- .../admin-guide/perf/dwc_pcie_pmu.rst | 61 +++++++++++++++++++ Documentation/admin-guide/perf/index.rst | 1 + 2 files changed, 62 insertions(+) create mode 100644 Documentation/admin-guide/perf/dwc_pcie_pmu.rst diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentatio= n/admin-guide/perf/dwc_pcie_pmu.rst new file mode 100644 index 000000000000..fbcbf10b23b7 --- /dev/null +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst @@ -0,0 +1,61 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +DesignWare Cores (DWC) PCIe PMU +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + +To facilitate collection of statistics, Synopsys DesignWare Cores PCIe +controller provides the following two features: + +- Time Based Analysis (RX/TX data throughput and time spent in each + low-power LTSSM state) +- Lane Event counters (Error and Non-Error for lanes) + +The PMU is not a PCIe Root Complex integrated End Point (RCiEP) device but +only register counters provided by each PCIe Root Port. + +Time Based Analysis +------------------- + +Using this feature you can obtain information regarding RX/TX data +throughput and time spent in each low-power LTSSM state by the controller. + +The counters are 64-bit width and measure data in two categories, + +- percentage of time does the controller stay in LTSSM state in a + configurable duration. The measurement range of each Event in Group#0. +- amount of data processed (Units of 16 bytes). The measurement range of + each Event in Group#1. + +Lane Event counters +------------------- + +Using this feature you can obtain Error and Non-Error information in +specific lane by the controller. + +The counters are 32-bit width and the measured event is select by: + +- Group i +- Event j within the Group i +- and Lank k + +Some of the event counters only exist for specific configurations. + +DesignWare Cores (DWC) PCIe PMU Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver add PMU devices for each PCIe Root Port. And the PMU device is +named based the BDF of Root Port. For example, + + 10:00.0 PCI bridge: Device 1ded:8000 (rev 01) + +the PMU device name for this Root Port is pcie_bdf_100000. + +Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: + + $# perf stat -a -e pcie_bdf_200/Rx_PCIe_TLP_Data_Payload/ + +average RX bandwidth can be calculated like this: + + PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 9c9ece88ce53..8e6a5472aeb3 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -18,3 +18,4 @@ Performance monitor support xgene-pmu arm_dsu_pmu thunderx2-pmu + dwc_pcie_pmu --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F02A5C77B7A for ; Tue, 16 May 2023 13:01:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233380AbjEPNBb (ORCPT ); Tue, 16 May 2023 09:01:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232963AbjEPNB1 (ORCPT ); Tue, 16 May 2023 09:01:27 -0400 Received: from out30-99.freemail.mail.aliyun.com (out30-99.freemail.mail.aliyun.com [115.124.30.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25EBA10CE; Tue, 16 May 2023 06:01:24 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R741e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045192;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0Vioby0F_1684242079; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vioby0F_1684242079) by smtp.aliyun-inc.com; Tue, 16 May 2023 21:01:20 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v4 1/4] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Date: Tue, 16 May 2023 21:01:07 +0800 Message-Id: <20230516130110.59632-2-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Alibaba's T-Head Yitan 710 SoC is built on Synopsys' widely deployed and silicon-proven DesignWare Core PCIe controller which implements PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue --- .../admin-guide/perf/dwc_pcie_pmu.rst | 61 +++++++++++++++++++ Documentation/admin-guide/perf/index.rst | 1 + 2 files changed, 62 insertions(+) create mode 100644 Documentation/admin-guide/perf/dwc_pcie_pmu.rst diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentatio= n/admin-guide/perf/dwc_pcie_pmu.rst new file mode 100644 index 000000000000..0672e959ebe4 --- /dev/null +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst @@ -0,0 +1,61 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +DesignWare Cores (DWC) PCIe PMU +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + +To facilitate collection of statistics, Synopsys DesignWare Cores PCIe +controller provides the following two features: + +- Time Based Analysis (RX/TX data throughput and time spent in each + low-power LTSSM state) +- Lane Event counters (Error and Non-Error for lanes) + +The PMU is not a PCIe Root Complex integrated End Point (RCiEP) device but +only register counters provided by each PCIe Root Port. + +Time Based Analysis +------------------- + +Using this feature you can obtain information regarding RX/TX data +throughput and time spent in each low-power LTSSM state by the controller. + +The counters are 64-bit width and measure data in two categories, + +- percentage of time does the controller stay in LTSSM state in a + configurable duration. The measurement range of each Event in Group#0. +- amount of data processed (Units of 16 bytes). The measurement range of + each Event in Group#1. + +Lane Event counters +------------------- + +Using this feature you can obtain Error and Non-Error information in +specific lane by the controller. + +The counters are 32-bit width and the measured event is select by: + +- Group i +- Event j within the Group i +- and Lane k + +Some of the event counters only exist for specific configurations. + +DesignWare Cores (DWC) PCIe PMU Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver add PMU devices for each PCIe Root Port. And the PMU device is +named based the BDF of Root Port. For example, + + 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) + +the PMU device name for this Root Port is dwc_rootport_3018. + +Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: + + $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ + +average RX bandwidth can be calculated like this: + + PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 9de64a40adab..11a80cd28a2e 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -19,5 +19,6 @@ Performance monitor support arm_dsu_pmu thunderx2-pmu alibaba_pmu + dwc_pcie_pmu nvidia-pmu meson-ddr-pmu --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EEC8C77B77 for ; Mon, 17 Apr 2023 06:17:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229682AbjDQGRn (ORCPT ); Mon, 17 Apr 2023 02:17:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229598AbjDQGRm (ORCPT ); Mon, 17 Apr 2023 02:17:42 -0400 Received: from out30-113.freemail.mail.aliyun.com (out30-113.freemail.mail.aliyun.com [115.124.30.113]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 381CB2D60; Sun, 16 Apr 2023 23:17:40 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R201e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046050;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0VgDPlGG_1681712257; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VgDPlGG_1681712257) by smtp.aliyun-inc.com; Mon, 17 Apr 2023 14:17:37 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v3 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Date: Mon, 17 Apr 2023 14:17:27 +0800 Message-Id: <20230417061729.84422-2-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Alibaba's T-Head Yitan 710 SoC is built on Synopsys' widely deployed and silicon-proven DesignWare Core PCIe controller which implements PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue --- .../admin-guide/perf/dwc_pcie_pmu.rst | 61 +++++++++++++++++++ Documentation/admin-guide/perf/index.rst | 1 + 2 files changed, 62 insertions(+) create mode 100644 Documentation/admin-guide/perf/dwc_pcie_pmu.rst diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentatio= n/admin-guide/perf/dwc_pcie_pmu.rst new file mode 100644 index 000000000000..0672e959ebe4 --- /dev/null +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst @@ -0,0 +1,61 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +DesignWare Cores (DWC) PCIe PMU +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + +To facilitate collection of statistics, Synopsys DesignWare Cores PCIe +controller provides the following two features: + +- Time Based Analysis (RX/TX data throughput and time spent in each + low-power LTSSM state) +- Lane Event counters (Error and Non-Error for lanes) + +The PMU is not a PCIe Root Complex integrated End Point (RCiEP) device but +only register counters provided by each PCIe Root Port. + +Time Based Analysis +------------------- + +Using this feature you can obtain information regarding RX/TX data +throughput and time spent in each low-power LTSSM state by the controller. + +The counters are 64-bit width and measure data in two categories, + +- percentage of time does the controller stay in LTSSM state in a + configurable duration. The measurement range of each Event in Group#0. +- amount of data processed (Units of 16 bytes). The measurement range of + each Event in Group#1. + +Lane Event counters +------------------- + +Using this feature you can obtain Error and Non-Error information in +specific lane by the controller. + +The counters are 32-bit width and the measured event is select by: + +- Group i +- Event j within the Group i +- and Lane k + +Some of the event counters only exist for specific configurations. + +DesignWare Cores (DWC) PCIe PMU Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver add PMU devices for each PCIe Root Port. And the PMU device is +named based the BDF of Root Port. For example, + + 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) + +the PMU device name for this Root Port is dwc_rootport_3018. + +Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: + + $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ + +average RX bandwidth can be calculated like this: + + PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 9de64a40adab..11a80cd28a2e 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -19,5 +19,6 @@ Performance monitor support arm_dsu_pmu thunderx2-pmu alibaba_pmu + dwc_pcie_pmu nvidia-pmu meson-ddr-pmu --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51A04C77B73 for ; Mon, 10 Apr 2023 03:17:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229445AbjDJDRW (ORCPT ); Sun, 9 Apr 2023 23:17:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229512AbjDJDRP (ORCPT ); Sun, 9 Apr 2023 23:17:15 -0400 Received: from out30-111.freemail.mail.aliyun.com (out30-111.freemail.mail.aliyun.com [115.124.30.111]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E5F72D79; Sun, 9 Apr 2023 20:17:14 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R231e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046049;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0VfeyoDh_1681096629; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VfeyoDh_1681096629) by smtp.aliyun-inc.com; Mon, 10 Apr 2023 11:17:10 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v2 1/3] docs: perf: Add description for Synopsys DesignWare PCIe PMU driver Date: Mon, 10 Apr 2023 11:17:00 +0800 Message-Id: <20230410031702.68355-2-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Alibaba's T-Head Yitan 710 SoC is built on Synopsys' widely deployed and silicon-proven DesignWare Core PCIe controller which implements PMU for performance and functional debugging to facilitate system maintenance. Document it to provide guidance on how to use it. Signed-off-by: Shuai Xue --- .../admin-guide/perf/dwc_pcie_pmu.rst | 61 +++++++++++++++++++ Documentation/admin-guide/perf/index.rst | 1 + 2 files changed, 62 insertions(+) create mode 100644 Documentation/admin-guide/perf/dwc_pcie_pmu.rst diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentatio= n/admin-guide/perf/dwc_pcie_pmu.rst new file mode 100644 index 000000000000..0672e959ebe4 --- /dev/null +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst @@ -0,0 +1,61 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Synopsys DesignWare Cores (DWC) PCIe Performance Monitoring Unit (PMU) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +DesignWare Cores (DWC) PCIe PMU +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + +To facilitate collection of statistics, Synopsys DesignWare Cores PCIe +controller provides the following two features: + +- Time Based Analysis (RX/TX data throughput and time spent in each + low-power LTSSM state) +- Lane Event counters (Error and Non-Error for lanes) + +The PMU is not a PCIe Root Complex integrated End Point (RCiEP) device but +only register counters provided by each PCIe Root Port. + +Time Based Analysis +------------------- + +Using this feature you can obtain information regarding RX/TX data +throughput and time spent in each low-power LTSSM state by the controller. + +The counters are 64-bit width and measure data in two categories, + +- percentage of time does the controller stay in LTSSM state in a + configurable duration. The measurement range of each Event in Group#0. +- amount of data processed (Units of 16 bytes). The measurement range of + each Event in Group#1. + +Lane Event counters +------------------- + +Using this feature you can obtain Error and Non-Error information in +specific lane by the controller. + +The counters are 32-bit width and the measured event is select by: + +- Group i +- Event j within the Group i +- and Lane k + +Some of the event counters only exist for specific configurations. + +DesignWare Cores (DWC) PCIe PMU Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This driver add PMU devices for each PCIe Root Port. And the PMU device is +named based the BDF of Root Port. For example, + + 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) + +the PMU device name for this Root Port is dwc_rootport_3018. + +Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: + + $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ + +average RX bandwidth can be calculated like this: + + PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin= -guide/perf/index.rst index 9de64a40adab..11a80cd28a2e 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -19,5 +19,6 @@ Performance monitor support arm_dsu_pmu thunderx2-pmu alibaba_pmu + dwc_pcie_pmu nvidia-pmu meson-ddr-pmu --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 525F0C77B72 for ; Mon, 17 Apr 2023 06:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229929AbjDQGRs (ORCPT ); Mon, 17 Apr 2023 02:17:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229688AbjDQGRo (ORCPT ); Mon, 17 Apr 2023 02:17:44 -0400 Received: from out30-98.freemail.mail.aliyun.com (out30-98.freemail.mail.aliyun.com [115.124.30.98]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24AE030DC; Sun, 16 Apr 2023 23:17:40 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R561e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046056;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0VgDPlGi_1681712257; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VgDPlGi_1681712257) by smtp.aliyun-inc.com; Mon, 17 Apr 2023 14:17:38 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v3 2/3] drivers/perf: add DesignWare PCIe PMU driver Date: Mon, 17 Apr 2023 14:17:28 +0800 Message-Id: <20230417061729.84422-3-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds the PCIe Performance Monitoring Unit (PMU) driver support for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express Core controller IP which provides statistics feature. The PMU is not a PCIe Root Complex integrated End Point(RCiEP) device but only register counters provided by each PCIe Root Port. To facilitate collection of statistics the controller provides the following two features for each Root Port: - Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) - Event counters (Error and Non-Error for lanes) Note, only one counter for each type and does not overflow interrupt. This driver adds PMU devices for each PCIe Root Port. And the PMU device is named based the BDF of Root Port. For example, 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) the PMU device name for this Root Port is dwc_rootport_3018. Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ average RX bandwidth can be calculated like this: PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window Signed-off-by: Shuai Xue --- drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/dwc_pcie_pmu.c | 855 ++++++++++++++++++++++++++++++++++++ 3 files changed, 863 insertions(+) create mode 100644 drivers/perf/dwc_pcie_pmu.c diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 66c259000a44..57bce3880cba 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -199,6 +199,13 @@ config MARVELL_CN10K_DDR_PMU Enable perf support for Marvell DDR Performance monitoring event on CN10K platform. =20 +config DWC_PCIE_PMU + tristate "Enable Synopsys DesignWare PCIe PMU Support" + depends on ARM64 || (COMPILE_TEST && 64BIT) + help + Enable perf support for Synopsys DesignWare PCIe PMU Performance + monitoring event on Yitian 710 platform. + source "drivers/perf/arm_cspmu/Kconfig" =20 source "drivers/perf/amlogic/Kconfig" diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 13e45da61100..3f233e96524e 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -21,5 +21,6 @@ obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) +=3D marvell_cn10k_ta= d_pmu.o obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) +=3D marvell_cn10k_ddr_pmu.o obj-$(CONFIG_APPLE_M1_CPU_PMU) +=3D apple_m1_cpu_pmu.o obj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) +=3D alibaba_uncore_drw_pmu.o +obj-$(CONFIG_DWC_PCIE_PMU) +=3D dwc_pcie_pmu.o obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) +=3D arm_cspmu/ obj-$(CONFIG_MESON_DDR_PMU) +=3D amlogic/ diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c new file mode 100644 index 000000000000..b7691cfe0df4 --- /dev/null +++ b/drivers/perf/dwc_pcie_pmu.c @@ -0,0 +1,855 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare PCIe PMU driver + * + * Copyright (C) 2021-2023 Alibaba Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define PCI_VENDOR_ID_ALIBABA 0x1ded + +#define ATTRI_NAME_MAX_SIZE 32 +#define DWC_PCIE_VSEC_RAS_DES_ID 0x02 + +#define DWC_PCIE_EVENT_CNT_CTL 0x8 +#define DWC_PCIE_CNT_EVENT_SEL GENMASK(27, 16) +#define DWC_PCIE_CNT_LANE_SEL GENMASK(11, 8) +#define DWC_PCIE_CNT_STATUS BIT(7) +#define DWC_PCIE_CNT_ENABLE GENMASK(4, 2) +#define DWC_PCIE_PER_EVENT_OFF FIELD_PREP(DWC_PCIE_CNT_ENABLE, 0x1) +#define DWC_PCIE_PER_EVENT_ON FIELD_PREP(DWC_PCIE_CNT_ENABLE, 0x3) +#define DWC_PCIE_EVENT_CLEAR GENMASK(1, 0) +#define DWC_PCIE_EVENT_PER_CLEAR 0x1 + +#define DWC_PCIE_EVENT_CNT_DATA 0xC + +#define DWC_PCIE_TIME_BASED_ANAL_CTL 0x10 +#define DWC_PCIE_TIME_BASED_REPORT_SEL GENMASK(31, 24) +#define DWC_PCIE_TIME_BASED_DURATION_SEL GENMASK(15, 8) +#define DWC_PCIE_DURATION_MANUAL_CTL 0x0 +#define DWC_PCIE_DURATION_1MS 0x1 +#define DWC_PCIE_DURATION_10MS 0x2 +#define DWC_PCIE_DURATION_100MS 0x3 +#define DWC_PCIE_DURATION_1S 0x4 +#define DWC_PCIE_DURATION_2S 0x5 +#define DWC_PCIE_DURATION_4S 0x6 +#define DWC_PCIE_DURATION_4US 0xff +#define DWC_PCIE_TIME_BASED_TIMER_START BIT(0) +#define DWC_PCIE_TIME_BASED_CNT_ENABLE 0x1 + +#define DWC_PCIE_TIME_BASED_ANAL_DATA_REG_LOW 0x14 +#define DWC_PCIE_TIME_BASED_ANAL_DATA_REG_HIGH 0x18 + +/* Event attributes */ +#define DWC_PCIE_CONFIG_EVENTID GENMASK(15, 0) +#define DWC_PCIE_CONFIG_TYPE GENMASK(19, 16) +#define DWC_PCIE_CONFIG_LANE GENMASK(27, 20) + +#define DWC_PCIE_EVENT_ID(event) FIELD_GET(DWC_PCIE_CONFIG_EVENTID, (event= )->attr.config) +#define DWC_PCIE_EVENT_TYPE(event) FIELD_GET(DWC_PCIE_CONFIG_TYPE, (event)= ->attr.config) +#define DWC_PCIE_EVENT_LANE(event) FIELD_GET(DWC_PCIE_CONFIG_LANE, (event)= ->attr.config) + +enum dwc_pcie_event_type { + DWC_PCIE_TYPE_INVALID, + DWC_PCIE_TIME_BASE_EVENT, + DWC_PCIE_LANE_EVENT, +}; + +struct dwc_event_counters { + const char name[32]; + u32 event_id; +}; + +struct dwc_pcie_pmu { + struct hlist_node node; + unsigned int on_cpu; + struct pmu pmu; + struct device *dev; +}; + +struct dwc_pcie_rp_info { + u32 bdf; + u32 ras_des; + u32 num_lanes; + + struct list_head rp_node; + struct pci_dev *pdev; + struct dwc_pcie_pmu pcie_pmu; + bool pmu_is_register; + struct perf_event *event; + + struct dwc_pcie_event_attr *lane_event_attrs; + struct attribute **pcie_pmu_event_attrs; + struct attribute_group pcie_pmu_event_attrs_group; + const struct attribute_group *pcie_pmu_attr_groups[4]; +}; + +struct dwc_pcie_pmu_priv { + struct device *dev; + u32 pcie_ctrl_num; + struct list_head rp_infos; +}; + +#define to_dwc_pcie_pmu(p) (container_of(p, struct dwc_pcie_pmu, pmu)) + +static struct platform_device *dwc_pcie_pmu_dev; +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(pcie_pmu->on_cpu)); +} +static DEVICE_ATTR_RO(cpumask); + +static struct attribute *dwc_pcie_pmu_cpumask_attrs[] =3D { + &dev_attr_cpumask.attr, + NULL +}; + +static struct attribute_group pcie_pmu_cpumask_attrs_group =3D { + .attrs =3D dwc_pcie_pmu_cpumask_attrs, +}; + +struct dwc_pcie_format_attr { + struct device_attribute attr; + u64 field; + int config; +}; + +static ssize_t dwc_pcie_pmu_format_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_format_attr *fmt =3D container_of(attr, typeof(*fmt), att= r); + int lo =3D __ffs(fmt->field), hi =3D __fls(fmt->field); + + if (lo =3D=3D hi) + return snprintf(buf, PAGE_SIZE, "config:%d\n", lo); + + if (!fmt->config) + return snprintf(buf, PAGE_SIZE, "config:%d-%d\n", lo, hi); + + return snprintf(buf, PAGE_SIZE, "config%d:%d-%d\n", fmt->config, lo, + hi); +} + +#define _dwc_pcie_format_attr(_name, _cfg, _fld) \ + (&((struct dwc_pcie_format_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_pmu_format_show, NULL), \ + .config =3D _cfg, \ + .field =3D _fld, \ + }})[0].attr.attr) + +#define dwc_pcie_format_attr(_name, _fld) _dwc_pcie_format_attr(_name, 0, = _fld) + +static struct attribute *dwc_pcie_format_attrs[] =3D { + dwc_pcie_format_attr(type, DWC_PCIE_CONFIG_TYPE), + dwc_pcie_format_attr(eventid, DWC_PCIE_CONFIG_EVENTID), + dwc_pcie_format_attr(lane, DWC_PCIE_CONFIG_LANE), + NULL, +}; + +static struct attribute_group pcie_pmu_format_attrs_group =3D { + .name =3D "format", + .attrs =3D dwc_pcie_format_attrs, +}; + +struct dwc_pcie_event_attr { + struct device_attribute attr; + enum dwc_pcie_event_type type; + u16 eventid; + u8 lane; +}; + +static ssize_t dwc_pcie_event_show(struct device *dev, + struct device_attribute *attr, char *page) +{ + struct dwc_pcie_event_attr *eattr; + + eattr =3D container_of(attr, typeof(*eattr), attr); + + if (eattr->type =3D=3D DWC_PCIE_LANE_EVENT) + return sprintf(page, "eventid=3D0x%lx, type=3D0x%lx, lane=3D0x%lx\n", + (unsigned long)eattr->eventid, + (unsigned long)eattr->type, + (unsigned long)eattr->lane); + + return sprintf(page, "eventid=3D0x%lx, type=3D0x%lx", + (unsigned long)eattr->eventid, + (unsigned long)eattr->type); +} + +#define DWC_PCIE_EVENT_ATTR(_name, _type, _eventid, _lane) \ + (&((struct dwc_pcie_event_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_event_show, NULL), \ + .type =3D _type, \ + .eventid =3D _eventid, \ + .lane =3D _lane, \ + }})[0].attr.attr) + +#define DWC_PCIE_PMU_BASE_TIME_ATTR(_name, _eventid) \ + DWC_PCIE_EVENT_ATTR(_name, DWC_PCIE_TIME_BASE_EVENT, _eventid, 0) + +static struct attribute *dwc_pcie_pmu_time_event_attrs[] =3D { + /* Group #0 */ + DWC_PCIE_PMU_BASE_TIME_ATTR(one_cycle, 0x00), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_L0S, 0x01), + DWC_PCIE_PMU_BASE_TIME_ATTR(RX_L0S, 0x02), + DWC_PCIE_PMU_BASE_TIME_ATTR(L0, 0x03), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1, 0x04), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_1, 0x05), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_2, 0x06), + DWC_PCIE_PMU_BASE_TIME_ATTR(CFG_RCVRY, 0x07), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_RX_L0S, 0x08), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_AUX, 0x09), + DWC_PCIE_PMU_BASE_TIME_ATTR(ONE_cycle, 0x10), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_L0S_, 0x11), + DWC_PCIE_PMU_BASE_TIME_ATTR(RX_L0S_, 0x12), + DWC_PCIE_PMU_BASE_TIME_ATTR(L0_, 0x13), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_, 0x17), + DWC_PCIE_PMU_BASE_TIME_ATTR(CFG_RCVRY_, 0x17), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_RX_L0S_, 0x18), + /* Group #1 */ + DWC_PCIE_PMU_BASE_TIME_ATTR(Tx_PCIe_TLP_Data_Payload, 0x20), + DWC_PCIE_PMU_BASE_TIME_ATTR(Rx_PCIe_TLP_Data_Payload, 0x21), + DWC_PCIE_PMU_BASE_TIME_ATTR(Tx_CCIX_TLP_Data_Payload, 0x22), + DWC_PCIE_PMU_BASE_TIME_ATTR(Rx_CCIX_TLP_Data_Payload, 0x23), + NULL +}; + +static inline umode_t pcie_pmu_event_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unuse) +{ + return attr->mode; +} + +static inline bool pci_dev_is_rootport(struct pci_dev *pdev) +{ + return (pci_is_pcie(pdev) && + pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT); +} + +static int dwc_pcie_ras_des_discover(struct dwc_pcie_pmu_priv *priv) +{ + int index =3D 0; + struct pci_dev *pdev =3D NULL; + struct dwc_pcie_rp_info *rp_info; + + INIT_LIST_HEAD(&priv->rp_infos); + + /* Match the rootport with VSEC_RAS_DES_ID */ + for_each_pci_dev(pdev) { + u16 vsec; + u32 val; + + if (!pci_dev_is_rootport(pdev)) + continue; + + rp_info =3D devm_kzalloc(&pdev->dev, sizeof(*rp_info), GFP_KERNEL); + if (!rp_info) + return -ENOMEM; + + rp_info->bdf =3D PCI_DEVID(pdev->bus->number, pdev->devfn); + rp_info->pdev =3D pdev; + + vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_ALIBABA, + DWC_PCIE_VSEC_RAS_DES_ID); + if (!vsec) + continue; + + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); + if (PCI_VNDR_HEADER_REV(val) !=3D 0x04 || + PCI_VNDR_HEADER_LEN(val) !=3D 0x100) + continue; + pci_dbg(pdev, + "Detected PCIe Vendor-Specific Extended Capability RAS DES\n"); + + rp_info->ras_des =3D vsec; + rp_info->num_lanes =3D pcie_get_width_cap(pdev); + + list_add(&rp_info->rp_node, &priv->rp_infos); + index++; + } + + if (!index) + return -ENODEV; + + priv->pcie_ctrl_num =3D index; + + return 0; +} + +static void dwc_pcie_pmu_set_event_id(struct pci_dev *pdev, u16 ras_des, + int event_id) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + val |=3D FIELD_PREP(DWC_PCIE_CNT_EVENT_SEL, event_id); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_write_event_lane(struct pci_dev *pdev, u16 ras_de= s, + int lane, int event_id) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + val |=3D FIELD_PREP(DWC_PCIE_CNT_EVENT_SEL, lane); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_event_enable(struct pci_dev *pdev, u16 ras_des, + u32 enable) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + if (enable) + val |=3D FIELD_PREP(DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_ON); + else + val |=3D FIELD_PREP(DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_OFF); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_base_time_enable(struct pci_dev *pdev, u16 ras_de= s, + u32 enable) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + &val); + + if (enable) + val |=3D DWC_PCIE_TIME_BASED_CNT_ENABLE; + else + val &=3D ~DWC_PCIE_TIME_BASED_CNT_ENABLE; + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + val); +} + +static void dwc_pcie_pmu_read_event_counter(struct pci_dev *pdev, u16 ras_= des, + u64 *counter) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_DATA, &val); + *counter =3D val; +} + +/* The results are cleared when next measurement starts. */ +static void dwc_pcie_pmu_read_base_time_counter(struct pci_dev *pdev, + u16 ras_des, u64 *counter) +{ + u32 val; + + pci_read_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_DATA_REG_HIGH, + &val); + *counter =3D val; + *counter <<=3D 32; + + pci_read_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_DATA_REG_LOW, + &val); + + *counter +=3D val; +} + +static void dwc_pcie_pmu_clear_event_counter(struct pci_dev *pdev, u16 ras= _des) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + val |=3D FIELD_PREP(DWC_PCIE_EVENT_CLEAR, DWC_PCIE_EVENT_PER_CLEAR); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_base_time_add_prepare(struct pci_dev *pdev, + u16 ras_des, u32 event_id) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + &val); + + val |=3D FIELD_PREP(DWC_PCIE_TIME_BASED_REPORT_SEL, event_id); + + /* + * TIME_BASED_ANAL_DATA_REG is a 64 bit register, we can safely + * use it with any manually controlled duration. + */ + val |=3D FIELD_PREP(DWC_PCIE_TIME_BASED_DURATION_SEL, + DWC_PCIE_DURATION_MANUAL_CTL); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + val); +} + +static struct dwc_pcie_rp_info *pmu_to_pcie_info(struct pmu *pmu) +{ + struct dwc_pcie_rp_info *rp_info; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(pmu); + + rp_info =3D container_of(pcie_pmu, struct dwc_pcie_rp_info, pcie_pmu); + + return rp_info; +} + +static void dwc_pcie_pmu_event_update(struct perf_event *event) +{ + u64 counter; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + struct pci_dev *pdev =3D rp_info->pdev; + u16 ras_des =3D rp_info->ras_des; + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + u64 delta, prev, now; + + do { + prev =3D local64_read(&hwc->prev_count); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_read_event_counter(pdev, ras_des, &counter); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_read_base_time_counter(pdev, ras_des, + &counter); + else + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); + + now =3D counter; + } while (local64_cmpxchg(&hwc->prev_count, prev, now) !=3D prev); + + delta =3D now - prev; + + local64_add(delta, &event->count); +} + +static int dwc_pcie_pmu_event_init(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct perf_event *sibling; + + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + if (hwc->sample_period) { + dev_err(pcie_pmu->dev, "Sampling not supported\n"); + return -EOPNOTSUPP; + } + + if (event->cpu < 0) { + dev_err(pcie_pmu->dev, "Per-task mode not supported\n"); + return -EOPNOTSUPP; + } + + event->cpu =3D pcie_pmu->on_cpu; + + if (event->group_leader !=3D event && + !is_software_event(event->group_leader)) + return -EINVAL; + + for_each_sibling_event(sibling, event->group_leader) { + if (sibling !=3D event && !is_software_event(sibling)) + return -EINVAL; + } + + hwc->idx =3D -1; + + return 0; +} + +static void dwc_pcie_pmu_set_period(struct hw_perf_event *hwc) +{ + local64_set(&hwc->prev_count, 0); +} + +static void dwc_pcie_pmu_event_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + struct pci_dev *pdev =3D rp_info->pdev; + u16 ras_des =3D rp_info->ras_des; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + + hwc->state =3D 0; + dwc_pcie_pmu_set_period(hwc); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_event_enable(pdev, ras_des, 1); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_base_time_enable(pdev, ras_des, 1); + else + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); +} + +static void dwc_pcie_pmu_event_stop(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + struct pci_dev *pdev =3D rp_info->pdev; + u16 ras_des =3D rp_info->ras_des; + + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + + if (event->hw.state & PERF_HES_STOPPED) + return; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_event_enable(pdev, ras_des, 0); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_base_time_enable(pdev, ras_des, 0); + else + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); + + dwc_pcie_pmu_event_update(event); +} + +static int dwc_pcie_pmu_event_add(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + struct pci_dev *pdev =3D rp_info->pdev; + u16 ras_des =3D rp_info->ras_des; + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + int event_id =3D DWC_PCIE_EVENT_ID(event); + int lane =3D DWC_PCIE_EVENT_LANE(event); + + /* Only one counter and it is in use */ + if (rp_info->event) + return -ENOSPC; + + rp_info->event =3D event; + + hwc->state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) { + dwc_pcie_pmu_event_enable(pdev, ras_des, 0); + dwc_pcie_pmu_write_event_lane(pdev, ras_des, lane, event_id); + dwc_pcie_pmu_set_event_id(pdev, ras_des, event_id); + dwc_pcie_pmu_clear_event_counter(pdev, ras_des); + } else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) { + dwc_pcie_pmu_base_time_enable(pdev, ras_des, 0); + dwc_pcie_pmu_base_time_add_prepare(pdev, ras_des, event_id); + } else { + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); + return -EINVAL; + } + + if (flags & PERF_EF_START) + dwc_pcie_pmu_event_start(event, PERF_EF_RELOAD); + + perf_event_update_userpage(event); + + return 0; +} + +static void dwc_pcie_pmu_event_del(struct perf_event *event, int flags) +{ + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + + dwc_pcie_pmu_event_stop(event, flags | PERF_EF_UPDATE); + perf_event_update_userpage(event); + rp_info->event =3D NULL; +} + +static void dwc_pcie_pmu_event_read(struct perf_event *event) +{ + dwc_pcie_pmu_event_update(event); +} + +static struct dwc_event_counters event_array[] =3D { + {"tx_ack_dllp", 0x600}, + {"tx_update_fc_dllp", 0x601}, + {"rx_ack_dllp", 0x602}, + {"rx_update_fc_dllp", 0x603}, + {"rx_nulified_tlp", 0x604}, + {"tx_nulified_tlp", 0x605}, + {"rx_duplicate_tlp", 0x606}, + {"tx_memory_write", 0x700}, + {"tx_memory_read", 0x701}, + {"tx_configuration_write", 0x702}, + {"tx_configuration_read", 0x703}, + {"tx_io_write", 0x704}, + {"tx_io_read", 0x705}, + {"tx_completion_without_data", 0x706}, + {"tx_completion_with_data", 0x707}, + {"tx_message_tlp", 0x708}, + {"tx_atomic", 0x709}, + {"tx_tlp_with_prefix", 0x70A}, + {"rx_memory_write", 0x70B}, + {"rx_memory_read", 0x70C}, + {"rx_io_write", 0x70F}, + {"rx_io_read", 0x710}, + {"rx_completion_without_data", 0x711}, + {"rx_completion_with_data", 0x712}, + {"rx_message_tlp", 0x713}, + {"rx_atomic", 0x714}, + {"rx_tlp_with_prefix", 0x715}, + {"tx_ccix_tlp", 0x716}, + {"rx_ccix_tlp", 0x717}, +}; + +static int dwc_pcie_pmu_attr_init(struct dwc_pcie_pmu_priv *priv, + struct dwc_pcie_rp_info *rp_info) +{ + int i, j; + char lane[8]; + const char tmp[64]; + int events_per_lane; + int num_lane_events; + int time_base_count; + int num_attrs, attr_idx; + struct dwc_pcie_event_attr *lane_attrs; + struct attribute **pmu_attrs; + + memset((void *)tmp, 0, sizeof(tmp)); + memset((void *)lane, 0, sizeof(lane)); + time_base_count =3D ARRAY_SIZE(dwc_pcie_pmu_time_event_attrs); + events_per_lane =3D ARRAY_SIZE(event_array); + num_lane_events =3D rp_info->num_lanes * events_per_lane; + num_attrs =3D time_base_count + num_lane_events; + + rp_info->lane_event_attrs =3D + devm_kcalloc(priv->dev, num_lane_events, + sizeof(struct dwc_pcie_event_attr), + GFP_KERNEL); + if (!rp_info->lane_event_attrs) + return -ENOMEM; + lane_attrs =3D rp_info->lane_event_attrs; + rp_info->pcie_pmu_event_attrs =3D + devm_kcalloc(priv->dev, num_attrs, sizeof(struct attribute *), + GFP_KERNEL); + if (!rp_info->pcie_pmu_event_attrs) + return -ENOMEM; + pmu_attrs =3D rp_info->pcie_pmu_event_attrs; + + for (i =3D 0; i < num_lane_events; i++) { + lane_attrs[i].attr.attr.name =3D + devm_kzalloc(priv->dev, sizeof(char) + * ATTRI_NAME_MAX_SIZE, GFP_KERNEL); + if (!lane_attrs[i].attr.attr.name) + return -ENOMEM; + } + + attr_idx =3D 0; + for (i =3D 0; i < rp_info->num_lanes; i++) { + sprintf(lane, "_lane%d", i); + + for (j =3D 0; j < events_per_lane; j++) { + int pos =3D i * events_per_lane + j; + + strcat((char *)tmp, event_array[j].name); + strcat((char *)tmp, lane); + memcpy((void *)lane_attrs[pos].attr.attr.name, + (void *)tmp, + sizeof(tmp)); + + lane_attrs[pos].attr.attr.mode =3D + VERIFY_OCTAL_PERMISSIONS(0444); + lane_attrs[pos].attr.show =3D dwc_pcie_event_show; + lane_attrs[pos].attr.store =3D NULL; + lane_attrs[pos].type =3D DWC_PCIE_LANE_EVENT; + lane_attrs[pos].eventid =3D event_array[j].event_id; + lane_attrs[pos].lane =3D i; + pmu_attrs[attr_idx++] =3D &lane_attrs[pos].attr.attr; + + memset((void *)tmp, 0, sizeof(tmp)); + } + } + + for (i =3D 0; i < ARRAY_SIZE(dwc_pcie_pmu_time_event_attrs); i++) + pmu_attrs[attr_idx++] =3D dwc_pcie_pmu_time_event_attrs[i]; + + rp_info->pcie_pmu_event_attrs[attr_idx++] =3D NULL; + + rp_info->pcie_pmu_event_attrs_group.name =3D "events"; + rp_info->pcie_pmu_event_attrs_group.is_visible =3D + pcie_pmu_event_attr_is_visible; + rp_info->pcie_pmu_event_attrs_group.attrs =3D + rp_info->pcie_pmu_event_attrs; + + rp_info->pcie_pmu_attr_groups[0] =3D + &rp_info->pcie_pmu_event_attrs_group; + rp_info->pcie_pmu_attr_groups[1] =3D &pcie_pmu_format_attrs_group; + rp_info->pcie_pmu_attr_groups[2] =3D &pcie_pmu_cpumask_attrs_group; + rp_info->pcie_pmu_attr_groups[3] =3D NULL; + + return 0; +} + +static int __dwc_pcie_pmu_probe(struct dwc_pcie_pmu_priv *priv, + struct dwc_pcie_rp_info *rp_info) +{ + struct dwc_pcie_pmu *pcie_pmu; + struct device *dev; + char *name; + int ret; + + pcie_pmu =3D &rp_info->pcie_pmu; + dev =3D &rp_info->pdev->dev; + + ret =3D dwc_pcie_pmu_attr_init(priv, rp_info); + if (ret) { + pci_err(rp_info->pdev, "PMU attr init fail ret=3D%d\n", ret); + return ret; + } + + pcie_pmu->dev =3D dev; + pcie_pmu->pmu =3D (struct pmu) { + .module =3D THIS_MODULE, + .task_ctx_nr =3D perf_invalid_context, + .pmu_enable =3D NULL, + .pmu_disable =3D NULL, + .event_init =3D dwc_pcie_pmu_event_init, + .add =3D dwc_pcie_pmu_event_add, + .del =3D dwc_pcie_pmu_event_del, + .start =3D dwc_pcie_pmu_event_start, + .stop =3D dwc_pcie_pmu_event_stop, + .read =3D dwc_pcie_pmu_event_read, + .attr_groups =3D rp_info->pcie_pmu_attr_groups, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + }; + + name =3D devm_kasprintf(priv->dev, GFP_KERNEL, "dwc_rootport_%x", + rp_info->bdf); + if (!name) + return -ENOMEM; + + /* + * Pick one CPU to be the preferred one on local NUMA node. + * + * Note, this PMU does NOT support interrupt, set on_cpu to indicate it + * is a uncore PMU device. + */ + pcie_pmu->on_cpu =3D cpumask_local_spread(0, dev_to_node(pcie_pmu->dev)); + ret =3D perf_pmu_register(&pcie_pmu->pmu, name, -1); + if (ret) { + pci_err(rp_info->pdev, "Error %d registering PMU @%x\n", ret, + rp_info->bdf); + return ret; + } + + rp_info->pmu_is_register =3D true; + + return 0; +} + +static int dwc_pcie_pmu_remove(struct platform_device *pdev) +{ + struct dwc_pcie_pmu_priv *priv =3D platform_get_drvdata(pdev); + struct dwc_pcie_pmu *pcie_pmu; + struct dwc_pcie_rp_info *rp_info; + + list_for_each_entry(rp_info, &priv->rp_infos, rp_node) { + if (rp_info->pmu_is_register) { + pcie_pmu =3D &rp_info->pcie_pmu; + perf_pmu_unregister(&pcie_pmu->pmu); + } + } + return 0; +} + +static int dwc_pcie_pmu_probe(struct platform_device *pdev) +{ + int ret; + struct dwc_pcie_pmu_priv *priv; + struct dwc_pcie_rp_info *rp_info; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D &pdev->dev; + platform_set_drvdata(pdev, priv); + + /* If RAS_DES PMU is not supported on current platform, keep silent */ + ret =3D dwc_pcie_ras_des_discover(priv); + if (ret) + return ret; + + list_for_each_entry(rp_info, &priv->rp_infos, rp_node) { + struct pci_dev *rp =3D rp_info->pdev; + + ret =3D __dwc_pcie_pmu_probe(priv, rp_info); + if (ret) { + dev_err(&rp->dev, "PCIe PMU probe fail\n"); + goto pmu_unregister; + } + } + + return 0; + +pmu_unregister: + dwc_pcie_pmu_remove(pdev); + + return ret; +} + +static struct platform_driver dwc_pcie_pmu_driver =3D { + .probe =3D dwc_pcie_pmu_probe, + .remove =3D dwc_pcie_pmu_remove, + .driver =3D {.name =3D "dwc_pcie_pmu",}, +}; + +static int __init dwc_pcie_pmu_init(void) +{ + int ret; + + ret =3D platform_driver_register(&dwc_pcie_pmu_driver); + + if (ret) + return ret; + + dwc_pcie_pmu_dev =3D platform_device_register_simple( + "dwc_pcie_pmu", PLATFORM_DEVID_NONE, NULL, 0); + if (IS_ERR(dwc_pcie_pmu_dev)) { + platform_driver_unregister(&dwc_pcie_pmu_driver); + return PTR_ERR(dwc_pcie_pmu_dev); + } + + return 0; +} + +static void __exit dwc_pcie_pmu_exit(void) +{ + platform_device_unregister(dwc_pcie_pmu_dev); + platform_driver_unregister(&dwc_pcie_pmu_driver); +} + +module_init(dwc_pcie_pmu_init); +module_exit(dwc_pcie_pmu_exit); + +MODULE_DESCRIPTION("PMU driver for DesignWare Cores PCI Express Controller= "); +MODULE_AUTHOR("Shuai xue "); +MODULE_AUTHOR("Wen Cheng "); +MODULE_LICENSE("GPL v2"); --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6930C76196 for ; Mon, 10 Apr 2023 03:17:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229592AbjDJDR1 (ORCPT ); Sun, 9 Apr 2023 23:17:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229663AbjDJDRS (ORCPT ); Sun, 9 Apr 2023 23:17:18 -0400 Received: from out30-98.freemail.mail.aliyun.com (out30-98.freemail.mail.aliyun.com [115.124.30.98]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 422B63AA1; Sun, 9 Apr 2023 20:17:15 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R381e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046056;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0VfeyoEX_1681096631; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VfeyoEX_1681096631) by smtp.aliyun-inc.com; Mon, 10 Apr 2023 11:17:12 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v2 2/3] drivers/perf: add DesignWare PCIe PMU driver Date: Mon, 10 Apr 2023 11:17:01 +0800 Message-Id: <20230410031702.68355-3-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds the PCIe Performance Monitoring Unit (PMU) driver support for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express Core controller IP which provides statistics feature. The PMU is not a PCIe Root Complex integrated End Point(RCiEP) device but only register counters provided by each PCIe Root Port. To facilitate collection of statistics the controller provides the following two features for each Root Port: - Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) - Event counters (Error and Non-Error for lanes) Note, only one counter for each type and does not overflow interrupt. This driver adds PMU devices for each PCIe Root Port. And the PMU device is named based the BDF of Root Port. For example, 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) the PMU device name for this Root Port is dwc_rootport_3018. Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ average RX bandwidth can be calculated like this: PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window Signed-off-by: Shuai Xue --- drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/dwc_pcie_pmu.c | 877 ++++++++++++++++++++++++++++++++++++ 3 files changed, 885 insertions(+) create mode 100644 drivers/perf/dwc_pcie_pmu.c diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 66c259000a44..57bce3880cba 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -199,6 +199,13 @@ config MARVELL_CN10K_DDR_PMU Enable perf support for Marvell DDR Performance monitoring event on CN10K platform. =20 +config DWC_PCIE_PMU + tristate "Enable Synopsys DesignWare PCIe PMU Support" + depends on ARM64 || (COMPILE_TEST && 64BIT) + help + Enable perf support for Synopsys DesignWare PCIe PMU Performance + monitoring event on Yitian 710 platform. + source "drivers/perf/arm_cspmu/Kconfig" =20 source "drivers/perf/amlogic/Kconfig" diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 13e45da61100..3f233e96524e 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -21,5 +21,6 @@ obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) +=3D marvell_cn10k_ta= d_pmu.o obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) +=3D marvell_cn10k_ddr_pmu.o obj-$(CONFIG_APPLE_M1_CPU_PMU) +=3D apple_m1_cpu_pmu.o obj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) +=3D alibaba_uncore_drw_pmu.o +obj-$(CONFIG_DWC_PCIE_PMU) +=3D dwc_pcie_pmu.o obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) +=3D arm_cspmu/ obj-$(CONFIG_MESON_DDR_PMU) +=3D amlogic/ diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c new file mode 100644 index 000000000000..c8c09f120d4e --- /dev/null +++ b/drivers/perf/dwc_pcie_pmu.c @@ -0,0 +1,877 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare PCIe PMU driver + * + * Copyright (C) 2021, 2022 Alibaba Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define PCI_VENDOR_ID_ALIBABA 0x1ded + +#define ATTRI_NAME_MAX_SIZE 32 +#define DWC_PCIE_VSEC_RAS_DES_ID 0x02 + +#define DWC_PCIE_EVENT_CNT_CTL 0x8 +#define DWC_PCIE_CNT_EVENT_SEL GENMASK(27, 16) +#define DWC_PCIE_CNT_LANE_SEL GENMASK(11, 8) +#define DWC_PCIE_CNT_STATUS BIT(7) +#define DWC_PCIE_CNT_ENABLE GENMASK(4, 2) +#define DWC_PCIE_PER_EVENT_OFF FIELD_PREP(DWC_PCIE_CNT_ENABLE, 0x1) +#define DWC_PCIE_PER_EVENT_ON FIELD_PREP(DWC_PCIE_CNT_ENABLE, 0x3) +#define DWC_PCIE_EVENT_CLEAR GENMASK(1, 0) +#define DWC_PCIE_EVENT_PER_CLEAR 0x1 + +#define DWC_PCIE_EVENT_CNT_DATA 0xC + +#define DWC_PCIE_TIME_BASED_ANAL_CTL 0x10 +#define DWC_PCIE_TIME_BASED_REPORT_SEL GENMASK(31, 24) +#define DWC_PCIE_TIME_BASED_DURATION_SEL GENMASK(15, 8) +#define DWC_PCIE_DURATION_MANUAL_CTL 0x0 +#define DWC_PCIE_DURATION_1MS 0x1 +#define DWC_PCIE_DURATION_10MS 0x2 +#define DWC_PCIE_DURATION_100MS 0x3 +#define DWC_PCIE_DURATION_1S 0x4 +#define DWC_PCIE_DURATION_2S 0x5 +#define DWC_PCIE_DURATION_4S 0x6 +#define DWC_PCIE_DURATION_4US 0xff +#define DWC_PCIE_TIME_BASED_CNT_ENABLE 0x1 + +#define DWC_PCIE_TIME_BASED_ANAL_DATA_REG_LOW 0x14 +#define DWC_PCIE_TIME_BASED_ANAL_DATA_REG_HIGH 0x18 + +/* Event attributes */ +#define DWC_PCIE_CONFIG_EVENTID GENMASK(15, 0) +#define DWC_PCIE_CONFIG_TYPE GENMASK(19, 16) +#define DWC_PCIE_CONFIG_LANE GENMASK(27, 20) + +#define DWC_PCIE_EVENT_ID(event) FIELD_GET(DWC_PCIE_CONFIG_EVENTID, (event= )->attr.config) +#define DWC_PCIE_EVENT_TYPE(event) FIELD_GET(DWC_PCIE_CONFIG_TYPE, (event)= ->attr.config) +#define DWC_PCIE_EVENT_LANE(event) FIELD_GET(DWC_PCIE_CONFIG_LANE, (event)= ->attr.config) + +#define DWC_PCIE_PMU_HAS_REGISTER 1 + +enum dwc_pcie_event_type { + DWC_PCIE_TYPE_INVALID, + DWC_PCIE_TIME_BASE_EVENT, + DWC_PCIE_LANE_EVENT, +}; + +struct dwc_event_counters { + const char name[32]; + u32 event_id; +}; + +struct dwc_pcie_pmu { + struct hlist_node node; + unsigned int on_cpu; + struct pmu pmu; + struct device *dev; +}; + +struct dwc_pcie_rp_info { + u32 bdf; + u32 ras_des; + u32 num_lanes; + + struct list_head rp_node; + struct pci_dev *pdev; + struct dwc_pcie_pmu pcie_pmu; + u8 pmu_is_register; + struct perf_event *event; + + struct dwc_pcie_event_attr *lane_event_attrs; + struct attribute **pcie_pmu_event_attrs; + struct attribute_group pcie_pmu_event_attrs_group; + const struct attribute_group *pcie_pmu_attr_groups[4]; +}; + +struct dwc_pcie_pmu_priv { + struct device *dev; + u32 pcie_ctrl_num; + struct list_head rp_infos; +}; + +#define to_dwc_pcie_pmu(p) (container_of(p, struct dwc_pcie_pmu, pmu)) + +static struct platform_device *dwc_pcie_pmu_dev; +static char *event_attr_name =3D "events"; + +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(pcie_pmu->on_cpu)); +} +static DEVICE_ATTR_RO(cpumask); + +#define DEVICE_ATTR_RO(_name) \ + struct device_attribute dev_attr_##_name =3D __ATTR_RO(_name) +#define __ATTR_RO(_name) { \ + .attr =3D { .name =3D __stringify(_name), .mode =3D 0444 }, \ + .show =3D _name##_show, \ +} +#define __ATTR(_name, _mode, _show, _store) { \ + .attr =3D {.name =3D __stringify(_name), \ + .mode =3D VERIFY_OCTAL_PERMISSIONS(_mode) }, \ + .show =3D _show, \ + .store =3D _store, \ +} + +static struct attribute *dwc_pcie_pmu_cpumask_attrs[] =3D { + &dev_attr_cpumask.attr, + NULL +}; + +static struct attribute_group pcie_pmu_cpumask_attrs_group =3D { + .attrs =3D dwc_pcie_pmu_cpumask_attrs, +}; + +struct dwc_pcie_format_attr { + struct device_attribute attr; + u64 field; + int config; +}; + +static ssize_t dwc_pcie_pmu_format_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_format_attr *fmt =3D container_of(attr, typeof(*fmt), att= r); + int lo =3D __ffs(fmt->field), hi =3D __fls(fmt->field); + + if (lo =3D=3D hi) + return snprintf(buf, PAGE_SIZE, "config:%d\n", lo); + + if (!fmt->config) + return snprintf(buf, PAGE_SIZE, "config:%d-%d\n", lo, hi); + + return snprintf(buf, PAGE_SIZE, "config%d:%d-%d\n", fmt->config, lo, + hi); +} + +#define _dwc_pcie_format_attr(_name, _cfg, _fld) \ + (&((struct dwc_pcie_format_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_pmu_format_show, NULL), \ + .config =3D _cfg, \ + .field =3D _fld, \ + }})[0].attr.attr) + +#define dwc_pcie_format_attr(_name, _fld) _dwc_pcie_format_attr(_name, 0, = _fld) + +static struct attribute *dwc_pcie_format_attrs[] =3D { + dwc_pcie_format_attr(type, DWC_PCIE_CONFIG_TYPE), + dwc_pcie_format_attr(eventid, DWC_PCIE_CONFIG_EVENTID), + dwc_pcie_format_attr(lane, DWC_PCIE_CONFIG_LANE), + NULL, +}; + +static struct attribute_group pcie_pmu_format_attrs_group =3D { + .name =3D "format", + .attrs =3D dwc_pcie_format_attrs, +}; + +struct dwc_pcie_event_attr { + struct device_attribute attr; + enum dwc_pcie_event_type type; + u16 eventid; + u8 lane; +}; + +ssize_t dwc_pcie_event_show(struct device *dev, + struct device_attribute *attr, char *page) +{ + struct dwc_pcie_event_attr *eattr; + + eattr =3D container_of(attr, typeof(*eattr), attr); + + if (eattr->type =3D=3D DWC_PCIE_LANE_EVENT) + return sprintf(page, "eventid=3D0x%lx, type=3D0x%lx, lane=3D0x%lx\n", + (unsigned long)eattr->eventid, + (unsigned long)eattr->type, + (unsigned long)eattr->lane); + else + return sprintf(page, "eventid=3D0x%lx, type=3D0x%lx", + (unsigned long)eattr->eventid, + (unsigned long)eattr->type); +} + +#define DWC_PCIE_EVENT_ATTR(_name, _type, _eventid, _lane) \ + (&((struct dwc_pcie_event_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_event_show, NULL), \ + .type =3D _type, \ + .eventid =3D _eventid, \ + .lane =3D _lane, \ + }})[0].attr.attr) + +#define DWC_PCIE_PMU_BASE_TIME_ATTR(_name, _eventid) \ + DWC_PCIE_EVENT_ATTR(_name, DWC_PCIE_TIME_BASE_EVENT, _eventid, 0) + +static struct attribute *dwc_pcie_pmu_time_event_attrs[] =3D { + /* Group #0 */ + DWC_PCIE_PMU_BASE_TIME_ATTR(one_cycle, 0x00), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_L0S, 0x01), + DWC_PCIE_PMU_BASE_TIME_ATTR(RX_L0S, 0x02), + DWC_PCIE_PMU_BASE_TIME_ATTR(L0, 0x03), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1, 0x04), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_1, 0x05), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_2, 0x06), + DWC_PCIE_PMU_BASE_TIME_ATTR(CFG_RCVRY, 0x07), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_RX_L0S, 0x08), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_AUX, 0x09), + DWC_PCIE_PMU_BASE_TIME_ATTR(ONE_cycle, 0x10), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_L0S_, 0x11), + DWC_PCIE_PMU_BASE_TIME_ATTR(RX_L0S_, 0x12), + DWC_PCIE_PMU_BASE_TIME_ATTR(L0_, 0x13), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_, 0x17), + DWC_PCIE_PMU_BASE_TIME_ATTR(CFG_RCVRY_, 0x17), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_RX_L0S_, 0x18), + /* Group #1 */ + DWC_PCIE_PMU_BASE_TIME_ATTR(Tx_PCIe_TLP_Data_Payload, 0x20), + DWC_PCIE_PMU_BASE_TIME_ATTR(Rx_PCIe_TLP_Data_Payload, 0x21), + DWC_PCIE_PMU_BASE_TIME_ATTR(Tx_CCIX_TLP_Data_Payload, 0x22), + DWC_PCIE_PMU_BASE_TIME_ATTR(Rx_CCIX_TLP_Data_Payload, 0x23), + NULL +}; + +static inline umode_t pcie_pmu_event_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unuse) +{ + return attr->mode; +} + +static inline bool pci_dev_is_rootport(struct pci_dev *pdev) +{ + return (pci_is_pcie(pdev) && + pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT); +} + +static int dwc_pcie_ras_des_discover(struct dwc_pcie_pmu_priv *priv) +{ + int index =3D 0; + struct pci_dev *pdev =3D NULL; + struct dwc_pcie_rp_info *rp_info; + + INIT_LIST_HEAD(&priv->rp_infos); + + /* Match the rootport with VSEC_RAS_DES_ID */ + for_each_pci_dev(pdev) { + u16 vsec; + u32 val; + + if (!pci_dev_is_rootport(pdev)) + continue; + + rp_info =3D devm_kzalloc(&pdev->dev, sizeof(*rp_info), GFP_KERNEL); + if (!rp_info) + return -ENOMEM; + + rp_info->bdf =3D PCI_DEVID(pdev->bus->number, pdev->devfn); + rp_info->pdev =3D pdev; + + vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_ALIBABA, + DWC_PCIE_VSEC_RAS_DES_ID); + if (!vsec) + continue; + + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); + if (PCI_VNDR_HEADER_REV(val) !=3D 0x04 || + PCI_VNDR_HEADER_LEN(val) !=3D 0x100) + continue; + pci_dbg(pdev, + "Detected PCIe Vendor-Specific Extended Capability RAS DES\n"); + + rp_info->ras_des =3D vsec; + + pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &val); + rp_info->num_lanes =3D pcie_get_width_cap(pdev); + + list_add(&rp_info->rp_node, &priv->rp_infos); + index++; + } + + if (!index) + return -ENODEV; + + priv->pcie_ctrl_num =3D index; + + return 0; +} + +static void dwc_pcie_pmu_set_event_id(struct pci_dev *pdev, u16 ras_des, + int event_id) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + val &=3D ~DWC_PCIE_CNT_ENABLE; + val |=3D FIELD_PREP(DWC_PCIE_CNT_EVENT_SEL, event_id); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_write_event_lane(struct pci_dev *pdev, u16 ras_de= s, + int lane, int event_id) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + val &=3D ~DWC_PCIE_CNT_LANE_SEL; + val |=3D FIELD_PREP(DWC_PCIE_CNT_EVENT_SEL, lane); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_event_enable(struct pci_dev *pdev, u16 ras_des, + u32 enable) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + val &=3D ~DWC_PCIE_CNT_ENABLE; + + if (enable) + val |=3D DWC_PCIE_PER_EVENT_ON; + else + val |=3D DWC_PCIE_PER_EVENT_OFF; + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_base_time_enable(struct pci_dev *pdev, u16 ras_de= s, + u32 enable) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, &val); + + if (enable) + val |=3D DWC_PCIE_TIME_BASED_CNT_ENABLE; + else + val &=3D ~DWC_PCIE_TIME_BASED_CNT_ENABLE; + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, val); +} + +static void dwc_pcie_pmu_read_event_counter(struct pci_dev *pdev, u16 ras_= des, + u64 *counter) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_DATA, &val); + *counter =3D val; +} + +/* The results are cleared when next measurement starts. */ +static void dwc_pcie_pmu_read_base_time_counter(struct pci_dev *pdev, + u16 ras_des, u64 *counter) +{ + u32 val; + + pci_read_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_DATA_REG_HIGH, + &val); + *counter =3D val; + *counter <<=3D 32; + + pci_read_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_DATA_REG_LOW, + &val); + + *counter +=3D val; +} + +static void dwc_pcie_pmu_clear_event_counter(struct pci_dev *pdev, u16 ras= _des) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + val |=3D FIELD_PREP(DWC_PCIE_EVENT_CLEAR, DWC_PCIE_EVENT_PER_CLEAR); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_base_time_add_prepare(struct pci_dev *pdev, + u16 ras_des, u32 event_id) +{ + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + &val); + + val &=3D ~DWC_PCIE_TIME_BASED_REPORT_SEL; + val |=3D FIELD_PREP(DWC_PCIE_TIME_BASED_REPORT_SEL, event_id); + val &=3D ~DWC_PCIE_TIME_BASED_DURATION_SEL; + + /* + * TIME_BASED_ANAL_DATA_REG is a 64 bit register, we can safely + * use it with any manually controlled duration. + */ + val &=3D ~(DWC_PCIE_TIME_BASED_DURATION_SEL); + val |=3D DWC_PCIE_DURATION_MANUAL_CTL; + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + val); +} + +static struct dwc_pcie_rp_info *pmu_to_pcie_info(struct pmu *pmu) +{ + struct dwc_pcie_rp_info *rp_info; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(pmu); + + rp_info =3D container_of(pcie_pmu, struct dwc_pcie_rp_info, pcie_pmu); + + return rp_info; +} + +static void dwc_pcie_pmu_event_update(struct perf_event *event) +{ + u64 counter; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + struct pci_dev *pdev =3D rp_info->pdev; + u16 ras_des =3D rp_info->ras_des; + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + u64 delta, prev, now; + + do { + prev =3D local64_read(&hwc->prev_count); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_read_event_counter(pdev, ras_des, &counter); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_read_base_time_counter(pdev, ras_des, + &counter); + else + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); + + now =3D counter; + } while (local64_cmpxchg(&hwc->prev_count, prev, now) !=3D prev); + + delta =3D now - prev; + + local64_add(delta, &event->count); +} + +static int dwc_pcie_pmu_event_init(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct perf_event *sibling; + + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + if (hwc->sample_period) { + dev_dbg(pcie_pmu->dev, "Sampling not supported\n"); + return -EOPNOTSUPP; + } + + if (event->cpu < 0) { + dev_dbg(pcie_pmu->dev, "Per-task mode not supported\n"); + return -EOPNOTSUPP; + } + + event->cpu =3D pcie_pmu->on_cpu; + + if (event->group_leader !=3D event && + !is_software_event(event->group_leader)) + return -EINVAL; + + for_each_sibling_event(sibling, event->group_leader) { + if (sibling !=3D event && !is_software_event(sibling)) + return -EINVAL; + } + + hwc->idx =3D -1; + + return 0; +} + +static void dwc_pcie_pmu_set_period(struct hw_perf_event *hwc) +{ + local64_set(&hwc->prev_count, 0); +} + +static void dwc_pcie_pmu_event_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + struct pci_dev *pdev =3D rp_info->pdev; + u16 ras_des =3D rp_info->ras_des; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + + hwc->state =3D 0; + dwc_pcie_pmu_set_period(hwc); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_event_enable(pdev, ras_des, 1); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_base_time_enable(pdev, ras_des, 1); + else + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); +} + +static void dwc_pcie_pmu_event_stop(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + struct pci_dev *pdev =3D rp_info->pdev; + u16 ras_des =3D rp_info->ras_des; + + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + + if (event->hw.state & PERF_HES_STOPPED) + return; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_event_enable(pdev, ras_des, 0); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_base_time_enable(pdev, ras_des, 0); + else + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); + + dwc_pcie_pmu_event_update(event); +} + +static int dwc_pcie_pmu_event_add(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + struct pci_dev *pdev =3D rp_info->pdev; + u16 ras_des =3D rp_info->ras_des; + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + int event_id =3D DWC_PCIE_EVENT_ID(event); + int lane =3D DWC_PCIE_EVENT_LANE(event); + + /* Only one counter and it is in use */ + if (rp_info->event) + return -ENOSPC; + + rp_info->event =3D event; + + hwc->state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) { + dwc_pcie_pmu_event_enable(pdev, ras_des, 0); + dwc_pcie_pmu_write_event_lane(pdev, ras_des, lane, event_id); + dwc_pcie_pmu_set_event_id(pdev, ras_des, event_id); + dwc_pcie_pmu_clear_event_counter(pdev, ras_des); + } else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) { + dwc_pcie_pmu_base_time_enable(pdev, ras_des, 0); + dwc_pcie_pmu_base_time_add_prepare(pdev, ras_des, event_id); + } else { + dev_err(pcie_pmu->dev, "invalid event type: 0x%x\n", type); + return -EINVAL; + } + + if (flags & PERF_EF_START) + dwc_pcie_pmu_event_start(event, PERF_EF_RELOAD); + + perf_event_update_userpage(event); + + return 0; +} + +static void dwc_pcie_pmu_event_del(struct perf_event *event, int flags) +{ + struct dwc_pcie_rp_info *rp_info =3D pmu_to_pcie_info(event->pmu); + + dwc_pcie_pmu_event_stop(event, flags | PERF_EF_UPDATE); + perf_event_update_userpage(event); + rp_info->event =3D NULL; +} + +static void dwc_pcie_pmu_event_read(struct perf_event *event) +{ + dwc_pcie_pmu_event_update(event); +} + +static struct dwc_event_counters event_array[] =3D { + {"tx_ack_dllp", 0x600}, + {"tx_update_fc_dllp", 0x601}, + {"rx_ack_dllp", 0x602}, + {"rx_update_fc_dllp", 0x603}, + {"rx_nulified_tlp", 0x604}, + {"tx_nulified_tlp", 0x605}, + {"rx_duplicate_tlp", 0x606}, + {"tx_memory_write", 0x700}, + {"tx_memory_read", 0x701}, + {"tx_configuration_write", 0x702}, + {"tx_configuration_read", 0x703}, + {"tx_io_write", 0x704}, + {"tx_io_read", 0x705}, + {"tx_completion_without_data", 0x706}, + {"tx_completion_with_data", 0x707}, + {"tx_message_tlp", 0x708}, + {"tx_atomic", 0x709}, + {"tx_tlp_with_prefix", 0x70A}, + {"rx_memory_write", 0x70B}, + {"rx_memory_read", 0x70C}, + {"rx_io_write", 0x70F}, + {"rx_io_read", 0x710}, + {"rx_completion_without_data", 0x711}, + {"rx_completion_with_data", 0x712}, + {"rx_message_tlp", 0x713}, + {"rx_atomic", 0x714}, + {"rx_tlp_with_prefix", 0x715}, + {"tx_ccix_tlp", 0x716}, + {"rx_ccix_tlp", 0x717}, +}; + +static int dwc_pcie_pmu_attr_init(struct dwc_pcie_pmu_priv *priv, + struct dwc_pcie_rp_info *rp_info) +{ + int i, j; + char lane[8]; + const char tmp[64]; + int events_per_lane; + int num_lane_events; + int time_base_count; + int num_attrs, attr_idx; + struct dwc_pcie_event_attr *lane_attrs; + struct attribute **pmu_attrs; + + memset((void *)tmp, 0, sizeof(tmp)); + memset((void *)lane, 0, sizeof(lane)); + time_base_count =3D ARRAY_SIZE(dwc_pcie_pmu_time_event_attrs); + events_per_lane =3D ARRAY_SIZE(event_array); + num_lane_events =3D rp_info->num_lanes * events_per_lane; + num_attrs =3D time_base_count + num_lane_events; + + rp_info->lane_event_attrs =3D + devm_kcalloc(priv->dev, num_lane_events, + sizeof(struct dwc_pcie_event_attr), + GFP_KERNEL); + if (!rp_info->lane_event_attrs) + return -ENOMEM; + lane_attrs =3D rp_info->lane_event_attrs; + rp_info->pcie_pmu_event_attrs =3D + devm_kcalloc(priv->dev, num_attrs, sizeof(struct attribute *), + GFP_KERNEL); + if (!rp_info->pcie_pmu_event_attrs) + return -ENOMEM; + pmu_attrs =3D rp_info->pcie_pmu_event_attrs; + + for (i =3D 0; i < num_lane_events; i++) { + lane_attrs[i].attr.attr.name =3D + devm_kzalloc(priv->dev, sizeof(char) + * ATTRI_NAME_MAX_SIZE, GFP_KERNEL); + if (!lane_attrs[i].attr.attr.name) + return -ENOMEM; + } + + attr_idx =3D 0; + for (i =3D 0; i < rp_info->num_lanes; i++) { + sprintf(lane, "_lane%d", i); + + for (j =3D 0; j < events_per_lane; j++) { + int pos =3D i * events_per_lane + j; + + strcat((char *)tmp, event_array[j].name); + strcat((char *)tmp, lane); + memcpy((void *)lane_attrs[pos].attr.attr.name, + (void *)tmp, + sizeof(tmp)); + + lane_attrs[pos].attr.attr.mode =3D + VERIFY_OCTAL_PERMISSIONS(0444); + lane_attrs[pos].attr.show =3D dwc_pcie_event_show; + lane_attrs[pos].attr.store =3D NULL; + lane_attrs[pos].type =3D DWC_PCIE_LANE_EVENT; + lane_attrs[pos].eventid =3D event_array[j].event_id; + lane_attrs[pos].lane =3D i; + pmu_attrs[attr_idx++] =3D &lane_attrs[pos].attr.attr; + + memset((void *)tmp, 0, sizeof(tmp)); + } + } + + for (i =3D 0; i < ARRAY_SIZE(dwc_pcie_pmu_time_event_attrs); i++) + pmu_attrs[attr_idx++] =3D dwc_pcie_pmu_time_event_attrs[i]; + + rp_info->pcie_pmu_event_attrs[attr_idx++] =3D NULL; + + rp_info->pcie_pmu_event_attrs_group.name =3D event_attr_name; + rp_info->pcie_pmu_event_attrs_group.is_visible =3D + pcie_pmu_event_attr_is_visible; + rp_info->pcie_pmu_event_attrs_group.attrs =3D + rp_info->pcie_pmu_event_attrs; + + rp_info->pcie_pmu_attr_groups[0] =3D + &rp_info->pcie_pmu_event_attrs_group; + rp_info->pcie_pmu_attr_groups[1] =3D &pcie_pmu_format_attrs_group; + rp_info->pcie_pmu_attr_groups[2] =3D &pcie_pmu_cpumask_attrs_group; + rp_info->pcie_pmu_attr_groups[3] =3D NULL; + + return 0; +} + +static int __dwc_pcie_pmu_probe(struct dwc_pcie_pmu_priv *priv, + struct dwc_pcie_rp_info *rp_info) +{ + struct dwc_pcie_pmu *pcie_pmu; + struct device *dev; + char *name; + int ret; + + pcie_pmu =3D &rp_info->pcie_pmu; + dev =3D &rp_info->pdev->dev; + + ret =3D dwc_pcie_pmu_attr_init(priv, rp_info); + if (ret) { + pci_err(rp_info->pdev, "PMU attr init fail ret=3D%d\n", ret); + return ret; + } + + pcie_pmu->dev =3D dev; + pcie_pmu->pmu =3D (struct pmu) { + .module =3D THIS_MODULE, + .task_ctx_nr =3D perf_invalid_context, + .pmu_enable =3D NULL, + .pmu_disable =3D NULL, + .event_init =3D dwc_pcie_pmu_event_init, + .add =3D dwc_pcie_pmu_event_add, + .del =3D dwc_pcie_pmu_event_del, + .start =3D dwc_pcie_pmu_event_start, + .stop =3D dwc_pcie_pmu_event_stop, + .read =3D dwc_pcie_pmu_event_read, + .attr_groups =3D rp_info->pcie_pmu_attr_groups, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + }; + + name =3D devm_kasprintf(priv->dev, GFP_KERNEL, "dwc_rootport_%x", + rp_info->bdf); + if (!name) + return -ENOMEM; + + /* + * Pick one CPU to be the preferred one on local NUMA node. + * + * Note, this PMU does NOT support interrupt, set on_cpu to indicate it + * is a uncore PMU device. + */ + pcie_pmu->on_cpu =3D cpumask_local_spread(0, dev_to_node(pcie_pmu->dev)); + ret =3D perf_pmu_register(&pcie_pmu->pmu, name, -1); + if (ret) { + pci_err(rp_info->pdev, "Error %d registering PMU @%x\n", ret, + rp_info->bdf); + return ret; + } + + rp_info->pmu_is_register =3D DWC_PCIE_PMU_HAS_REGISTER; + + return ret; +} + +static int dwc_pcie_pmu_remove(struct platform_device *pdev) +{ + struct dwc_pcie_pmu_priv *priv =3D platform_get_drvdata(pdev); + struct dwc_pcie_pmu *pcie_pmu; + struct dwc_pcie_rp_info *rp_info; + + list_for_each_entry(rp_info, &priv->rp_infos, rp_node) { + if (rp_info->pmu_is_register) { + pcie_pmu =3D &rp_info->pcie_pmu; + perf_pmu_unregister(&pcie_pmu->pmu); + } + } + return 0; +} + +static int dwc_pcie_pmu_probe(struct platform_device *pdev) +{ + int ret; + struct dwc_pcie_pmu_priv *priv; + struct dwc_pcie_rp_info *rp_info; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D &pdev->dev; + platform_set_drvdata(pdev, priv); + + /* If RAS_DES PMU is not supported on current platform, keep silent */ + ret =3D dwc_pcie_ras_des_discover(priv); + if (ret) + return ret; + + list_for_each_entry(rp_info, &priv->rp_infos, rp_node) { + struct pci_dev *rp =3D rp_info->pdev; + + ret =3D __dwc_pcie_pmu_probe(priv, rp_info); + if (ret) { + dev_err(&rp->dev, "PCIe PMU probe fail\n"); + goto pmu_unregister; + } + } + + return 0; + +pmu_unregister: + dwc_pcie_pmu_remove(pdev); + + return ret; +} + +static struct platform_driver dwc_pcie_pmu_driver =3D { + .probe =3D dwc_pcie_pmu_probe, + .remove =3D dwc_pcie_pmu_remove, + .driver =3D {.name =3D "dwc_pcie_pmu",}, +}; + +static int __init dwc_pcie_pmu_init(void) +{ + int ret; + + ret =3D platform_driver_register(&dwc_pcie_pmu_driver); + + if (ret) + return ret; + + dwc_pcie_pmu_dev =3D + platform_device_register_simple("dwc_pcie_pmu", -1, NULL, 0); + if (IS_ERR(dwc_pcie_pmu_dev)) { + platform_driver_unregister(&dwc_pcie_pmu_driver); + return PTR_ERR(dwc_pcie_pmu_dev); + } + + return 0; +} + +static void __exit dwc_pcie_pmu_exit(void) +{ + platform_device_unregister(dwc_pcie_pmu_dev); + platform_driver_unregister(&dwc_pcie_pmu_driver); +} + +module_init(dwc_pcie_pmu_init); +module_exit(dwc_pcie_pmu_exit); + +MODULE_DESCRIPTION("PMU driver for DesignWare Cores PCI Express Controller= "); +MODULE_AUTHOR("xueshuai@linux.alibaba.com"); +MODULE_AUTHOR("yinxuan_cw@linux.alibaba.com"); +MODULE_LICENSE("GPL v2"); --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B060C54EE9 for ; Sat, 17 Sep 2022 12:10:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229527AbiIQMKx (ORCPT ); Sat, 17 Sep 2022 08:10:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229454AbiIQMKr (ORCPT ); Sat, 17 Sep 2022 08:10:47 -0400 Received: from out30-54.freemail.mail.aliyun.com (out30-54.freemail.mail.aliyun.com [115.124.30.54]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21D102B242 for ; Sat, 17 Sep 2022 05:10:44 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R971e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046049;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=10;SR=0;TI=SMTPD_---0VQ-l721_1663416641; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VQ-l721_1663416641) by smtp.aliyun-inc.com; Sat, 17 Sep 2022 20:10:42 +0800 From: Shuai Xue To: will@kernel.org, Jonathan.Cameron@Huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v1 2/3] drivers/perf: add DesignWare PCIe PMU driver Date: Sat, 17 Sep 2022 20:10:35 +0800 Message-Id: <20220917121036.14864-3-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This commit adds the PCIe Performance Monitoring Unit (PMU) driver support for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express Core controller IP which provides statistics feature. The PMU is not a PCIe Root Complex integrated End Point(RCiEP) device but only register counters provided by each PCIe Root Port. To facilitate collection of statistics the controller provides the following two features for each Root Port: - Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) - Event counters (Error and Non-Error for lanes) Note, only one counter for each type. This driver add PMU devices for each PCIe Root Port. And the PMU device is named based the BDF of Root Port. For example, 10:00.0 PCI bridge: Device 1ded:8000 (rev 01) the PMU device name for this Root Port is pcie_bdf_100000. Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: $# perf stat -a -e pcie_bdf_200/Rx_PCIe_TLP_Data_Payload/ average RX bandwidth can be calculated like this: PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window Signed-off-by: Shuai Xue --- drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/dwc_pcie_pmu.c | 976 ++++++++++++++++++++++++++++++++++++ 3 files changed, 984 insertions(+) create mode 100644 drivers/perf/dwc_pcie_pmu.c diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 1e2d69453771..11ae99de5bbf 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -192,4 +192,11 @@ config MARVELL_CN10K_DDR_PMU Enable perf support for Marvell DDR Performance monitoring event on CN10K platform. =20 +config CONFIG_DWC_PCIE_PMU + tristate "Enable Synopsys DesignWare PCIe PMU Support" + depends on ARM64 || (COMPILE_TEST && 64BIT) + help + Enable perf support for Synopsys DesignWare PCIe PMU Performance + monitoring event on Yitan 710 platform. + endmenu diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index 57a279c61df5..36f75cb0f320 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_ARM_DMC620_PMU) +=3D arm_dmc620_pmu.o obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) +=3D marvell_cn10k_tad_pmu.o obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) +=3D marvell_cn10k_ddr_pmu.o obj-$(CONFIG_APPLE_M1_CPU_PMU) +=3D apple_m1_cpu_pmu.o +obj-$(CONFIG_DWC_PCIE_PMU) +=3D dwc_pcie_pmu.o diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c new file mode 100644 index 000000000000..81e534be13fa --- /dev/null +++ b/drivers/perf/dwc_pcie_pmu.c @@ -0,0 +1,976 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare PCIe PMU driver + * + * Copyright (C) 2021, 2022 Alibaba Inc. + */ +=C2=A0 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "dwc_pcie_pmu" +#define DEV_NAME "dwc_pcie_pmu" +#define RP_NUM_MAX 32 /* 2die * 4RC * 4Ctrol */ +#define ATTRI_NAME_MAX_SIZE 32 + +#define DWC_PCIE_VSEC_ID 0x02 +#define DWC_PCIE_VSEC_REV 0x04 + +#define DWC_PCIE_LINK_CAPABILITIES_REG 0xC +#define DWC_PCIE_LANE_SHIFT 4 +#define DWC_PCIE_LANE_MASK GENMASK(9, 4) + +#define DWC_PCIE_EVENT_CNT_CTRL 0x8 +#define DWC_PCIE__CNT_EVENT_SELECT_SHIFT 16 +#define DWC_PCIE__CNT_EVENT_SELECT_MASK GENMASK(27, 16) +#define DWC_PCIE__CNT_LANE_SELECT_SHIFT 8 +#define DWC_PCIE__CNT_LANE_SELECT_MASK GENMASK(11, 8) +#define DWC_PCIE__CNT_STATUS_SHIFT 7 +#define DWC_PCIE__CNT_STATUS_MASK BIT(7) +#define DWC_PCIE__CNT_ENABLE_SHIFT 2 +#define DWC_PCIE__CNT_ENABLE_MASK GENMASK(4, 2) +#define DWC_PCIE_PER_EVENT_OFF (0x1 << DWC_PCIE__CNT_ENABLE_SHIFT) +#define DWC_PCIE_PER_EVENT_ON (0x3 << DWC_PCIE__CNT_ENABLE_SHIFT) +#define DWC_PCIE_EVENT_CLEAR_MASK GENMASK(1, 0) + +#define DWC_PCIE_EVENT_CNT_DATA 0xC + +#define DWC_PCIE_TIME_BASED_ANALYSIS_CTRL 0x10 +#define DWC_PCIE__TIME_BASED_REPORT_SELECT_SHIFT 24 +#define DWC_PCIE__TIME_BASED_REPORT_SELECT_MASK GENMASK(31, 24) +#define DWC_PCIE__TIME_BASED_DURATION_SHIFT 8 +#define DWC_PCIE__TIME_BASED_DURATION_SELECT GENMASK(15, 8) +#define DWC_PCIE_DURATION_MANUAL_CTRL 0x0 +#define DWC_PCIE_DURATION_1MS 0x1 +#define DWC_PCIE_DURATION_10MS 0x2 +#define DWC_PCIE_DURATION_100MS 0x3 +#define DWC_PCIE_DURATION_1S 0x4 +#define DWC_PCIE_DURATION_2S 0x5 +#define DWC_PCIE_DURATION_4S 0x6 +#define DWC_PCIE_DURATION_4US 0xff +#define DWC_PCIE__TIME_BASED_COUNTER_ENABLE 1 + +#define DWC_PCIE_TIME_BASED_ANALYSIS_DATA_REG_LOW 0x14 +#define DWC_PCIE_TIME_BASED_ANALYSIS_DATA_REG_HIGH 0x18 + +/* Event attributes */ +#define DWC_PCIE_CONFIG_EVENTID GENMASK(15, 0) +#define DWC_PCIE_CONFIG_TYPE GENMASK(19, 16) +#define DWC_PCIE_CONFIG_LANE GENMASK(27, 20) + +#define DWC_PCIE_EVENT_ID(event) FIELD_GET(DWC_PCIE_CONFIG_EVENTID, (event= )->attr.config) +#define DWC_PCIE_EVENT_TYPE(event) FIELD_GET(DWC_PCIE_CONFIG_TYPE, (event)= ->attr.config) +#define DWC_PCIE_EVENT_LANE(event) FIELD_GET(DWC_PCIE_CONFIG_LANE, (event)= ->attr.config) + +#define DWC_PCIE_PMU_HAS_REGISTER 1 + +enum dwc_pcie_event_type { + DWC_PCIE_TYPE_INVALID, + DWC_PCIE_TIME_BASE_EVENT, + DWC_PCIE_LANE_EVENT, +}; + +struct dwc_event_counters { + const char name[32]; + u32 event_id; +}; + +struct dwc_pcie_pmu { + struct hlist_node node; + unsigned int on_cpu; + struct pmu pmu; + struct device *dev; +}; + +struct dwc_pcie_info_table { + u32 bdf; + u32 cap_pos; + u32 num_lanes; + struct pci_dev *pdev; + struct dwc_pcie_pmu pcie_pmu; + u8 pmu_is_register; + struct perf_event *event; + + struct dwc_pcie_event_attr *lane_event_attrs; + struct attribute **pcie_pmu_event_attrs; + struct attribute_group pcie_pmu_event_attrs_group; + const struct attribute_group *pcie_pmu_attr_groups[4]; +}; + +struct dwc_pcie_pmu_priv { + struct device *dev; + u32 pcie_ctrl_num; + struct dwc_pcie_info_table *pcie_table; +}; + +#define DWC_PCIE_CREATE_BDF(seg, bus, dev, func) \ + (((seg) << 24) | (((bus) & 0xFF) << 16) | (((dev) & 0xFF) << 8) | (func)) +#define to_pcie_pmu(p) (container_of(p, struct dwc_pcie_pmu, pmu)) + +static struct platform_device *dwc_pcie_pmu_dev; +static char *event_attr_name =3D "events"; + +static ssize_t dwc_pcie_pmu_cpumask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_pcie_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(pcie_pmu->on_cpu)); +} + +static struct device_attribute dwc_pcie_pmu_cpumask_attr =3D +__ATTR(cpumask, 0444, dwc_pcie_pmu_cpumask_show, NULL); + +static struct attribute *dwc_pcie_pmu_cpumask_attrs[] =3D { + &dwc_pcie_pmu_cpumask_attr.attr, + NULL +}; + +static struct attribute_group pcie_pmu_cpumask_attrs_group =3D { + .attrs =3D dwc_pcie_pmu_cpumask_attrs, +}; + +struct dwc_pcie_format_attr { + struct device_attribute attr; + u64 field; + int config; +}; + +static ssize_t dwc_pcie_pmu_format_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_format_attr *fmt =3D container_of(attr, typeof(*fmt), att= r); + int lo =3D __ffs(fmt->field), hi =3D __fls(fmt->field); + + if (lo =3D=3D hi) + return snprintf(buf, PAGE_SIZE, "config:%d\n", lo); + + if (!fmt->config) + return snprintf(buf, PAGE_SIZE, "config:%d-%d\n", lo, hi); + + return snprintf(buf, PAGE_SIZE, "config%d:%d-%d\n", fmt->config, lo, + hi); +} + +#define _dwc_pcie_format_attr(_name, _cfg, _fld) \ + (&((struct dwc_pcie_format_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_pmu_format_show, NULL), \ + .config =3D _cfg, \ + .field =3D _fld, \ + }})[0].attr.attr) + +#define dwc_pcie_format_attr(_name, _fld) _dwc_pcie_format_attr(_name, 0, = _fld) + +static struct attribute *dwc_pcie_format_attrs[] =3D { + dwc_pcie_format_attr(type, DWC_PCIE_CONFIG_TYPE), + dwc_pcie_format_attr(eventid, DWC_PCIE_CONFIG_EVENTID), + dwc_pcie_format_attr(lane, DWC_PCIE_CONFIG_LANE), + NULL, +}; + +static struct attribute_group pcie_pmu_format_attrs_group =3D { + .name =3D "format", + .attrs =3D dwc_pcie_format_attrs, +}; + +struct dwc_pcie_event_attr { + struct device_attribute attr; + enum dwc_pcie_event_type type; + u16 eventid; + u8 lane; +}; + +ssize_t dwc_pcie_event_show(struct device *dev, + struct device_attribute *attr, char *page) +{ + struct dwc_pcie_event_attr *eattr; + + eattr =3D container_of(attr, typeof(*eattr), attr); + + if (eattr->type =3D=3D DWC_PCIE_LANE_EVENT) + return sprintf(page, "eventid=3D0x%lx, type=3D0x%lx, lane=3D0x%lx\n", + (unsigned long)eattr->eventid, + (unsigned long)eattr->type, + (unsigned long)eattr->lane); + else + return sprintf(page, "eventid=3D0x%lx, type=3D0x%lx", + (unsigned long)eattr->eventid, + (unsigned long)eattr->type); +} + +#define DWC_PCIE_EVENT_ATTR(_name, _type, _eventid, _lane) \ + (&((struct dwc_pcie_event_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_event_show, NULL), \ + .type =3D _type, \ + .eventid =3D _eventid, \ + .lane =3D _lane, \ + }})[0].attr.attr) + +#define DWC_PCIE_PMU_BASE_TIME_ATTR(_name, _eventid) \ + DWC_PCIE_EVENT_ATTR(_name, DWC_PCIE_TIME_BASE_EVENT, _eventid, 0) + +static struct attribute *dwc_pcie_pmu_time_event_attrs[] =3D { + /* Group #0 */ + DWC_PCIE_PMU_BASE_TIME_ATTR(one_cycle, 0x00), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_L0S, 0x01), + DWC_PCIE_PMU_BASE_TIME_ATTR(RX_L0S, 0x02), + DWC_PCIE_PMU_BASE_TIME_ATTR(L0, 0x03), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1, 0x04), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_1, 0x05), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_2, 0x06), + DWC_PCIE_PMU_BASE_TIME_ATTR(CFG_RCVRY, 0x07), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_RX_L0S, 0x08), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_AUX, 0x09), + DWC_PCIE_PMU_BASE_TIME_ATTR(ONE_cycle, 0x10), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_L0S_, 0x11), + DWC_PCIE_PMU_BASE_TIME_ATTR(RX_L0S_, 0x12), + DWC_PCIE_PMU_BASE_TIME_ATTR(L0_, 0x13), + DWC_PCIE_PMU_BASE_TIME_ATTR(L1_, 0x17), + DWC_PCIE_PMU_BASE_TIME_ATTR(CFG_RCVRY_, 0x17), + DWC_PCIE_PMU_BASE_TIME_ATTR(TX_RX_L0S_, 0x18), + /* Group #1 */ + DWC_PCIE_PMU_BASE_TIME_ATTR(Tx_PCIe_TLP_Data_Payload, 0x20), + DWC_PCIE_PMU_BASE_TIME_ATTR(Rx_PCIe_TLP_Data_Payload, 0x21), + DWC_PCIE_PMU_BASE_TIME_ATTR(Tx_CCIX_TLP_Data_Payload, 0x22), + DWC_PCIE_PMU_BASE_TIME_ATTR(Rx_CCIX_TLP_Data_Payload, 0x23), + NULL +}; + +static inline umode_t pcie_pmu_event_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unuse) +{ + return attr->mode; +} + +static inline bool pci_dev_is_rootport(struct pci_dev *pdev) +{ + return (pci_is_pcie(pdev) && + pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT); +} + +static inline unsigned int dwc_pcie_get_bdf(struct pci_dev *dev) +{ + return (DWC_PCIE_CREATE_BDF(pci_domain_nr(dev->bus), dev->bus->number, + PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn))); +} + +static int dwc_pcie_find_ras_des_cap_position(struct pci_dev *pdev, int *p= os) +{ + u32 header; + int vsec =3D 0; + + while ((vsec =3D pci_find_next_ext_capability(pdev, vsec, + PCI_EXT_CAP_ID_VNDR))) { + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &header); + /* Is the device part of a DesignWare Cores PCIe Controller ? */ + if (PCI_VNDR_HEADER_ID(header) =3D=3D DWC_PCIE_VSEC_ID && + PCI_VNDR_HEADER_REV(header) =3D=3D DWC_PCIE_VSEC_REV) { + *pos =3D vsec; + return 0; + } + } + + return -ENODEV; +} + +static int dwc_pcie_pmu_discover(struct dwc_pcie_pmu_priv *priv) +{ + int val, where, index =3D 0; + struct pci_dev *pdev =3D NULL; + struct dwc_pcie_info_table *pcie_info; + + priv->pcie_table =3D + devm_kcalloc(priv->dev, RP_NUM_MAX, sizeof(*pcie_info), GFP_KERNEL); + if (!priv->pcie_table) + return -EINVAL; + + pcie_info =3D priv->pcie_table; + while ((pdev =3D pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) !=3D NULL = && + index < RP_NUM_MAX) { + if (!pci_dev_is_rootport(pdev)) + continue; + + pcie_info[index].bdf =3D dwc_pcie_get_bdf(pdev); + pcie_info[index].pdev =3D pdev; + + if (dwc_pcie_find_ras_des_cap_position(pdev, &where)) + continue; + + pcie_info[index].cap_pos =3D where; + + pci_read_config_dword(pdev, + pdev->pcie_cap + DWC_PCIE_LINK_CAPABILITIES_REG, + &val); + pcie_info[index].num_lanes =3D + (val & DWC_PCIE_LANE_MASK) >> DWC_PCIE_LANE_SHIFT; + index++; + } + + if (!index) + return -ENODEV; + + priv->pcie_ctrl_num =3D index; + + return 0; +} + +static inline int dwc_pcie_pmu_read_dword(struct dwc_pcie_info_table *pcie= _info, + u32 reg, u32 *val) +{ + return pci_read_config_dword(pcie_info->pdev, pcie_info->cap_pos + reg, + val); +} + +static inline int dwc_pcie_pmu_write_dword(struct dwc_pcie_info_table + *pcie_info, u32 reg, u32 val) +{ + return pci_write_config_dword(pcie_info->pdev, pcie_info->cap_pos + reg, + val); +} + +static int dwc_pcie_pmu_set_event_id(struct dwc_pcie_info_table *pcie_info, + int event_id) +{ + int ret; + u32 val; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, DWC_PCIE_EVENT_CNT_CTRL, &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + + val &=3D ~DWC_PCIE__CNT_ENABLE_MASK; + val &=3D ~DWC_PCIE__CNT_EVENT_SELECT_MASK; + val |=3D event_id << DWC_PCIE__CNT_EVENT_SELECT_SHIFT; + + ret =3D dwc_pcie_pmu_write_dword(pcie_info, DWC_PCIE_EVENT_CNT_CTRL, val); + if (ret) + pci_err(pcie_info->pdev, "PCIe write fail\n"); + + return ret; +} + +static int dwc_pcie_pmu_write_event_lane(struct dwc_pcie_info_table *pcie_= info, + int lane, int event_id) +{ + u32 ret; + u32 val; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, DWC_PCIE_EVENT_CNT_CTRL, &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + + val &=3D ~DWC_PCIE__CNT_LANE_SELECT_MASK; + val |=3D lane << DWC_PCIE__CNT_LANE_SELECT_SHIFT; + + ret =3D dwc_pcie_pmu_write_dword(pcie_info, DWC_PCIE_EVENT_CNT_CTRL, val); + if (ret) + pci_err(pcie_info->pdev, "PCIe write fail\n"); + + return ret; +} + +static int dwc_pcie_pmu_event_enable(struct dwc_pcie_info_table *pcie_info, + u32 enable) +{ + u32 ret; + u32 val; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, DWC_PCIE_EVENT_CNT_CTRL, &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + + val &=3D ~(DWC_PCIE__CNT_ENABLE_MASK); + + if (enable) + val |=3D DWC_PCIE_PER_EVENT_ON; + else + val |=3D DWC_PCIE_PER_EVENT_OFF; + + ret =3D dwc_pcie_pmu_write_dword(pcie_info, DWC_PCIE_EVENT_CNT_CTRL, val); + if (ret) + pci_err(pcie_info->pdev, "PCIe write fail\n"); + + return ret; +} + +static int dwc_pcie_pmu_base_time_enable(struct dwc_pcie_info_table *pcie_= info, + u32 enable) +{ + u32 ret; + u32 val; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, + DWC_PCIE_TIME_BASED_ANALYSIS_CTRL, &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + + if (enable) + val |=3D DWC_PCIE__TIME_BASED_COUNTER_ENABLE; + else + val &=3D ~DWC_PCIE__TIME_BASED_COUNTER_ENABLE; + + ret =3D dwc_pcie_pmu_write_dword(pcie_info, + DWC_PCIE_TIME_BASED_ANALYSIS_CTRL, val); + if (ret) + pci_err(pcie_info->pdev, "PCIe write fail\n"); + + return ret; +} + +static int dwc_pcie_pmu_read_event_counter(struct dwc_pcie_info_table + *pcie_info, u64 *counter) +{ + u32 ret, val; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, DWC_PCIE_EVENT_CNT_DATA, &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + *counter =3D val; + + return ret; +} + +static int dwc_pcie_pmu_read_base_time_counter(struct dwc_pcie_info_table + *pcie_info, u64 *counter) +{ + u32 ret, val; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, + DWC_PCIE_TIME_BASED_ANALYSIS_DATA_REG_HIGH, + &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + + *counter =3D val; + *counter <<=3D 32; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, + DWC_PCIE_TIME_BASED_ANALYSIS_DATA_REG_LOW, + &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + + *counter +=3D val; + + return ret; +} + +static int dwc_pcie_pmu_clear_event_counter(struct dwc_pcie_info_table + *pcie_info) +{ + u32 ret; + u32 val; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, DWC_PCIE_EVENT_CNT_CTRL, &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + + val &=3D ~DWC_PCIE_EVENT_CLEAR_MASK; + val |=3D 1; + + ret =3D dwc_pcie_pmu_write_dword(pcie_info, DWC_PCIE_EVENT_CNT_CTRL, val); + if (ret) + pci_err(pcie_info->pdev, "PCIe write fail\n"); + + return ret; +} + +static int dwc_pcie_pmu_base_time_add_prepare(struct dwc_pcie_info_table + *pcie_info, u32 event_id) +{ + u32 ret; + u32 val; + + ret =3D dwc_pcie_pmu_read_dword(pcie_info, + DWC_PCIE_TIME_BASED_ANALYSIS_CTRL, &val); + if (ret) { + pci_err(pcie_info->pdev, "PCIe read fail\n"); + return ret; + } + + val &=3D ~DWC_PCIE__TIME_BASED_REPORT_SELECT_MASK; + val |=3D event_id << DWC_PCIE__TIME_BASED_REPORT_SELECT_SHIFT; + val &=3D ~DWC_PCIE__TIME_BASED_DURATION_SELECT; + + /* + * TIME_BASED_ANALYSIS_DATA_REG is a 64 bit register, we can safely + * use it with any manually controllered duration. + */ + val &=3D ~(DWC_PCIE__TIME_BASED_DURATION_SELECT); + val |=3D DWC_PCIE_DURATION_MANUAL_CTRL; + + ret =3D dwc_pcie_pmu_write_dword(pcie_info, + DWC_PCIE_TIME_BASED_ANALYSIS_CTRL, val); + if (ret) + pci_err(pcie_info->pdev, "PCIe write fail\n"); + + return ret; +} + +static struct dwc_pcie_info_table *pmu_to_pcie_info(struct pmu *pmu) +{ + struct dwc_pcie_info_table *pcie_info; + struct dwc_pcie_pmu *pcie_pmu =3D to_pcie_pmu(pmu); + + pcie_info =3D container_of(pcie_pmu, struct dwc_pcie_info_table, pcie_pmu= ); + if (pcie_info =3D=3D NULL) + pci_err(pcie_info->pdev, "Can't get pcie info\n"); + + return pcie_info; +} + +static void dwc_pcie_pmu_event_update(struct perf_event *event) +{ + u64 counter; + struct dwc_pcie_info_table *pcie_info =3D pmu_to_pcie_info(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + u64 delta, prev, now; + + do { + prev =3D local64_read(&hwc->prev_count); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_read_event_counter(pcie_info, &counter); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_read_base_time_counter(pcie_info, + &counter); + else + pci_err(pcie_info->pdev, "Input param is invalid\n"); + + now =3D counter; + } while (local64_cmpxchg(&hwc->prev_count, prev, now) !=3D prev); + + delta =3D now - prev; + + local64_add(delta, &event->count); +} + +static int dwc_pcie_pmu_event_init(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct dwc_pcie_pmu *pcie_pmu =3D to_pcie_pmu(event->pmu); + struct perf_event *sibling; + + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + if (hwc->sample_period) { + dev_dbg(pcie_pmu->dev, "Sampling not supported\n"); + return -EOPNOTSUPP; + } + + if (event->cpu < 0) { + dev_dbg(pcie_pmu->dev, "Per-task mode not supported\n"); + return -EOPNOTSUPP; + } + + event->cpu =3D pcie_pmu->on_cpu; + + if (event->group_leader !=3D event && + !is_software_event(event->group_leader)) { + dev_dbg(pcie_pmu->dev, "Drive way only allow one event!\n"); + return -EINVAL; + } + + for_each_sibling_event(sibling, event->group_leader) { + if (sibling !=3D event && !is_software_event(sibling)) { + dev_dbg(pcie_pmu->dev, "Drive way event not allowed!\n"); + return -EINVAL; + } + } + + hwc->idx =3D -1; + + return 0; +} + +static void dwc_pcie_pmu_set_period(struct hw_perf_event *hwc) +{ + u64 new =3D 0; + + local64_set(&hwc->prev_count, new); +} + +static void dwc_pcie_pmu_event_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct dwc_pcie_info_table *pcie_info =3D pmu_to_pcie_info(event->pmu); + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + + hwc->state =3D 0; + dwc_pcie_pmu_set_period(hwc); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_event_enable(pcie_info, 1); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_base_time_enable(pcie_info, 1); + else + pci_err(pcie_info->pdev, "Input param is invalid\n"); +} + +static void dwc_pcie_pmu_event_stop(struct perf_event *event, int flags) +{ + struct dwc_pcie_info_table *pcie_info =3D pmu_to_pcie_info(event->pmu); + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + + if (event->hw.state & PERF_HES_STOPPED) + return; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_event_enable(pcie_info, 0); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_base_time_enable(pcie_info, 0); + else + pci_err(pcie_info->pdev, "Input param is invalid\n"); + + dwc_pcie_pmu_event_update(event); +} + +static int dwc_pcie_pmu_event_add(struct perf_event *event, int flags) +{ + struct dwc_pcie_info_table *pcie_info =3D pmu_to_pcie_info(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + int event_id =3D DWC_PCIE_EVENT_ID(event); + int lane =3D DWC_PCIE_EVENT_LANE(event); + + if (pcie_info->event) + return -ENOSPC; + + pcie_info->event =3D event; + + hwc->state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) { + dwc_pcie_pmu_event_enable(pcie_info, 0); + dwc_pcie_pmu_write_event_lane(pcie_info, lane, event_id); + dwc_pcie_pmu_set_event_id(pcie_info, event_id); + dwc_pcie_pmu_clear_event_counter(pcie_info); + } else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) { + dwc_pcie_pmu_base_time_enable(pcie_info, 0); + dwc_pcie_pmu_base_time_add_prepare(pcie_info, event_id); + } else { + pci_err(pcie_info->pdev, "Input param is invalid\n"); + return -EINVAL; + } + + if (flags & PERF_EF_START) + dwc_pcie_pmu_event_start(event, PERF_EF_RELOAD); + + perf_event_update_userpage(event); + + return 0; +} + +static void dwc_pcie_pmu_event_del(struct perf_event *event, int flags) +{ + struct dwc_pcie_info_table *pcie_info =3D pmu_to_pcie_info(event->pmu); + + dwc_pcie_pmu_event_stop(event, flags | PERF_EF_UPDATE); + perf_event_update_userpage(event); + pcie_info->event =3D NULL; +} + +static void dwc_pcie_pmu_event_read(struct perf_event *event) +{ + dwc_pcie_pmu_event_update(event); +} + +static struct dwc_event_counters event_array[] =3D { + {"tx_ack_dllp", 0x600}, + {"tx_update_fc_dllp", 0x601}, + {"rx_ack_dllp", 0x602}, + {"rx_update_fc_dllp", 0x603}, + {"rx_nulified_tlp", 0x604}, + {"tx_nulified_tlp", 0x605}, + {"rx_duplicate_tlp", 0x606}, + {"tx_memory_write", 0x700}, + {"tx_memory_read", 0x701}, + {"tx_configuration_write", 0x702}, + {"tx_configuration_read", 0x703}, + {"tx_io_write", 0x704}, + {"tx_io_read", 0x705}, + {"tx_completion_without_data", 0x706}, + {"tx_completion_with_data", 0x707}, + {"tx_message_tlp", 0x708}, + {"tx_atomic", 0x709}, + {"tx_tlp_with_prefix", 0x70A}, + {"rx_memory_write", 0x70B}, + {"rx_memory_read", 0x70C}, + {"rx_io_write", 0x70F}, + {"rx_io_read", 0x710}, + {"rx_completion_without_data", 0x711}, + {"rx_completion_with_data", 0x712}, + {"rx_message_tlp", 0x713}, + {"rx_atomic", 0x714}, + {"rx_tlp_with_prefix", 0x715}, + {"tx_ccix_tlp", 0x716}, + {"rx_ccix_tlp", 0x717}, +}; + +static int dwc_pcie_pmu_attr_init(struct dwc_pcie_pmu_priv *priv, + struct dwc_pcie_info_table *pcie_info) +{ + int i, j; + char lane[8]; + const char tmp[64]; + int events_per_lane; + int num_lane_events; + int time_base_count; + int num_attrs, attr_idx; + struct dwc_pcie_event_attr *lane_attrs; + struct attribute **pmu_attrs; + + memset((void *)tmp, 0, sizeof(tmp)); + memset((void *)lane, 0, sizeof(lane)); + time_base_count =3D ARRAY_SIZE(dwc_pcie_pmu_time_event_attrs); + events_per_lane =3D ARRAY_SIZE(event_array); + num_lane_events =3D pcie_info->num_lanes * events_per_lane; + num_attrs =3D time_base_count + num_lane_events; + + pcie_info->lane_event_attrs =3D + devm_kcalloc(priv->dev, num_lane_events, + sizeof(struct dwc_pcie_event_attr), + GFP_KERNEL); + if (!pcie_info->lane_event_attrs) + return -ENOMEM; + lane_attrs =3D pcie_info->lane_event_attrs; + pcie_info->pcie_pmu_event_attrs =3D + devm_kcalloc(priv->dev, num_attrs, sizeof(struct attribute *), + GFP_KERNEL); + if (!pcie_info->pcie_pmu_event_attrs) + return -ENOMEM; + pmu_attrs =3D pcie_info->pcie_pmu_event_attrs; + + for (i =3D 0; i < num_lane_events; i++) { + lane_attrs[i].attr.attr.name =3D + devm_kzalloc(priv->dev, sizeof(char) + * ATTRI_NAME_MAX_SIZE, GFP_KERNEL); + if (!lane_attrs[i].attr.attr.name) + return -ENOMEM; + } + + attr_idx =3D 0; + for (i =3D 0; i < pcie_info->num_lanes; i++) { + sprintf(lane, "_lane%d", i); + + for (j =3D 0; j < events_per_lane; j++) { + int pos =3D i * events_per_lane + j; + + strcat((char *)tmp, event_array[j].name); + strcat((char *)tmp, lane); + memcpy((void *)lane_attrs[pos].attr.attr.name, + (void *)tmp, + sizeof(tmp)); + + lane_attrs[pos].attr.attr.mode =3D + VERIFY_OCTAL_PERMISSIONS(0444); + lane_attrs[pos].attr.show =3D dwc_pcie_event_show; + lane_attrs[pos].attr.store =3D NULL; + lane_attrs[pos].type =3D DWC_PCIE_LANE_EVENT; + lane_attrs[pos].eventid =3D event_array[j].event_id; + lane_attrs[pos].lane =3D i; + pmu_attrs[attr_idx++] =3D &lane_attrs[pos].attr.attr; + + memset((void *)tmp, 0, sizeof(tmp)); + } + } + + for (i =3D 0; i < ARRAY_SIZE(dwc_pcie_pmu_time_event_attrs); i++) + pmu_attrs[attr_idx++] =3D dwc_pcie_pmu_time_event_attrs[i]; + + pcie_info->pcie_pmu_event_attrs[attr_idx++] =3D NULL; + + pcie_info->pcie_pmu_event_attrs_group.name =3D event_attr_name; + pcie_info->pcie_pmu_event_attrs_group.is_visible =3D + pcie_pmu_event_attr_is_visible; + pcie_info->pcie_pmu_event_attrs_group.attrs =3D + pcie_info->pcie_pmu_event_attrs; + + pcie_info->pcie_pmu_attr_groups[0] =3D + &pcie_info->pcie_pmu_event_attrs_group; + pcie_info->pcie_pmu_attr_groups[1] =3D &pcie_pmu_format_attrs_group; + pcie_info->pcie_pmu_attr_groups[2] =3D &pcie_pmu_cpumask_attrs_group; + pcie_info->pcie_pmu_attr_groups[3] =3D NULL; + + return 0; +} + +static int __dwc_pcie_pmu_probe(struct dwc_pcie_pmu_priv *priv, + struct dwc_pcie_info_table *pcie_info) +{ + int ret; + char *name; + struct dwc_pcie_pmu *pcie_pmu; + struct device *dev; + + if (!pcie_info || !pcie_info->pdev) { + pci_err(pcie_info->pdev, "Input parameter is invalid\n"); + return -EINVAL; + } + + pcie_pmu =3D &pcie_info->pcie_pmu; + dev =3D &pcie_info->pdev->dev; + + ret =3D dwc_pcie_pmu_attr_init(priv, pcie_info); + if (ret) { + pci_err(pcie_info->pdev, "PMU attr init fail ret=3D%d\n", ret); + return ret; + } + + pcie_pmu->dev =3D dev; + pcie_pmu->pmu =3D (struct pmu) { + .module =3D THIS_MODULE, + .task_ctx_nr =3D perf_invalid_context, + .pmu_enable =3D NULL, + .pmu_disable =3D NULL, + .event_init =3D dwc_pcie_pmu_event_init, + .add =3D dwc_pcie_pmu_event_add, + .del =3D dwc_pcie_pmu_event_del, + .start =3D dwc_pcie_pmu_event_start, + .stop =3D dwc_pcie_pmu_event_stop, + .read =3D dwc_pcie_pmu_event_read, + .attr_groups =3D pcie_info->pcie_pmu_attr_groups, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + }; + + name =3D devm_kasprintf(priv->dev, GFP_KERNEL, "pcie_bdf_%x", + pcie_info->bdf); + if (!name) + return -ENOMEM; + + /* Pick one CPU to be the preferred one to use */ + pcie_pmu->on_cpu =3D raw_smp_processor_id(); + + ret =3D perf_pmu_register(&pcie_pmu->pmu, name, -1); + if (ret) { + pci_err(pcie_info->pdev, "Error %d registering PMU @%x\n", ret, + pcie_info->bdf); + return ret; + } + + pcie_info->pmu_is_register =3D DWC_PCIE_PMU_HAS_REGISTER; + + return ret; +} + +static int dwc_pcie_pmu_remove(struct platform_device *pdev) +{ + struct dwc_pcie_pmu_priv *priv =3D platform_get_drvdata(pdev); + int index; + struct dwc_pcie_pmu *pcie_pmu; + + for (index =3D 0; index < priv->pcie_ctrl_num; index++) + if (priv->pcie_table[index].pmu_is_register) { + pcie_pmu =3D &priv->pcie_table[index].pcie_pmu; + perf_pmu_unregister(&pcie_pmu->pmu); + } + return 0; +} + +static int dwc_pcie_pmu_probe(struct platform_device *pdev) +{ + int ret =3D 0; + int pcie_index; + struct dwc_pcie_pmu_priv *priv; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->dev =3D &pdev->dev; + platform_set_drvdata(pdev, priv); + + /* If PMU is not support on current platform, keep slient */ + if (dwc_pcie_pmu_discover(priv)) + return 0; + + for (pcie_index =3D 0; pcie_index < priv->pcie_ctrl_num; pcie_index++) { + struct pci_dev *rp =3D priv->pcie_table[pcie_index].pdev; + + ret =3D __dwc_pcie_pmu_probe(priv, &priv->pcie_table[pcie_index]); + if (ret) { + dev_err(&rp->dev, "PCIe PMU probe fail\n"); + goto pmu_unregister; + } + } + dev_info(&pdev->dev, "PCIe PMUs registered\n"); + + return 0; + +pmu_unregister: + dwc_pcie_pmu_remove(pdev); + + return ret; +} + +static struct platform_driver dwc_pcie_pmu_driver =3D { + .probe =3D dwc_pcie_pmu_probe, + .remove =3D dwc_pcie_pmu_remove, + .driver =3D {.name =3D DRV_NAME,}, +}; + +static int __init dwc_pcie_pmu_init(void) +{ + int ret; + + ret =3D platform_driver_register(&dwc_pcie_pmu_driver); + + if (ret) + return ret; + + dwc_pcie_pmu_dev =3D + platform_device_register_simple(DEV_NAME, -1, NULL, 0); + if (IS_ERR(dwc_pcie_pmu_dev)) { + platform_driver_unregister(&dwc_pcie_pmu_driver); + return PTR_ERR(dwc_pcie_pmu_dev); + } + + return 0; +} + +static void __exit dwc_pcie_pmu_exit(void) +{ + platform_device_unregister(dwc_pcie_pmu_dev); + platform_driver_unregister(&dwc_pcie_pmu_driver); +} + +module_init(dwc_pcie_pmu_init); +module_exit(dwc_pcie_pmu_exit); + +MODULE_DESCRIPTION("PMU driver for DesignWare Cores PCI Express Controller= "); +MODULE_AUTHOR("xueshuai@linux.alibaba.com"); +MODULE_AUTHOR("yinxuan_cw@linux.alibaba.com"); +MODULE_LICENSE("GPL v2"); --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95022C77B75 for ; Tue, 16 May 2023 13:01:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233393AbjEPNBl (ORCPT ); Tue, 16 May 2023 09:01:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233341AbjEPNB3 (ORCPT ); Tue, 16 May 2023 09:01:29 -0400 Received: from out30-132.freemail.mail.aliyun.com (out30-132.freemail.mail.aliyun.com [115.124.30.132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53BE710D0; Tue, 16 May 2023 06:01:25 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R131e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045168;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0Vioby17_1684242081; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vioby17_1684242081) by smtp.aliyun-inc.com; Tue, 16 May 2023 21:01:22 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v4 2/4] PCI: move Alibaba Vendor ID linux/pci_ids.h Date: Tue, 16 May 2023 21:01:08 +0800 Message-Id: <20230516130110.59632-3-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move Alibaba Vendor ID (0x1ded) to linux/pci_ids.h so that it can shared by several drivers. Signed-off-by: Shuai Xue --- drivers/infiniband/hw/erdma/erdma_hw.h | 2 -- include/linux/pci_ids.h | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/erdma/erdma_hw.h b/drivers/infiniband/hw= /erdma/erdma_hw.h index 37ad1bb1917c..6985b689f632 100644 --- a/drivers/infiniband/hw/erdma/erdma_hw.h +++ b/drivers/infiniband/hw/erdma/erdma_hw.h @@ -11,8 +11,6 @@ #include =20 /* PCIe device related definition. */ -#define PCI_VENDOR_ID_ALIBABA 0x1ded - #define ERDMA_PCI_WIDTH 64 #define ERDMA_FUNC_BAR 0 #define ERDMA_MISX_BAR 2 diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 45c3d62e616d..d07791bae9c5 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2585,6 +2585,8 @@ #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 =20 +#define PCI_VENDOR_ID_ALIBABA 0x1ded + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 397C6C7EE2D for ; Mon, 22 May 2023 03:55:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231582AbjEVDyz (ORCPT ); Sun, 21 May 2023 23:54:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229620AbjEVDyl (ORCPT ); Sun, 21 May 2023 23:54:41 -0400 Received: from out30-99.freemail.mail.aliyun.com (out30-99.freemail.mail.aliyun.com [115.124.30.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC6D5C4; Sun, 21 May 2023 20:54:39 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R491e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045170;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=15;SR=0;TI=SMTPD_---0Vj6oJHi_1684727676; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vj6oJHi_1684727676) by smtp.aliyun-inc.com; Mon, 22 May 2023 11:54:36 +0800 From: Shuai Xue To: chengyou@linux.alibaba.com, kaishen@linux.alibaba.com, helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v5 2/4] PCI: move Alibaba Vendor ID linux/pci_ids.h Date: Mon, 22 May 2023 11:54:26 +0800 Message-Id: <20230522035428.69441-3-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move Alibaba Vendor ID (0x1ded) to linux/pci_ids.h so that it can shared by several drivers. Signed-off-by: Shuai Xue --- drivers/infiniband/hw/erdma/erdma_hw.h | 2 -- include/linux/pci_ids.h | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/erdma/erdma_hw.h b/drivers/infiniband/hw= /erdma/erdma_hw.h index 76ce2856be28..ee35ebef9ee7 100644 --- a/drivers/infiniband/hw/erdma/erdma_hw.h +++ b/drivers/infiniband/hw/erdma/erdma_hw.h @@ -11,8 +11,6 @@ #include =20 /* PCIe device related definition. */ -#define PCI_VENDOR_ID_ALIBABA 0x1ded - #define ERDMA_PCI_WIDTH 64 #define ERDMA_FUNC_BAR 0 #define ERDMA_MISX_BAR 2 diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 95f33dadb2be..9e8aec472f06 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2586,6 +2586,8 @@ #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 =20 +#define PCI_VENDOR_ID_ALIBABA 0x1ded + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B52C5ECAAD3 for ; Sat, 17 Sep 2022 12:11:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229639AbiIQMK7 (ORCPT ); Sat, 17 Sep 2022 08:10:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229586AbiIQMKt (ORCPT ); Sat, 17 Sep 2022 08:10:49 -0400 Received: from out30-42.freemail.mail.aliyun.com (out30-42.freemail.mail.aliyun.com [115.124.30.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DD1B2B1B7 for ; Sat, 17 Sep 2022 05:10:45 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R141e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046051;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=10;SR=0;TI=SMTPD_---0VQ-l72Q_1663416642; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VQ-l72Q_1663416642) by smtp.aliyun-inc.com; Sat, 17 Sep 2022 20:10:43 +0800 From: Shuai Xue To: will@kernel.org, Jonathan.Cameron@Huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v1 3/3] MAINTAINERS: add maintainers for DesignWare PCIe PMU driver Date: Sat, 17 Sep 2022 20:10:36 +0800 Message-Id: <20220917121036.14864-4-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add maintainers for Synopsys DesignWare PCIe PMU driver and driver document. Signed-off-by: Shuai Xue --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 936490dcc97b..2a6965e97be7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19731,6 +19731,12 @@ L: linux-mmc@vger.kernel.org S: Maintained F: drivers/mmc/host/dw_mmc* =20 +SYNOPSYS SYNOPSYS DESIGNWARE PCIE PMU DRIVER +M: Shuai Xue +S: Supported +F: Documentation/admin-guide/perf/dwc_pcie_pmu.rst +F: drivers/perf/dwc_pcie_pmu.c + SYNOPSYS HSDK RESET CONTROLLER DRIVER M: Eugeniy Paltsev S: Supported --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17D47C77B75 for ; Tue, 16 May 2023 13:01:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233397AbjEPNBo (ORCPT ); Tue, 16 May 2023 09:01:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233365AbjEPNBb (ORCPT ); Tue, 16 May 2023 09:01:31 -0400 Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A352E2; Tue, 16 May 2023 06:01:27 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R471e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045192;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0Vioby1n_1684242082; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vioby1n_1684242082) by smtp.aliyun-inc.com; Tue, 16 May 2023 21:01:23 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v4 3/4] drivers/perf: add DesignWare PCIe PMU driver Date: Tue, 16 May 2023 21:01:09 +0800 Message-Id: <20230516130110.59632-4-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds the PCIe Performance Monitoring Unit (PMU) driver support for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express Core controller IP which provides statistics feature. The PMU is not a PCIe Root Complex integrated End Point(RCiEP) device but only register counters provided by each PCIe Root Port. To facilitate collection of statistics the controller provides the following two features for each Root Port: - Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) - Event counters (Error and Non-Error for lanes) Note, only one counter for each type and does not overflow interrupt. This driver adds PMU devices for each PCIe Root Port. And the PMU device is named based the BDF of Root Port. For example, 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) the PMU device name for this Root Port is dwc_rootport_3018. Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ average RX bandwidth can be calculated like this: PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window Signed-off-by: Shuai Xue --- drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/dwc_pcie_pmu.c | 700 ++++++++++++++++++++++++++++++++++++ 3 files changed, 708 insertions(+) create mode 100644 drivers/perf/dwc_pcie_pmu.c diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 711f82400086..d5750cbc67c4 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -209,6 +209,13 @@ config MARVELL_CN10K_DDR_PMU Enable perf support for Marvell DDR Performance monitoring event on CN10K platform. =20 +config DWC_PCIE_PMU + tristate "Enable Synopsys DesignWare PCIe PMU Support" + depends on ARM64 || COMPILE_TEST + help + Enable perf support for Synopsys DesignWare PCIe PMU Performance + monitoring event on Yitian 710 platform. + source "drivers/perf/arm_cspmu/Kconfig" =20 source "drivers/perf/amlogic/Kconfig" diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index dabc859540ce..13a6d1b286da 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -22,5 +22,6 @@ obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) +=3D marvell_cn10k_ta= d_pmu.o obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) +=3D marvell_cn10k_ddr_pmu.o obj-$(CONFIG_APPLE_M1_CPU_PMU) +=3D apple_m1_cpu_pmu.o obj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) +=3D alibaba_uncore_drw_pmu.o +obj-$(CONFIG_DWC_PCIE_PMU) +=3D dwc_pcie_pmu.o obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) +=3D arm_cspmu/ obj-$(CONFIG_MESON_DDR_PMU) +=3D amlogic/ diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c new file mode 100644 index 000000000000..1ecb06579137 --- /dev/null +++ b/drivers/perf/dwc_pcie_pmu.c @@ -0,0 +1,700 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare PCIe PMU driver + * + * Copyright (C) 2021-2023 Alibaba Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DWC_PCIE_VSEC_RAS_DES_ID 0x02 + +#define DWC_PCIE_EVENT_CNT_CTL 0x8 +/* + * Event Counter Data Select includes two parts: + * - 27-24: Group number(4-bit: 0..0x7) + * - 23-16: Event number(8-bit: 0..0x13) within the Group + * + * Put them togother as TRM used. + */ +#define DWC_PCIE_CNT_EVENT_SEL GENMASK(27, 16) +#define DWC_PCIE_CNT_LANE_SEL GENMASK(11, 8) +#define DWC_PCIE_CNT_STATUS BIT(7) +#define DWC_PCIE_CNT_ENABLE GENMASK(4, 2) +#define DWC_PCIE_PER_EVENT_OFF 0x1 +#define DWC_PCIE_PER_EVENT_ON 0x3 +#define DWC_PCIE_EVENT_CLEAR GENMASK(1, 0) +#define DWC_PCIE_EVENT_PER_CLEAR 0x1 + +#define DWC_PCIE_EVENT_CNT_DATA 0xC + +#define DWC_PCIE_TIME_BASED_ANAL_CTL 0x10 +#define DWC_PCIE_TIME_BASED_REPORT_SEL GENMASK(31, 24) +#define DWC_PCIE_TIME_BASED_DURATION_SEL GENMASK(15, 8) +#define DWC_PCIE_DURATION_MANUAL_CTL 0x0 +#define DWC_PCIE_DURATION_1MS 0x1 +#define DWC_PCIE_DURATION_10MS 0x2 +#define DWC_PCIE_DURATION_100MS 0x3 +#define DWC_PCIE_DURATION_1S 0x4 +#define DWC_PCIE_DURATION_2S 0x5 +#define DWC_PCIE_DURATION_4S 0x6 +#define DWC_PCIE_DURATION_4US 0xff +#define DWC_PCIE_TIME_BASED_TIMER_START BIT(0) +#define DWC_PCIE_TIME_BASED_CNT_ENABLE 0x1 + +#define DWC_PCIE_TIME_BASED_ANAL_DATA_REG_LOW 0x14 +#define DWC_PCIE_TIME_BASED_ANAL_DATA_REG_HIGH 0x18 + +/* Event attributes */ +#define DWC_PCIE_CONFIG_EVENTID GENMASK(15, 0) +#define DWC_PCIE_CONFIG_TYPE GENMASK(19, 16) +#define DWC_PCIE_CONFIG_LANE GENMASK(27, 20) + +#define DWC_PCIE_EVENT_ID(event) FIELD_GET(DWC_PCIE_CONFIG_EVENTID, (event= )->attr.config) +#define DWC_PCIE_EVENT_TYPE(event) FIELD_GET(DWC_PCIE_CONFIG_TYPE, (event)= ->attr.config) +#define DWC_PCIE_EVENT_LANE(event) FIELD_GET(DWC_PCIE_CONFIG_LANE, (event)= ->attr.config) + +enum dwc_pcie_event_type { + DWC_PCIE_TYPE_INVALID, + DWC_PCIE_TIME_BASE_EVENT, + DWC_PCIE_LANE_EVENT, +}; + +#define DWC_PCIE_LANE_EVENT_MAX_PERIOD (GENMASK_ULL(31, 0)) +#define DWC_PCIE_TIME_BASED_EVENT_MAX_PERIOD (GENMASK_ULL(63, 0)) + + +struct dwc_pcie_pmu { + struct pci_dev *pdev; /* Root Port device */ + u32 ras_des; /* RAS DES capability offset */ + u32 nr_lanes; + + struct list_head pmu_node; + struct hlist_node cpuhp_node; + struct pmu pmu; + struct perf_event *event; + int oncpu; +}; + +struct dwc_pcie_pmu_priv { + struct device *dev; + struct list_head pmu_nodes; +}; + +#define to_dwc_pcie_pmu(p) (container_of(p, struct dwc_pcie_pmu, pmu)) + +static struct platform_device *dwc_pcie_pmu_dev; +static int dwc_pcie_pmu_hp_state; + +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(pcie_pmu->oncpu)); +} +static DEVICE_ATTR_RO(cpumask); + +static struct attribute *dwc_pcie_pmu_cpumask_attrs[] =3D { + &dev_attr_cpumask.attr, + NULL +}; + +static struct attribute_group dwc_pcie_cpumask_attr_group =3D { + .attrs =3D dwc_pcie_pmu_cpumask_attrs, +}; + +struct dwc_pcie_format_attr { + struct device_attribute attr; + u64 field; + int config; +}; + +static ssize_t dwc_pcie_pmu_format_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_format_attr *fmt =3D container_of(attr, typeof(*fmt), att= r); + int lo =3D __ffs(fmt->field), hi =3D __fls(fmt->field); + + return sysfs_emit(buf, "config:%d-%d\n", lo, hi); +} + +#define _dwc_pcie_format_attr(_name, _cfg, _fld) \ + (&((struct dwc_pcie_format_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_pmu_format_show, NULL), \ + .config =3D _cfg, \ + .field =3D _fld, \ + }})[0].attr.attr) + +#define dwc_pcie_format_attr(_name, _fld) _dwc_pcie_format_attr(_name, 0, = _fld) + +static struct attribute *dwc_pcie_format_attrs[] =3D { + dwc_pcie_format_attr(type, DWC_PCIE_CONFIG_TYPE), + dwc_pcie_format_attr(eventid, DWC_PCIE_CONFIG_EVENTID), + dwc_pcie_format_attr(lane, DWC_PCIE_CONFIG_LANE), + NULL, +}; + +static struct attribute_group dwc_pcie_format_attrs_group =3D { + .name =3D "format", + .attrs =3D dwc_pcie_format_attrs, +}; + +struct dwc_pcie_event_attr { + struct device_attribute attr; + enum dwc_pcie_event_type type; + u16 eventid; + u8 lane; +}; + +static ssize_t dwc_pcie_event_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dwc_pcie_event_attr *eattr; + + eattr =3D container_of(attr, typeof(*eattr), attr); + + if (eattr->type =3D=3D DWC_PCIE_LANE_EVENT) + return sysfs_emit(buf, "eventid=3D0x%x,type=3D0x%x,lane=3D?\n", + eattr->eventid, eattr->type); + + return sysfs_emit(buf, "eventid=3D0x%x,type=3D0x%x\n", eattr->eventid, + eattr->type); +} + +#define DWC_PCIE_EVENT_ATTR(_name, _type, _eventid, _lane) \ + (&((struct dwc_pcie_event_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_event_show, NULL), \ + .type =3D _type, \ + .eventid =3D _eventid, \ + .lane =3D _lane, \ + }})[0].attr.attr) + +#define DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(_name, _eventid) \ + DWC_PCIE_EVENT_ATTR(_name, DWC_PCIE_TIME_BASE_EVENT, _eventid, 0) +#define DWC_PCIE_PMU_LANE_EVENT_ATTR(_name, _eventid) \ + DWC_PCIE_EVENT_ATTR(_name, DWC_PCIE_LANE_EVENT, _eventid, 0) + +static struct attribute *dwc_pcie_pmu_time_event_attrs[] =3D { + /* Group #0 */ + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(one_cycle, 0x00), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(TX_L0S, 0x01), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(RX_L0S, 0x02), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L0, 0x03), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1, 0x04), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_1, 0x05), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_2, 0x06), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(CFG_RCVRY, 0x07), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(TX_RX_L0S, 0x08), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_AUX, 0x09), + + /* Group #1 */ + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(Tx_PCIe_TLP_Data_Payload, 0x20), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(Rx_PCIe_TLP_Data_Payload, 0x21), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(Tx_CCIX_TLP_Data_Payload, 0x22), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(Rx_CCIX_TLP_Data_Payload, 0x23), + + /* + * Leave it to the user to specify the lane ID to avoid generating + * a list of hundreds of events. + */ + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_ack_dllp, 0x600), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_update_fc_dllp, 0x601), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_ack_dllp, 0x602), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_update_fc_dllp, 0x603), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_nulified_tlp, 0x604), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_nulified_tlp, 0x605), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_duplicate_tl, 0x606), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_memory_write, 0x700), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_memory_read, 0x701), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_configuration_write, 0x702), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_configuration_read, 0x703), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_io_write, 0x704), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_io_read, 0x705), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_completion_without_data, 0x706), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_completion_with_data, 0x707), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_message_tlp, 0x708), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_atomic, 0x709), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_tlp_with_prefix, 0x70A), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_memory_write, 0x70B), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_memory_read, 0x70C), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_io_write, 0x70F), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_io_read, 0x710), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_completion_without_data, 0x711), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_completion_with_data, 0x712), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_message_tlp, 0x713), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_atomic, 0x714), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_tlp_with_prefix, 0x715), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_ccix_tlp, 0x716), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_ccix_tlp, 0x717), + + NULL +}; + +static const struct attribute_group dwc_pcie_event_attrs_group =3D { + .name =3D "events", + .attrs =3D dwc_pcie_pmu_time_event_attrs, +}; + +static const struct attribute_group *dwc_pcie_attr_groups[] =3D { + &dwc_pcie_event_attrs_group, + &dwc_pcie_format_attrs_group, + &dwc_pcie_cpumask_attr_group, + NULL +}; + +static void dwc_pcie_pmu_lane_event_enable(struct dwc_pcie_pmu *pcie_pmu, + bool enable) +{ + struct pci_dev *pdev =3D pcie_pmu->pdev; + u16 ras_des =3D pcie_pmu->ras_des; + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + /* Clear DWC_PCIE_CNT_ENABLE field first */ + val &=3D ~DWC_PCIE_CNT_ENABLE; + if (enable) + val |=3D FIELD_PREP(DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_ON); + else + val |=3D FIELD_PREP(DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_OFF); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_time_based_event_enable(struct dwc_pcie_pmu *pcie= _pmu, + bool enable) +{ + struct pci_dev *pdev =3D pcie_pmu->pdev; + u16 ras_des =3D pcie_pmu->ras_des; + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + &val); + + if (enable) + val |=3D DWC_PCIE_TIME_BASED_CNT_ENABLE; + else + val &=3D ~DWC_PCIE_TIME_BASED_CNT_ENABLE; + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + val); +} + +static u64 dwc_pcie_pmu_read_lane_event_counter(struct dwc_pcie_pmu *pcie_= pmu) +{ + struct pci_dev *pdev =3D pcie_pmu->pdev; + u16 ras_des =3D pcie_pmu->ras_des; + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_DATA, &val); + + return val; +} + +static u64 dwc_pcie_pmu_read_time_based_counter(struct dwc_pcie_pmu *pcie_= pmu) +{ + struct pci_dev *pdev =3D pcie_pmu->pdev; + u16 ras_des =3D pcie_pmu->ras_des; + u64 count; + u32 val; + + pci_read_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_DATA_REG_HIGH, &val); + count =3D val; + count <<=3D 32; + + pci_read_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_DATA_REG_LOW, &val); + + count +=3D val; + + return count; +} + +static void dwc_pcie_pmu_event_update(struct perf_event *event) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + u64 delta, prev, now; + + do { + prev =3D local64_read(&hwc->prev_count); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + now =3D dwc_pcie_pmu_read_lane_event_counter(pcie_pmu); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + now =3D dwc_pcie_pmu_read_time_based_counter(pcie_pmu); + + } while (local64_cmpxchg(&hwc->prev_count, prev, now) !=3D prev); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + delta =3D (now - prev) & DWC_PCIE_LANE_EVENT_MAX_PERIOD; + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + delta =3D (now - prev) & DWC_PCIE_TIME_BASED_EVENT_MAX_PERIOD; + + local64_add(delta, &event->count); +} + +static int dwc_pcie_pmu_event_init(struct perf_event *event) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + struct perf_event *sibling; + u32 lane; + + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + /* We don't support sampling */ + if (is_sampling_event(event)) + return -EINVAL; + + /* We cannot support task bound events */ + if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + if (event->group_leader !=3D event && + !is_software_event(event->group_leader)) + return -EINVAL; + + for_each_sibling_event(sibling, event->group_leader) { + if (sibling->pmu !=3D event->pmu && !is_software_event(sibling)) + return -EINVAL; + } + + if (type =3D=3D DWC_PCIE_LANE_EVENT) { + lane =3D DWC_PCIE_EVENT_LANE(event); + if (lane < 0 || lane >=3D pcie_pmu->nr_lanes) + return -EINVAL; + } + + event->cpu =3D pcie_pmu->oncpu; + + return 0; +} + +static void dwc_pcie_pmu_set_period(struct hw_perf_event *hwc) +{ + local64_set(&hwc->prev_count, 0); +} + +static void dwc_pcie_pmu_event_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + + hwc->state =3D 0; + dwc_pcie_pmu_set_period(hwc); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_lane_event_enable(pcie_pmu, true); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_time_based_event_enable(pcie_pmu, true); +} + +static void dwc_pcie_pmu_event_stop(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + struct hw_perf_event *hwc =3D &event->hw; + + if (event->hw.state & PERF_HES_STOPPED) + return; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_lane_event_enable(pcie_pmu, false); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_time_based_event_enable(pcie_pmu, false); + + dwc_pcie_pmu_event_update(event); + hwc->state |=3D PERF_HES_STOPPED | PERF_HES_UPTODATE; +} + +static int dwc_pcie_pmu_event_add(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct pci_dev *pdev =3D pcie_pmu->pdev; + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + int event_id =3D DWC_PCIE_EVENT_ID(event); + int lane =3D DWC_PCIE_EVENT_LANE(event); + u16 ras_des =3D pcie_pmu->ras_des; + u32 ctrl; + + /* Only one counter and it is in use */ + if (pcie_pmu->event) + return -ENOSPC; + + pcie_pmu->event =3D event; + hwc->state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) { + /* EVENT_COUNTER_DATA_REG needs clear manually */ + ctrl =3D FIELD_PREP(DWC_PCIE_CNT_EVENT_SEL, event_id) | + FIELD_PREP(DWC_PCIE_CNT_LANE_SEL, lane) | + FIELD_PREP(DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_OFF) | + FIELD_PREP(DWC_PCIE_EVENT_CLEAR, DWC_PCIE_EVENT_PER_CLEAR); + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, + ctrl); + } else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) { + /* + * TIME_BASED_ANAL_DATA_REG is a 64 bit register, we can safely + * use it with any manually controlled duration. And it is + * cleared when next measurement starts. + */ + ctrl =3D FIELD_PREP(DWC_PCIE_TIME_BASED_REPORT_SEL, event_id) | + FIELD_PREP(DWC_PCIE_TIME_BASED_DURATION_SEL, + DWC_PCIE_DURATION_MANUAL_CTL) | + DWC_PCIE_TIME_BASED_CNT_ENABLE; + pci_write_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, ctrl); + } + + if (flags & PERF_EF_START) + dwc_pcie_pmu_event_start(event, PERF_EF_RELOAD); + + perf_event_update_userpage(event); + + return 0; +} + +static void dwc_pcie_pmu_event_del(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + + dwc_pcie_pmu_event_stop(event, flags | PERF_EF_UPDATE); + perf_event_update_userpage(event); + pcie_pmu->event =3D NULL; +} + +static int __dwc_pcie_pmu_probe(struct dwc_pcie_pmu_priv *priv) +{ + struct pci_dev *pdev =3D NULL; + struct dwc_pcie_pmu *pcie_pmu; + char *name; + u32 bdf; + int ret; + + INIT_LIST_HEAD(&priv->pmu_nodes); + + /* Match the rootport with VSEC_RAS_DES_ID, and register a PMU for it */ + for_each_pci_dev(pdev) { + u16 vsec; + u32 val; + + if (!(pci_is_pcie(pdev) && + pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT)) + continue; + + vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_ALIBABA, + DWC_PCIE_VSEC_RAS_DES_ID); + if (!vsec) + continue; + + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); + if (PCI_VNDR_HEADER_REV(val) !=3D 0x04 || + PCI_VNDR_HEADER_LEN(val) !=3D 0x100) + continue; + pci_dbg(pdev, + "Detected PCIe Vendor-Specific Extended Capability RAS DES\n"); + + bdf =3D PCI_DEVID(pdev->bus->number, pdev->devfn); + name =3D devm_kasprintf(priv->dev, GFP_KERNEL, "dwc_rootport_%x", + bdf); + if (!name) + return -ENOMEM; + + /* All checks passed, go go go */ + pcie_pmu =3D devm_kzalloc(&pdev->dev, sizeof(*pcie_pmu), GFP_KERNEL); + if (!pcie_pmu) { + pci_dev_put(pdev); + return -ENOMEM; + } + + pcie_pmu->pdev =3D pdev; + pcie_pmu->ras_des =3D vsec; + pcie_pmu->nr_lanes =3D pcie_get_width_cap(pdev); + pcie_pmu->pmu =3D (struct pmu){ + .module =3D THIS_MODULE, + .attr_groups =3D dwc_pcie_attr_groups, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + .task_ctx_nr =3D perf_invalid_context, + .event_init =3D dwc_pcie_pmu_event_init, + .add =3D dwc_pcie_pmu_event_add, + .del =3D dwc_pcie_pmu_event_del, + .start =3D dwc_pcie_pmu_event_start, + .stop =3D dwc_pcie_pmu_event_stop, + .read =3D dwc_pcie_pmu_event_update, + }; + + /* Add this instance to the list used by the offline callback */ + ret =3D cpuhp_state_add_instance(dwc_pcie_pmu_hp_state, + &pcie_pmu->cpuhp_node); + if (ret) { + pci_err(pcie_pmu->pdev, + "Error %d registering hotplug @%x\n", ret, bdf); + return ret; + } + ret =3D perf_pmu_register(&pcie_pmu->pmu, name, -1); + if (ret) { + pci_err(pcie_pmu->pdev, + "Error %d registering PMU @%x\n", ret, bdf); + cpuhp_state_remove_instance_nocalls( + dwc_pcie_pmu_hp_state, &pcie_pmu->cpuhp_node); + return ret; + } + + /* Add registered PMUs and unregister them when this driver remove */ + list_add(&pcie_pmu->pmu_node, &priv->pmu_nodes); + } + + return 0; +} + +static int dwc_pcie_pmu_remove(struct platform_device *pdev) +{ + struct dwc_pcie_pmu_priv *priv =3D platform_get_drvdata(pdev); + struct dwc_pcie_pmu *pcie_pmu; + + list_for_each_entry(pcie_pmu, &priv->pmu_nodes, pmu_node) { + cpuhp_state_remove_instance(dwc_pcie_pmu_hp_state, + &pcie_pmu->cpuhp_node); + perf_pmu_unregister(&pcie_pmu->pmu); + } + + return 0; +} + +static int dwc_pcie_pmu_probe(struct platform_device *pdev) +{ + struct dwc_pcie_pmu_priv *priv; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D &pdev->dev; + platform_set_drvdata(pdev, priv); + + /* If one PMU registration fails, remove all. */ + if (__dwc_pcie_pmu_probe(priv)) + dwc_pcie_pmu_remove(pdev); + + return 0; +} + +static void dwc_pcie_pmu_migrate(struct dwc_pcie_pmu *pcie_pmu, unsigned i= nt cpu) +{ + /* This PMU does NOT support interrupt, just migrate context. */ + perf_pmu_migrate_context(&pcie_pmu->pmu, pcie_pmu->oncpu, cpu); + pcie_pmu->oncpu =3D cpu; +} + +static int dwc_pcie_pmu_online_cpu(unsigned int cpu, struct hlist_node *cp= uhp_node) +{ + struct dwc_pcie_pmu *pcie_pmu; + struct pci_dev *pdev; + int node; + + pcie_pmu =3D hlist_entry_safe(cpuhp_node, struct dwc_pcie_pmu, cpuhp_node= ); + pdev =3D pcie_pmu->pdev; + node =3D dev_to_node(&pdev->dev); + + if (node !=3D NUMA_NO_NODE && cpu_to_node(pcie_pmu->oncpu) !=3D node && + cpu_to_node(cpu) =3D=3D node) + dwc_pcie_pmu_migrate(pcie_pmu, cpu); + + return 0; +} + +static int dwc_pcie_pmu_offline_cpu(unsigned int cpu, struct hlist_node *c= puhp_node) +{ + struct dwc_pcie_pmu *pcie_pmu; + struct pci_dev *pdev; + int node; + cpumask_t mask; + unsigned int target; + + pcie_pmu =3D hlist_entry_safe(cpuhp_node, struct dwc_pcie_pmu, cpuhp_node= ); + if (cpu !=3D pcie_pmu->oncpu) + return 0; + + pdev =3D pcie_pmu->pdev; + node =3D dev_to_node(&pdev->dev); + if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) && + cpumask_andnot(&mask, &mask, cpumask_of(cpu))) + target =3D cpumask_any(&mask); + else + target =3D cpumask_any_but(cpu_online_mask, cpu); + if (target < nr_cpu_ids) + dwc_pcie_pmu_migrate(pcie_pmu, target); + + return 0; +} + +static struct platform_driver dwc_pcie_pmu_driver =3D { + .probe =3D dwc_pcie_pmu_probe, + .remove =3D dwc_pcie_pmu_remove, + .driver =3D {.name =3D "dwc_pcie_pmu",}, +}; + +static int __init dwc_pcie_pmu_init(void) +{ + int ret; + + ret =3D cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/dwc_pcie_pmu:online", + dwc_pcie_pmu_online_cpu, + dwc_pcie_pmu_offline_cpu); + if (ret < 0) + return ret; + + dwc_pcie_pmu_hp_state =3D ret; + + ret =3D platform_driver_register(&dwc_pcie_pmu_driver); + if (ret) { + cpuhp_remove_multi_state(dwc_pcie_pmu_hp_state); + return ret; + } + + dwc_pcie_pmu_dev =3D platform_device_register_simple( + "dwc_pcie_pmu", PLATFORM_DEVID_NONE, NULL, 0); + if (IS_ERR(dwc_pcie_pmu_dev)) { + platform_driver_unregister(&dwc_pcie_pmu_driver); + return PTR_ERR(dwc_pcie_pmu_dev); + } + + return 0; +} + +static void __exit dwc_pcie_pmu_exit(void) +{ + platform_device_unregister(dwc_pcie_pmu_dev); + platform_driver_unregister(&dwc_pcie_pmu_driver); +} + +module_init(dwc_pcie_pmu_init); +module_exit(dwc_pcie_pmu_exit); + +MODULE_DESCRIPTION("PMU driver for DesignWare Cores PCI Express Controller= "); +MODULE_AUTHOR("Shuai xue "); +MODULE_AUTHOR("Wen Cheng "); +MODULE_LICENSE("GPL v2"); --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38F1AC77B72 for ; Mon, 17 Apr 2023 06:17:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229967AbjDQGRv (ORCPT ); Mon, 17 Apr 2023 02:17:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229742AbjDQGRp (ORCPT ); Mon, 17 Apr 2023 02:17:45 -0400 Received: from out30-132.freemail.mail.aliyun.com (out30-132.freemail.mail.aliyun.com [115.124.30.132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40BBB30E8; Sun, 16 Apr 2023 23:17:42 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R101e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046051;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0VgDPlH8_1681712258; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VgDPlH8_1681712258) by smtp.aliyun-inc.com; Mon, 17 Apr 2023 14:17:39 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v3 3/3] MAINTAINERS: add maintainers for DesignWare PCIe PMU driver Date: Mon, 17 Apr 2023 14:17:29 +0800 Message-Id: <20230417061729.84422-4-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add maintainers for Synopsys DesignWare PCIe PMU driver and driver document. Signed-off-by: Shuai Xue --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 90abe83c02f3..6d96e5bb8174 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20279,6 +20279,12 @@ L: linux-mmc@vger.kernel.org S: Maintained F: drivers/mmc/host/dw_mmc* =20 +SYNOPSYS DESIGNWARE PCIE PMU DRIVER +M: Shuai Xue +S: Supported +F: Documentation/admin-guide/perf/dwc_pcie_pmu.rst +F: drivers/perf/dwc_pcie_pmu.c + SYNOPSYS HSDK RESET CONTROLLER DRIVER M: Eugeniy Paltsev S: Supported --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A834C77B61 for ; Mon, 10 Apr 2023 03:17:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229589AbjDJDRb (ORCPT ); Sun, 9 Apr 2023 23:17:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229541AbjDJDRS (ORCPT ); Sun, 9 Apr 2023 23:17:18 -0400 Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48C6930C6; Sun, 9 Apr 2023 20:17:17 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R171e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046059;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0VfeyoFa_1681096632; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0VfeyoFa_1681096632) by smtp.aliyun-inc.com; Mon, 10 Apr 2023 11:17:13 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, robin.murphy@arm.com, mark.rutland@arm.com, baolin.wang@linux.alibaba.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v2 3/3] MAINTAINERS: add maintainers for DesignWare PCIe PMU driver Date: Mon, 10 Apr 2023 11:17:02 +0800 Message-Id: <20230410031702.68355-4-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add maintainers for Synopsys DesignWare PCIe PMU driver and driver document. Signed-off-by: Shuai Xue --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e01e546f3a90..52e9b0b91272 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20278,6 +20278,12 @@ L: linux-mmc@vger.kernel.org S: Maintained F: drivers/mmc/host/dw_mmc* =20 +SYNOPSYS DESIGNWARE PCIE PMU DRIVER +M: Shuai Xue +S: Supported +F: Documentation/admin-guide/perf/dwc_pcie_pmu.rst +F: drivers/perf/dwc_pcie_pmu.c + SYNOPSYS HSDK RESET CONTROLLER DRIVER M: Eugeniy Paltsev S: Supported --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2958AC7EE23 for ; Mon, 22 May 2023 03:55:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231474AbjEVDzE (ORCPT ); Sun, 21 May 2023 23:55:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231351AbjEVDyo (ORCPT ); Sun, 21 May 2023 23:54:44 -0400 Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64184BE; Sun, 21 May 2023 20:54:41 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R451e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046056;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=15;SR=0;TI=SMTPD_---0Vj6oJIJ_1684727677; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vj6oJIJ_1684727677) by smtp.aliyun-inc.com; Mon, 22 May 2023 11:54:38 +0800 From: Shuai Xue To: chengyou@linux.alibaba.com, kaishen@linux.alibaba.com, helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v5 3/4] drivers/perf: add DesignWare PCIe PMU driver Date: Mon, 22 May 2023 11:54:27 +0800 Message-Id: <20230522035428.69441-4-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit adds the PCIe Performance Monitoring Unit (PMU) driver support for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express Core controller IP which provides statistics feature. The PMU is not a PCIe Root Complex integrated End Point(RCiEP) device but only register counters provided by each PCIe Root Port. To facilitate collection of statistics the controller provides the following two features for each Root Port: - Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) - Event counters (Error and Non-Error for lanes) Note, only one counter for each type and does not overflow interrupt. This driver adds PMU devices for each PCIe Root Port. And the PMU device is named based the BDF of Root Port. For example, 30:03.0 PCI bridge: Device 1ded:8000 (rev 01) the PMU device name for this Root Port is dwc_rootport_3018. Example usage of counting PCIe RX TLP data payload (Units of 16 bytes):: $# perf stat -a -e dwc_rootport_3018/Rx_PCIe_TLP_Data_Payload/ average RX bandwidth can be calculated like this: PCIe TX Bandwidth =3D PCIE_TX_DATA * 16B / Measure_Time_Window Signed-off-by: Shuai Xue Reported-by: kernel test robot Link: https://lore.kernel.org/oe-kbuild-all/202305170639.XU3djFZX-lkp@intel= .com/ Reviewed-by: Baolin Wang --- drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/dwc_pcie_pmu.c | 701 ++++++++++++++++++++++++++++++++++++ 3 files changed, 709 insertions(+) create mode 100644 drivers/perf/dwc_pcie_pmu.c diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 711f82400086..6ff3921d7a62 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -209,6 +209,13 @@ config MARVELL_CN10K_DDR_PMU Enable perf support for Marvell DDR Performance monitoring event on CN10K platform. =20 +config DWC_PCIE_PMU + tristate "Enable Synopsys DesignWare PCIe PMU Support" + depends on (ARM64 && PCI) + help + Enable perf support for Synopsys DesignWare PCIe PMU Performance + monitoring event on Yitian 710 platform. + source "drivers/perf/arm_cspmu/Kconfig" =20 source "drivers/perf/amlogic/Kconfig" diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index dabc859540ce..13a6d1b286da 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -22,5 +22,6 @@ obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) +=3D marvell_cn10k_ta= d_pmu.o obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) +=3D marvell_cn10k_ddr_pmu.o obj-$(CONFIG_APPLE_M1_CPU_PMU) +=3D apple_m1_cpu_pmu.o obj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) +=3D alibaba_uncore_drw_pmu.o +obj-$(CONFIG_DWC_PCIE_PMU) +=3D dwc_pcie_pmu.o obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) +=3D arm_cspmu/ obj-$(CONFIG_MESON_DDR_PMU) +=3D amlogic/ diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c new file mode 100644 index 000000000000..e4e85575ea7d --- /dev/null +++ b/drivers/perf/dwc_pcie_pmu.c @@ -0,0 +1,701 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare PCIe PMU driver + * + * Copyright (C) 2021-2023 Alibaba Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DWC_PCIE_VSEC_RAS_DES_ID 0x02 + +#define DWC_PCIE_EVENT_CNT_CTL 0x8 + +/* + * Event Counter Data Select includes two parts: + * - 27-24: Group number(4-bit: 0..0x7) + * - 23-16: Event number(8-bit: 0..0x13) within the Group + * + * Put them togother as TRM used. + */ +#define DWC_PCIE_CNT_EVENT_SEL GENMASK(27, 16) +#define DWC_PCIE_CNT_LANE_SEL GENMASK(11, 8) +#define DWC_PCIE_CNT_STATUS BIT(7) +#define DWC_PCIE_CNT_ENABLE GENMASK(4, 2) +#define DWC_PCIE_PER_EVENT_OFF 0x1 +#define DWC_PCIE_PER_EVENT_ON 0x3 +#define DWC_PCIE_EVENT_CLEAR GENMASK(1, 0) +#define DWC_PCIE_EVENT_PER_CLEAR 0x1 + +#define DWC_PCIE_EVENT_CNT_DATA 0xC + +#define DWC_PCIE_TIME_BASED_ANAL_CTL 0x10 +#define DWC_PCIE_TIME_BASED_REPORT_SEL GENMASK(31, 24) +#define DWC_PCIE_TIME_BASED_DURATION_SEL GENMASK(15, 8) +#define DWC_PCIE_DURATION_MANUAL_CTL 0x0 +#define DWC_PCIE_DURATION_1MS 0x1 +#define DWC_PCIE_DURATION_10MS 0x2 +#define DWC_PCIE_DURATION_100MS 0x3 +#define DWC_PCIE_DURATION_1S 0x4 +#define DWC_PCIE_DURATION_2S 0x5 +#define DWC_PCIE_DURATION_4S 0x6 +#define DWC_PCIE_DURATION_4US 0xFF +#define DWC_PCIE_TIME_BASED_TIMER_START BIT(0) +#define DWC_PCIE_TIME_BASED_CNT_ENABLE 0x1 + +#define DWC_PCIE_TIME_BASED_ANAL_DATA_REG_LOW 0x14 +#define DWC_PCIE_TIME_BASED_ANAL_DATA_REG_HIGH 0x18 + +/* Event attributes */ +#define DWC_PCIE_CONFIG_EVENTID GENMASK(15, 0) +#define DWC_PCIE_CONFIG_TYPE GENMASK(19, 16) +#define DWC_PCIE_CONFIG_LANE GENMASK(27, 20) + +#define DWC_PCIE_EVENT_ID(event) FIELD_GET(DWC_PCIE_CONFIG_EVENTID, (event= )->attr.config) +#define DWC_PCIE_EVENT_TYPE(event) FIELD_GET(DWC_PCIE_CONFIG_TYPE, (event)= ->attr.config) +#define DWC_PCIE_EVENT_LANE(event) FIELD_GET(DWC_PCIE_CONFIG_LANE, (event)= ->attr.config) + +enum dwc_pcie_event_type { + DWC_PCIE_TYPE_INVALID, + DWC_PCIE_TIME_BASE_EVENT, + DWC_PCIE_LANE_EVENT, +}; + +#define DWC_PCIE_LANE_EVENT_MAX_PERIOD GENMASK_ULL(31, 0) +#define DWC_PCIE_TIME_BASED_EVENT_MAX_PERIOD GENMASK_ULL(63, 0) + + +struct dwc_pcie_pmu { + struct pci_dev *pdev; /* Root Port device */ + u16 ras_des; /* RAS DES capability offset */ + u32 nr_lanes; + + struct list_head pmu_node; + struct hlist_node cpuhp_node; + struct pmu pmu; + struct perf_event *event; + int oncpu; +}; + +struct dwc_pcie_pmu_priv { + struct device *dev; + struct list_head pmu_nodes; +}; + +#define to_dwc_pcie_pmu(p) (container_of(p, struct dwc_pcie_pmu, pmu)) + +static struct platform_device *dwc_pcie_pmu_dev; +static int dwc_pcie_pmu_hp_state; + +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(pcie_pmu->oncpu)); +} +static DEVICE_ATTR_RO(cpumask); + +static struct attribute *dwc_pcie_pmu_cpumask_attrs[] =3D { + &dev_attr_cpumask.attr, + NULL +}; + +static struct attribute_group dwc_pcie_cpumask_attr_group =3D { + .attrs =3D dwc_pcie_pmu_cpumask_attrs, +}; + +struct dwc_pcie_format_attr { + struct device_attribute attr; + u64 field; + int config; +}; + +static ssize_t dwc_pcie_pmu_format_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dwc_pcie_format_attr *fmt =3D container_of(attr, typeof(*fmt), att= r); + int lo =3D __ffs(fmt->field), hi =3D __fls(fmt->field); + + return sysfs_emit(buf, "config:%d-%d\n", lo, hi); +} + +#define _dwc_pcie_format_attr(_name, _cfg, _fld) \ + (&((struct dwc_pcie_format_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_pmu_format_show, NULL), \ + .config =3D _cfg, \ + .field =3D _fld, \ + }})[0].attr.attr) + +#define dwc_pcie_format_attr(_name, _fld) _dwc_pcie_format_attr(_name, 0, = _fld) + +static struct attribute *dwc_pcie_format_attrs[] =3D { + dwc_pcie_format_attr(type, DWC_PCIE_CONFIG_TYPE), + dwc_pcie_format_attr(eventid, DWC_PCIE_CONFIG_EVENTID), + dwc_pcie_format_attr(lane, DWC_PCIE_CONFIG_LANE), + NULL, +}; + +static struct attribute_group dwc_pcie_format_attrs_group =3D { + .name =3D "format", + .attrs =3D dwc_pcie_format_attrs, +}; + +struct dwc_pcie_event_attr { + struct device_attribute attr; + enum dwc_pcie_event_type type; + u16 eventid; + u8 lane; +}; + +static ssize_t dwc_pcie_event_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dwc_pcie_event_attr *eattr; + + eattr =3D container_of(attr, typeof(*eattr), attr); + + if (eattr->type =3D=3D DWC_PCIE_LANE_EVENT) + return sysfs_emit(buf, "eventid=3D0x%x,type=3D0x%x,lane=3D?\n", + eattr->eventid, eattr->type); + + return sysfs_emit(buf, "eventid=3D0x%x,type=3D0x%x\n", eattr->eventid, + eattr->type); +} + +#define DWC_PCIE_EVENT_ATTR(_name, _type, _eventid, _lane) \ + (&((struct dwc_pcie_event_attr[]) {{ \ + .attr =3D __ATTR(_name, 0444, dwc_pcie_event_show, NULL), \ + .type =3D _type, \ + .eventid =3D _eventid, \ + .lane =3D _lane, \ + }})[0].attr.attr) + +#define DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(_name, _eventid) \ + DWC_PCIE_EVENT_ATTR(_name, DWC_PCIE_TIME_BASE_EVENT, _eventid, 0) +#define DWC_PCIE_PMU_LANE_EVENT_ATTR(_name, _eventid) \ + DWC_PCIE_EVENT_ATTR(_name, DWC_PCIE_LANE_EVENT, _eventid, 0) + +static struct attribute *dwc_pcie_pmu_time_event_attrs[] =3D { + /* Group #0 */ + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(one_cycle, 0x00), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(TX_L0S, 0x01), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(RX_L0S, 0x02), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L0, 0x03), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1, 0x04), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_1, 0x05), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_2, 0x06), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(CFG_RCVRY, 0x07), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(TX_RX_L0S, 0x08), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_AUX, 0x09), + + /* Group #1 */ + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(Tx_PCIe_TLP_Data_Payload, 0x20), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(Rx_PCIe_TLP_Data_Payload, 0x21), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(Tx_CCIX_TLP_Data_Payload, 0x22), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(Rx_CCIX_TLP_Data_Payload, 0x23), + + /* + * Leave it to the user to specify the lane ID to avoid generating + * a list of hundreds of events. + */ + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_ack_dllp, 0x600), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_update_fc_dllp, 0x601), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_ack_dllp, 0x602), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_update_fc_dllp, 0x603), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_nulified_tlp, 0x604), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_nulified_tlp, 0x605), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_duplicate_tl, 0x606), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_memory_write, 0x700), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_memory_read, 0x701), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_configuration_write, 0x702), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_configuration_read, 0x703), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_io_write, 0x704), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_io_read, 0x705), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_completion_without_data, 0x706), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_completion_with_data, 0x707), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_message_tlp, 0x708), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_atomic, 0x709), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_tlp_with_prefix, 0x70A), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_memory_write, 0x70B), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_memory_read, 0x70C), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_io_write, 0x70F), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_io_read, 0x710), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_completion_without_data, 0x711), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_completion_with_data, 0x712), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_message_tlp, 0x713), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_atomic, 0x714), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_tlp_with_prefix, 0x715), + DWC_PCIE_PMU_LANE_EVENT_ATTR(tx_ccix_tlp, 0x716), + DWC_PCIE_PMU_LANE_EVENT_ATTR(rx_ccix_tlp, 0x717), + + NULL +}; + +static const struct attribute_group dwc_pcie_event_attrs_group =3D { + .name =3D "events", + .attrs =3D dwc_pcie_pmu_time_event_attrs, +}; + +static const struct attribute_group *dwc_pcie_attr_groups[] =3D { + &dwc_pcie_event_attrs_group, + &dwc_pcie_format_attrs_group, + &dwc_pcie_cpumask_attr_group, + NULL +}; + +static void dwc_pcie_pmu_lane_event_enable(struct dwc_pcie_pmu *pcie_pmu, + bool enable) +{ + struct pci_dev *pdev =3D pcie_pmu->pdev; + u16 ras_des =3D pcie_pmu->ras_des; + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, &val); + + /* Clear DWC_PCIE_CNT_ENABLE field first */ + val &=3D ~DWC_PCIE_CNT_ENABLE; + if (enable) + val |=3D FIELD_PREP(DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_ON); + else + val |=3D FIELD_PREP(DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_OFF); + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, val); +} + +static void dwc_pcie_pmu_time_based_event_enable(struct dwc_pcie_pmu *pcie= _pmu, + bool enable) +{ + struct pci_dev *pdev =3D pcie_pmu->pdev; + u16 ras_des =3D pcie_pmu->ras_des; + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + &val); + + if (enable) + val |=3D DWC_PCIE_TIME_BASED_CNT_ENABLE; + else + val &=3D ~DWC_PCIE_TIME_BASED_CNT_ENABLE; + + pci_write_config_dword(pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, + val); +} + +static u64 dwc_pcie_pmu_read_lane_event_counter(struct dwc_pcie_pmu *pcie_= pmu) +{ + struct pci_dev *pdev =3D pcie_pmu->pdev; + u16 ras_des =3D pcie_pmu->ras_des; + u32 val; + + pci_read_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_DATA, &val); + + return val; +} + +static u64 dwc_pcie_pmu_read_time_based_counter(struct dwc_pcie_pmu *pcie_= pmu) +{ + struct pci_dev *pdev =3D pcie_pmu->pdev; + u16 ras_des =3D pcie_pmu->ras_des; + u64 count; + u32 val; + + pci_read_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_DATA_REG_HIGH, &val); + count =3D val; + count <<=3D 32; + + pci_read_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_DATA_REG_LOW, &val); + + count +=3D val; + + return count; +} + +static void dwc_pcie_pmu_event_update(struct perf_event *event) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + u64 delta, prev, now; + + do { + prev =3D local64_read(&hwc->prev_count); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + now =3D dwc_pcie_pmu_read_lane_event_counter(pcie_pmu); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + now =3D dwc_pcie_pmu_read_time_based_counter(pcie_pmu); + + } while (local64_cmpxchg(&hwc->prev_count, prev, now) !=3D prev); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + delta =3D (now - prev) & DWC_PCIE_LANE_EVENT_MAX_PERIOD; + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + delta =3D (now - prev) & DWC_PCIE_TIME_BASED_EVENT_MAX_PERIOD; + + local64_add(delta, &event->count); +} + +static int dwc_pcie_pmu_event_init(struct perf_event *event) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + struct perf_event *sibling; + u32 lane; + + if (event->attr.type !=3D event->pmu->type) + return -ENOENT; + + /* We don't support sampling */ + if (is_sampling_event(event)) + return -EINVAL; + + /* We cannot support task bound events */ + if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + if (event->group_leader !=3D event && + !is_software_event(event->group_leader)) + return -EINVAL; + + for_each_sibling_event(sibling, event->group_leader) { + if (sibling->pmu !=3D event->pmu && !is_software_event(sibling)) + return -EINVAL; + } + + if (type =3D=3D DWC_PCIE_LANE_EVENT) { + lane =3D DWC_PCIE_EVENT_LANE(event); + if (lane < 0 || lane >=3D pcie_pmu->nr_lanes) + return -EINVAL; + } + + event->cpu =3D pcie_pmu->oncpu; + + return 0; +} + +static void dwc_pcie_pmu_set_period(struct hw_perf_event *hwc) +{ + local64_set(&hwc->prev_count, 0); +} + +static void dwc_pcie_pmu_event_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + + hwc->state =3D 0; + dwc_pcie_pmu_set_period(hwc); + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_lane_event_enable(pcie_pmu, true); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_time_based_event_enable(pcie_pmu, true); +} + +static void dwc_pcie_pmu_event_stop(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + struct hw_perf_event *hwc =3D &event->hw; + + if (event->hw.state & PERF_HES_STOPPED) + return; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) + dwc_pcie_pmu_lane_event_enable(pcie_pmu, false); + else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) + dwc_pcie_pmu_time_based_event_enable(pcie_pmu, false); + + dwc_pcie_pmu_event_update(event); + hwc->state |=3D PERF_HES_STOPPED | PERF_HES_UPTODATE; +} + +static int dwc_pcie_pmu_event_add(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + struct pci_dev *pdev =3D pcie_pmu->pdev; + struct hw_perf_event *hwc =3D &event->hw; + enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); + int event_id =3D DWC_PCIE_EVENT_ID(event); + int lane =3D DWC_PCIE_EVENT_LANE(event); + u16 ras_des =3D pcie_pmu->ras_des; + u32 ctrl; + + /* Only one counter and it is in use */ + if (pcie_pmu->event) + return -ENOSPC; + + pcie_pmu->event =3D event; + hwc->state =3D PERF_HES_STOPPED | PERF_HES_UPTODATE; + + if (type =3D=3D DWC_PCIE_LANE_EVENT) { + /* EVENT_COUNTER_DATA_REG needs clear manually */ + ctrl =3D FIELD_PREP(DWC_PCIE_CNT_EVENT_SEL, event_id) | + FIELD_PREP(DWC_PCIE_CNT_LANE_SEL, lane) | + FIELD_PREP(DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_OFF) | + FIELD_PREP(DWC_PCIE_EVENT_CLEAR, DWC_PCIE_EVENT_PER_CLEAR); + pci_write_config_dword(pdev, ras_des + DWC_PCIE_EVENT_CNT_CTL, + ctrl); + } else if (type =3D=3D DWC_PCIE_TIME_BASE_EVENT) { + /* + * TIME_BASED_ANAL_DATA_REG is a 64 bit register, we can safely + * use it with any manually controlled duration. And it is + * cleared when next measurement starts. + */ + ctrl =3D FIELD_PREP(DWC_PCIE_TIME_BASED_REPORT_SEL, event_id) | + FIELD_PREP(DWC_PCIE_TIME_BASED_DURATION_SEL, + DWC_PCIE_DURATION_MANUAL_CTL) | + DWC_PCIE_TIME_BASED_CNT_ENABLE; + pci_write_config_dword( + pdev, ras_des + DWC_PCIE_TIME_BASED_ANAL_CTL, ctrl); + } + + if (flags & PERF_EF_START) + dwc_pcie_pmu_event_start(event, PERF_EF_RELOAD); + + perf_event_update_userpage(event); + + return 0; +} + +static void dwc_pcie_pmu_event_del(struct perf_event *event, int flags) +{ + struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); + + dwc_pcie_pmu_event_stop(event, flags | PERF_EF_UPDATE); + perf_event_update_userpage(event); + pcie_pmu->event =3D NULL; +} + +static int __dwc_pcie_pmu_probe(struct dwc_pcie_pmu_priv *priv) +{ + struct pci_dev *pdev =3D NULL; + struct dwc_pcie_pmu *pcie_pmu; + char *name; + u32 bdf; + int ret; + + INIT_LIST_HEAD(&priv->pmu_nodes); + + /* Match the rootport with VSEC_RAS_DES_ID, and register a PMU for it */ + for_each_pci_dev(pdev) { + u16 vsec; + u32 val; + + if (!(pci_is_pcie(pdev) && + pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT)) + continue; + + vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_ALIBABA, + DWC_PCIE_VSEC_RAS_DES_ID); + if (!vsec) + continue; + + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); + if (PCI_VNDR_HEADER_REV(val) !=3D 0x04 || + PCI_VNDR_HEADER_LEN(val) !=3D 0x100) + continue; + pci_dbg(pdev, + "Detected PCIe Vendor-Specific Extended Capability RAS DES\n"); + + bdf =3D PCI_DEVID(pdev->bus->number, pdev->devfn); + name =3D devm_kasprintf(priv->dev, GFP_KERNEL, "dwc_rootport_%x", + bdf); + if (!name) + return -ENOMEM; + + /* All checks passed, go go go */ + pcie_pmu =3D devm_kzalloc(&pdev->dev, sizeof(*pcie_pmu), GFP_KERNEL); + if (!pcie_pmu) { + pci_dev_put(pdev); + return -ENOMEM; + } + + pcie_pmu->pdev =3D pdev; + pcie_pmu->ras_des =3D vsec; + pcie_pmu->nr_lanes =3D pcie_get_width_cap(pdev); + pcie_pmu->pmu =3D (struct pmu){ + .module =3D THIS_MODULE, + .attr_groups =3D dwc_pcie_attr_groups, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + .task_ctx_nr =3D perf_invalid_context, + .event_init =3D dwc_pcie_pmu_event_init, + .add =3D dwc_pcie_pmu_event_add, + .del =3D dwc_pcie_pmu_event_del, + .start =3D dwc_pcie_pmu_event_start, + .stop =3D dwc_pcie_pmu_event_stop, + .read =3D dwc_pcie_pmu_event_update, + }; + + /* Add this instance to the list used by the offline callback */ + ret =3D cpuhp_state_add_instance(dwc_pcie_pmu_hp_state, + &pcie_pmu->cpuhp_node); + if (ret) { + pci_err(pcie_pmu->pdev, + "Error %d registering hotplug @%x\n", ret, bdf); + return ret; + } + ret =3D perf_pmu_register(&pcie_pmu->pmu, name, -1); + if (ret) { + pci_err(pcie_pmu->pdev, + "Error %d registering PMU @%x\n", ret, bdf); + cpuhp_state_remove_instance_nocalls( + dwc_pcie_pmu_hp_state, &pcie_pmu->cpuhp_node); + return ret; + } + + /* Add registered PMUs and unregister them when this driver remove */ + list_add(&pcie_pmu->pmu_node, &priv->pmu_nodes); + } + + return 0; +} + +static int dwc_pcie_pmu_remove(struct platform_device *pdev) +{ + struct dwc_pcie_pmu_priv *priv =3D platform_get_drvdata(pdev); + struct dwc_pcie_pmu *pcie_pmu; + + list_for_each_entry(pcie_pmu, &priv->pmu_nodes, pmu_node) { + cpuhp_state_remove_instance(dwc_pcie_pmu_hp_state, + &pcie_pmu->cpuhp_node); + perf_pmu_unregister(&pcie_pmu->pmu); + } + + return 0; +} + +static int dwc_pcie_pmu_probe(struct platform_device *pdev) +{ + struct dwc_pcie_pmu_priv *priv; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D &pdev->dev; + platform_set_drvdata(pdev, priv); + + /* If one PMU registration fails, remove all. */ + if (__dwc_pcie_pmu_probe(priv)) + dwc_pcie_pmu_remove(pdev); + + return 0; +} + +static void dwc_pcie_pmu_migrate(struct dwc_pcie_pmu *pcie_pmu, unsigned i= nt cpu) +{ + /* This PMU does NOT support interrupt, just migrate context. */ + perf_pmu_migrate_context(&pcie_pmu->pmu, pcie_pmu->oncpu, cpu); + pcie_pmu->oncpu =3D cpu; +} + +static int dwc_pcie_pmu_online_cpu(unsigned int cpu, struct hlist_node *cp= uhp_node) +{ + struct dwc_pcie_pmu *pcie_pmu; + struct pci_dev *pdev; + int node; + + pcie_pmu =3D hlist_entry_safe(cpuhp_node, struct dwc_pcie_pmu, cpuhp_node= ); + pdev =3D pcie_pmu->pdev; + node =3D dev_to_node(&pdev->dev); + + if (node !=3D NUMA_NO_NODE && cpu_to_node(pcie_pmu->oncpu) !=3D node && + cpu_to_node(cpu) =3D=3D node) + dwc_pcie_pmu_migrate(pcie_pmu, cpu); + + return 0; +} + +static int dwc_pcie_pmu_offline_cpu(unsigned int cpu, struct hlist_node *c= puhp_node) +{ + struct dwc_pcie_pmu *pcie_pmu; + struct pci_dev *pdev; + int node; + cpumask_t mask; + unsigned int target; + + pcie_pmu =3D hlist_entry_safe(cpuhp_node, struct dwc_pcie_pmu, cpuhp_node= ); + if (cpu !=3D pcie_pmu->oncpu) + return 0; + + pdev =3D pcie_pmu->pdev; + node =3D dev_to_node(&pdev->dev); + if (cpumask_and(&mask, cpumask_of_node(node), cpu_online_mask) && + cpumask_andnot(&mask, &mask, cpumask_of(cpu))) + target =3D cpumask_any(&mask); + else + target =3D cpumask_any_but(cpu_online_mask, cpu); + if (target < nr_cpu_ids) + dwc_pcie_pmu_migrate(pcie_pmu, target); + + return 0; +} + +static struct platform_driver dwc_pcie_pmu_driver =3D { + .probe =3D dwc_pcie_pmu_probe, + .remove =3D dwc_pcie_pmu_remove, + .driver =3D {.name =3D "dwc_pcie_pmu",}, +}; + +static int __init dwc_pcie_pmu_init(void) +{ + int ret; + + ret =3D cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/dwc_pcie_pmu:online", + dwc_pcie_pmu_online_cpu, + dwc_pcie_pmu_offline_cpu); + if (ret < 0) + return ret; + + dwc_pcie_pmu_hp_state =3D ret; + + ret =3D platform_driver_register(&dwc_pcie_pmu_driver); + if (ret) { + cpuhp_remove_multi_state(dwc_pcie_pmu_hp_state); + return ret; + } + + dwc_pcie_pmu_dev =3D platform_device_register_simple( + "dwc_pcie_pmu", PLATFORM_DEVID_NONE, NULL, 0); + if (IS_ERR(dwc_pcie_pmu_dev)) { + platform_driver_unregister(&dwc_pcie_pmu_driver); + return PTR_ERR(dwc_pcie_pmu_dev); + } + + return 0; +} + +static void __exit dwc_pcie_pmu_exit(void) +{ + platform_device_unregister(dwc_pcie_pmu_dev); + platform_driver_unregister(&dwc_pcie_pmu_driver); +} + +module_init(dwc_pcie_pmu_init); +module_exit(dwc_pcie_pmu_exit); + +MODULE_DESCRIPTION("PMU driver for DesignWare Cores PCI Express Controller= "); +MODULE_AUTHOR("Shuai xue "); +MODULE_AUTHOR("Wen Cheng "); +MODULE_LICENSE("GPL v2"); --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 327BAC77B75 for ; Mon, 22 May 2023 03:55:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231546AbjEVDzI (ORCPT ); Sun, 21 May 2023 23:55:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231348AbjEVDyo (ORCPT ); Sun, 21 May 2023 23:54:44 -0400 Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C927C2; Sun, 21 May 2023 20:54:43 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R261e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046050;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=15;SR=0;TI=SMTPD_---0Vj6oJIw_1684727678; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vj6oJIw_1684727678) by smtp.aliyun-inc.com; Mon, 22 May 2023 11:54:39 +0800 From: Shuai Xue To: chengyou@linux.alibaba.com, kaishen@linux.alibaba.com, helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v5 4/4] MAINTAINERS: add maintainers for DesignWare PCIe PMU driver Date: Mon, 22 May 2023 11:54:28 +0800 Message-Id: <20230522035428.69441-5-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add maintainers for Synopsys DesignWare PCIe PMU driver and driver document. Signed-off-by: Shuai Xue --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e0ad886d3163..70271eed279d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20478,6 +20478,12 @@ L: linux-mmc@vger.kernel.org S: Maintained F: drivers/mmc/host/dw_mmc* =20 +SYNOPSYS DESIGNWARE PCIE PMU DRIVER +M: Shuai Xue +S: Supported +F: Documentation/admin-guide/perf/dwc_pcie_pmu.rst +F: drivers/perf/dwc_pcie_pmu.c + SYNOPSYS HSDK RESET CONTROLLER DRIVER M: Eugeniy Paltsev S: Supported --=20 2.20.1.12.g72788fdb From nobody Fri Apr 3 02:23:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD625C77B7A for ; Tue, 16 May 2023 13:01:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231237AbjEPNBr (ORCPT ); Tue, 16 May 2023 09:01:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232885AbjEPNBc (ORCPT ); Tue, 16 May 2023 09:01:32 -0400 Received: from out30-99.freemail.mail.aliyun.com (out30-99.freemail.mail.aliyun.com [115.124.30.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64AAB173D; Tue, 16 May 2023 06:01:30 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R861e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046059;MF=xueshuai@linux.alibaba.com;NM=1;PH=DS;RN=13;SR=0;TI=SMTPD_---0Vioby2P_1684242084; Received: from localhost.localdomain(mailfrom:xueshuai@linux.alibaba.com fp:SMTPD_---0Vioby2P_1684242084) by smtp.aliyun-inc.com; Tue, 16 May 2023 21:01:25 +0800 From: Shuai Xue To: helgaas@kernel.org, yangyicong@huawei.com, will@kernel.org, Jonathan.Cameron@huawei.com, baolin.wang@linux.alibaba.com, robin.murphy@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, rdunlap@infradead.org, mark.rutland@arm.com, zhuo.song@linux.alibaba.com, xueshuai@linux.alibaba.com Subject: [PATCH v4 4/4] MAINTAINERS: add maintainers for DesignWare PCIe PMU driver Date: Tue, 16 May 2023 21:01:10 +0800 Message-Id: <20230516130110.59632-5-xueshuai@linux.alibaba.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220917121036.14864-1-xueshuai@linux.alibaba.com> References: <20220917121036.14864-1-xueshuai@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add maintainers for Synopsys DesignWare PCIe PMU driver and driver document. Signed-off-by: Shuai Xue --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ebd26b3ca90e..14f4db0f8977 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20378,6 +20378,12 @@ L: linux-mmc@vger.kernel.org S: Maintained F: drivers/mmc/host/dw_mmc* =20 +SYNOPSYS DESIGNWARE PCIE PMU DRIVER +M: Shuai Xue +S: Supported +F: Documentation/admin-guide/perf/dwc_pcie_pmu.rst +F: drivers/perf/dwc_pcie_pmu.c + SYNOPSYS HSDK RESET CONTROLLER DRIVER M: Eugeniy Paltsev S: Supported --=20 2.20.1.12.g72788fdb