From nobody Fri Apr 3 03:54:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26BEAECAAD8 for ; Fri, 16 Sep 2022 12:12:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231357AbiIPMM3 (ORCPT ); Fri, 16 Sep 2022 08:12:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231264AbiIPMMX (ORCPT ); Fri, 16 Sep 2022 08:12:23 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 517C85F102; Fri, 16 Sep 2022 05:12:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id EFDE7B82686; Fri, 16 Sep 2022 12:12:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7444FC4347C; Fri, 16 Sep 2022 12:12:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663330339; bh=OpH/LkFcan6rEPF6JDBQlCDJrC4M5P0hs4ZvJDBbnrk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aTMlMmP/ozrY2LtTOsUOZCxF+j9qjHhjUx2PYRRDg4xAo3mCytowQ4f42HfLpmFaO LYM+xbcfoqguoxNLAt6cVkBY7mv/AA0NZyBy7VOBmdPj1Byj1ZDM0yCl4ByLsiieb+ XRBqFZ4xmyzUJvrSZJfknpueKOctI2bidHyhepxR1b/EEsAyzxjJ1HXIB6TuouyKQS sEfcxbsifgEw8DpnCgUfqCZZ7qFQhA6eOsVLl/PBLKFj8SONUBuCQl95NvI6EQ8UMd cMayKMo4chPpnYN8ycBtnRHGFQwEI6MRv+aqSuYFFip5HkRvPgDY2gQmJCiwQBWzjg ls0+aLecSV91A== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: firmware: document Qualcomm SC8180x SCM Date: Fri, 16 Sep 2022 17:41:59 +0530 Message-Id: <20220916121204.3880182-2-vkoul@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220916121204.3880182-1-vkoul@kernel.org> References: <20220916121204.3880182-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the compatible for Qualcomm SC8180x SCM Signed-off-by: Vinod Koul Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index c5b76c9f7ad0..a8a14da54e53 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -40,6 +40,7 @@ properties: - qcom,scm-msm8998 - qcom,scm-sc7180 - qcom,scm-sc7280 + - qcom,scm-sc8180x - qcom,scm-sc8280xp - qcom,scm-sdm845 - qcom,scm-sdx55 --=20 2.37.3 From nobody Fri Apr 3 03:54:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 025ABC54EE9 for ; Fri, 16 Sep 2022 12:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231472AbiIPMMo (ORCPT ); Fri, 16 Sep 2022 08:12:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231366AbiIPMMf (ORCPT ); Fri, 16 Sep 2022 08:12:35 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F369B089B; Fri, 16 Sep 2022 05:12:26 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0C259B825ED; Fri, 16 Sep 2022 12:12:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 42111C433D6; Fri, 16 Sep 2022 12:12:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663330343; bh=1yC4yByue2GYH632QAml0xc+/AbTMt75z9T2KM9E5/8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KzBWuMVdTPhMTe7OZeES5V8+g4vhkw12tj9mM/M25RaibgJwfS7C3Jsb7o4GhrMgJ RbsmLfuReB/1BCYW9OP5T/V663gzk1deObXpWwfAm/cLR/HV2MPB7MpTPjWmDE27tX dpM73KAvVZVNQatnfqQtU9Ud0T/rpYZqt4ZlWHrX8kzljTh6frj3apEUTjPRG1esBu BhY8Od0s0ZdU8/MLsXWFAc9JlzJL6TgsTHSzLKNIIV2Lnbh5OuNgai3t7G57b5hIk5 cJGFo9nwiE/t/OJKdR7RiPHPjqoNczIdKS9jB2OHFzdGTMiJkDvTPl7bzSVg095lhi 2/83eGzL+6yCQ== From: Vinod Koul To: "Martin K . Petersen" , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Alim Akhtar , Avri Altman , Bart Van Assche , linux-scsi@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] scsi: ufs: dt-bindings: Add SC8180x binding Date: Fri, 16 Sep 2022 17:42:00 +0530 Message-Id: <20220916121204.3880182-3-vkoul@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220916121204.3880182-1-vkoul@kernel.org> References: <20220916121204.3880182-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the UFS HC for SC8180x SoC Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index f2d6298d926c..dd0256357247 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -26,6 +26,7 @@ properties: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - qcom,msm8998-ufshc + - qcom,sc8180x-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6350-ufshc --=20 2.37.3 From nobody Fri Apr 3 03:54:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD1DEC6FA86 for ; Fri, 16 Sep 2022 12:12:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231404AbiIPMMw (ORCPT ); Fri, 16 Sep 2022 08:12:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231368AbiIPMMf (ORCPT ); Fri, 16 Sep 2022 08:12:35 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 463CAB0B04; Fri, 16 Sep 2022 05:12:28 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C887B62B41; Fri, 16 Sep 2022 12:12:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 45D7BC43143; Fri, 16 Sep 2022 12:12:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663330347; bh=3gGcMHmFimfPD8rpeW8RQN1ZNlCrlPvnyk0muFEHR1E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N+tkvv+CSf3zCbI1dirRPAgwseoXj5cvkfdbLhwETGl9HUywBDai8fbyTJuQ72dDO H/no8skPjwqBisbnsJ0Tcm+X5KIBi0aI/WX1VqtvIUZ+aIP2yGnrYOICDk0xTQfoPW vVeYf35NCcampBpmhVg7lv+K5/4tZwjTH6xtN1/4PmVIf5XGhkn+uydHmgZaDpr4Ta KhgJjaCVXY19u5yx5pcbBsD07V50G5noLazKP6KcaMgXS9Z8SZwX/YSKFI35JI4NEH bzUYsYWqUEop+QfvISpYamO7rWRlCJBIaFp7gKeSbApLnTq0oqlXQHt4krUlv5SMJW e5BlCR36bSEmg== From: Vinod Koul To: Greg Kroah-Hartman , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Vinod Koul , Wesley Cheng , linux-usb@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] dt-bindings: usb: qcom,dwc3: Add SC8180x binding Date: Fri, 16 Sep 2022 17:42:01 +0530 Message-Id: <20220916121204.3880182-4-vkoul@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220916121204.3880182-1-vkoul@kernel.org> References: <20220916121204.3880182-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the USB dwc3 controller for SC8180x SoC Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documen= tation/devicetree/bindings/usb/qcom,dwc3.yaml index fea3e7092ace..f33735f3702d 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -24,6 +24,7 @@ properties: - qcom,qcs404-dwc3 - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 + - qcom,sc8180x-dwc3 - qcom,sc8280xp-dwc3 - qcom,sdm660-dwc3 - qcom,sdm845-dwc3 --=20 2.37.3 From nobody Fri Apr 3 03:54:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 155CFC54EE9 for ; Fri, 16 Sep 2022 12:13:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231389AbiIPMM7 (ORCPT ); Fri, 16 Sep 2022 08:12:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231407AbiIPMMj (ORCPT ); Fri, 16 Sep 2022 08:12:39 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71474B0B10; Fri, 16 Sep 2022 05:12:32 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 88ED962B41; Fri, 16 Sep 2022 12:12:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA3BCC433B5; Fri, 16 Sep 2022 12:12:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663330351; bh=+DLTT9UAH1NVWmODamw9HpEGaclxsPw5IVouUKLk+PQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qBRM3jfDI9XVSyn4VY+anlVgP7XK79D3oFVBCsnvQdQEVvWeLnBWsfhyt+AktJdp2 lSCE6COerOZEK1Ej6zELOsoOXjuwwUg/C4lZQZItNxEWaUP82ZKRsUw6RugH78U1hA JcBbUdZLy0Porxr9Yq5v42ojPZoaFONmLfEWC0i4E0IT83mO4AFqXu2EJmLDAsNZqK 79LCOYLHF8n8J4ZGy6Ae04g0T8UW36R/2E25j4bUNFWGwV6XwxJb+Q80lApkRhUrFz JRP93pIkwSz4xaLt0asYUQmGplq44wf/0uTMqJUMrYeyDoVUYSsDVCwXVRzOYszGrQ Hv9WEqi+q/UIA== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH 4/6] arm64: dts: qcom: Introduce the SC8180x platform Date: Fri, 16 Sep 2022 17:42:02 +0530 Message-Id: <20220916121204.3880182-5-vkoul@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220916121204.3880182-1-vkoul@kernel.org> References: <20220916121204.3880182-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Andersson Introduce a base dtsi for the Qualcomm SC8180x platform, with CPUs, global clock controller, SMMU, rpmh clocks, rpmh power-domains, CPUfreq, QUP blocks, UFS, USB, ADSP, CDSP and MPSS and WiFi. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 3939 +++++++++++++++++++++++++ 1 file changed, 3939 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi new file mode 100644 index 000000000000..91f1edf83651 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -0,0 +1,3939 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board_clk: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <38400000>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32764>; + clock-output-names =3D "sleep_clk"; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo485"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains =3D <&CPU_PD0>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + L2_0: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + L3_0: l3-cache { + compatible =3D "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo485"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_100>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains =3D <&CPU_PD1>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + L2_100: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo485"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_200>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains =3D <&CPU_PD2>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + L2_200: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo485"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <602>; + next-level-cache =3D <&L2_300>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains =3D <&CPU_PD3>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + L2_300: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo485"; + reg =3D <0x0 0x400>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_400>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains =3D <&CPU_PD4>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + L2_400: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo485"; + reg =3D <0x0 0x500>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_500>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains =3D <&CPU_PD5>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + L2_500: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo485"; + reg =3D <0x0 0x600>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_600>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains =3D <&CPU_PD6>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + L2_600: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo485"; + reg =3D <0x0 0x700>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + next-level-cache =3D <&L2_700>; + qcom,freq-domain =3D <&cpufreq_hw 1>; + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + power-domains =3D <&CPU_PD7>; + power-domain-names =3D "psci"; + #cooling-cells =3D <2>; + L2_700: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + + core4 { + cpu =3D <&CPU4>; + }; + + core5 { + cpu =3D <&CPU5>; + }; + + core6 { + cpu =3D <&CPU6>; + }; + + core7 { + cpu =3D <&CPU7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "little-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <355>; + exit-latency-us =3D <909>; + min-residency-us =3D <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "big-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <241>; + exit-latency-us =3D <1461>; + min-residency-us =3D <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + idle-state-name =3D "cluster-power-collapse"; + arm,psci-suspend-param =3D <0x4100c244>; + entry-latency-us =3D <3263>; + exit-latency-us =3D <6562>; + min-residency-us =3D <9987>; + }; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-peak-kBps =3D <800000 9600000>; + }; + + opp-422400000 { + opp-hz =3D /bits/ 64 <422400000>; + opp-peak-kBps =3D <800000 9600000>; + }; + + opp-537600000 { + opp-hz =3D /bits/ 64 <537600000>; + opp-peak-kBps =3D <800000 12902400>; + }; + + opp-652800000 { + opp-hz =3D /bits/ 64 <652800000>; + opp-peak-kBps =3D <800000 12902400>; + }; + + opp-768000000 { + opp-hz =3D /bits/ 64 <768000000>; + opp-peak-kBps =3D <800000 15974400>; + }; + + opp-883200000 { + opp-hz =3D /bits/ 64 <883200000>; + opp-peak-kBps =3D <1804000 19660800>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + opp-peak-kBps =3D <1804000 19660800>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <1804000 22732800>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-peak-kBps =3D <1804000 22732800>; + }; + + opp-1363200000 { + opp-hz =3D /bits/ 64 <1363200000>; + opp-peak-kBps =3D <2188000 25804800>; + }; + + opp-1478400000 { + opp-hz =3D /bits/ 64 <1478400000>; + opp-peak-kBps =3D <2188000 31948800>; + }; + + opp-1574400000 { + opp-hz =3D /bits/ 64 <1574400000>; + opp-peak-kBps =3D <3072000 31948800>; + }; + + opp-1670400000 { + opp-hz =3D /bits/ 64 <1670400000>; + opp-peak-kBps =3D <3072000 31948800>; + }; + + opp-1766400000 { + opp-hz =3D /bits/ 64 <1766400000>; + opp-peak-kBps =3D <3072000 31948800>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz =3D /bits/ 64 <825600000>; + opp-peak-kBps =3D <1804000 15974400>; + }; + + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + opp-peak-kBps =3D <2188000 19660800>; + }; + + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + opp-peak-kBps =3D <2188000 22732800>; + }; + + opp-1171200000 { + opp-hz =3D /bits/ 64 <1171200000>; + opp-peak-kBps =3D <3072000 25804800>; + }; + + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + opp-peak-kBps =3D <3072000 31948800>; + }; + + opp-1420800000 { + opp-hz =3D /bits/ 64 <1420800000>; + opp-peak-kBps =3D <4068000 31948800>; + }; + + opp-1536000000 { + opp-hz =3D /bits/ 64 <1536000000>; + opp-peak-kBps =3D <4068000 31948800>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <4068000 40550400>; + }; + + opp-1766400000 { + opp-hz =3D /bits/ 64 <1766400000>; + opp-peak-kBps =3D <4068000 40550400>; + }; + + opp-1881600000 { + opp-hz =3D /bits/ 64 <1881600000>; + opp-peak-kBps =3D <4068000 43008000>; + }; + + opp-1996800000 { + opp-hz =3D /bits/ 64 <1996800000>; + opp-peak-kBps =3D <6220000 43008000>; + }; + + opp-2131200000 { + opp-hz =3D /bits/ 64 <2131200000>; + opp-peak-kBps =3D <6220000 49152000>; + }; + + opp-2246400000 { + opp-hz =3D /bits/ 64 <2246400000>; + opp-peak-kBps =3D <7216000 49152000>; + }; + + opp-2361600000 { + opp-hz =3D /bits/ 64 <2361600000>; + opp-peak-kBps =3D <8368000 49152000>; + }; + + opp-2457600000 { + opp-hz =3D /bits/ 64 <2457600000>; + opp-peak-kBps =3D <8368000 51609600>; + }; + + opp-2553600000 { + opp-hz =3D /bits/ 64 <2553600000>; + opp-peak-kBps =3D <8368000 51609600>; + }; + + opp-2649600000 { + opp-hz =3D /bits/ 64 <2649600000>; + opp-peak-kBps =3D <8368000 51609600>; + }; + + opp-2745600000 { + opp-hz =3D /bits/ 64 <2745600000>; + opp-peak-kBps =3D <8368000 51609600>; + }; + + opp-2841600000 { + opp-hz =3D /bits/ 64 <2841600000>; + opp-peak-kBps =3D <8368000 51609600>; + }; + + opp-2918400000 { + opp-hz =3D /bits/ 64 <2918400000>; + opp-peak-kBps =3D <8368000 51609600>; + }; + + opp-2995200000 { + opp-hz =3D /bits/ 64 <2995200000>; + opp-peak-kBps =3D <8368000 51609600>; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-sc8180x", "qcom,scm"; + }; + }; + + camnoc_virt: interconnect-camnoc-virt { + compatible =3D "qcom,sc8180x-camnoc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible =3D "qcom,sc8180x-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + qup_virt: interconnect-qup-virt { + compatible =3D "qcom,sc8180x-qup-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&CLUSTER_PD>; + domain-idle-states =3D <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&CLUSTER_SLEEP_0>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hyp_mem: hyp-region@85700000 { + reg =3D <0x0 0x85700000 0x0 0x600000>; + no-map; + }; + + xbl_mem: xbl-region@85d00000 { + reg =3D <0x0 0x85d00000 0x0 0x140000>; + no-map; + }; + + aop_mem: aop-region@85f00000 { + reg =3D <0x0 0x85f00000 0x0 0x20000>; + no-map; + }; + + aop_cmd_db: cmd-db-region@85f20000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + + reserved-region@85f40000 { + reg =3D <0x0 0x85f40000 0x0 0x10000>; + no-map; + }; + + smem_mem: smem-region@86000000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86000000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + reserved-region@86200000 { + reg =3D <0x0 0x86200000 0x0 0x3900000>; + no-map; + }; + + reserved-region@89b00000 { + reg =3D <0x0 0x89b00000 0x0 0x1c00000>; + no-map; + }; + + reserved-region@9d400000 { + reg =3D <0x0 0x9d400000 0x0 0x1000000>; + no-map; + }; + + reserved-region@9e400000 { + reg =3D <0x0 0x9e400000 0x0 0x1400000>; + no-map; + }; + + reserved-region@9f800000 { + reg =3D <0x0 0x9f800000 0x0 0x800000>; + no-map; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <94>, <432>; + + interrupts =3D ; + + mboxes =3D <&apss_shared 6>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-lpass { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + + interrupts =3D ; + + mboxes =3D <&apss_shared 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-mpss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + mboxes =3D <&apss_shared 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + modem_smp2p_ipa_out: ipa-out { + qcom,entry-name =3D "ipa"; + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_ipa_in: ipa-in { + qcom,entry-name =3D "ipa"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + modem_smp2p_wlan_in: wlan { + qcom,entry-name =3D "wlan"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-slpi { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <481>, <430>; + + interrupts =3D ; + + mboxes =3D <&apss_shared 26>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <3>; + + slpi_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + slpi_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + compatible =3D "simple-bus"; + + gcc: clock-controller@100000 { + compatible =3D "qcom,gcc-sc8180x"; + reg =3D <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clock-names =3D "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + }; + + qupv3_id_0: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0 0x008c0000 0 0x6000>; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + iommus =3D <&apps_smmu 0x4c3 0>; + status =3D "disabled"; + + i2c0: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00880000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi0: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00880000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart0: serial@880000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00880000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c1: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00884000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00884000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart1: serial@884000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00884000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c2: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00888000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi2: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00888000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart2: serial@888000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00888000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c3: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0088c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0088c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart3: serial@88c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x0088c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c4: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00890000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi4: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00890000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart4: serial@890000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00890000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c5: i2c@894000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00894000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi5: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00894000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart5: serial@894000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00894000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c6: i2c@898000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00898000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi6: spi@898000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00898000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart6: serial@898000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00898000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c7: i2c@89c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0089c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi7: spi@89c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0089c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart7: serial@89c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x0089c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x6000>; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + iommus =3D <&apps_smmu 0x603 0>; + status =3D "disabled"; + + i2c8: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a80000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi8: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a80000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart8: serial@a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00a80000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c9: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a84000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi9: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a84000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart9: serial@a84000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0 0x00a84000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c10: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi10: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart10: serial@a88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00a88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a8c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi11: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a8c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart11: serial@a8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00a8c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c12: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a90000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi12: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a90000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart12: serial@a90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00a90000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c16: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a94000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi16: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a94000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart16: serial@a94000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00a94000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + }; + + qupv3_id_2: geniqup@cc0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00cc0000 0x0 0x6000>; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + iommus =3D <&apps_smmu 0x7a3 0>; + status =3D "disabled"; + + i2c17: i2c@c80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00c80000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi17: spi@c80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00c80000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart17: serial@c80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00c80000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c18: i2c@c84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00c84000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi18: spi@c84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00c84000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart18: serial@c84000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00c84000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c19: i2c@c88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00c88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi19: spi@c88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00c88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart19: serial@c88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00c88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c13: i2c@c8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00c8c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi13: spi@c8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00c8c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart13: serial@c8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00c8c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c14: i2c@c90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00c90000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi14: spi@c90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00c90000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart14: serial@c90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00c90000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + + i2c15: i2c@c94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00c94000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi15: spi@c94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00c94000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart15: serial@c94000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00c94000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts =3D ; + interconnects =3D <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; + }; + + config_noc: interconnect@1500000 { + compatible =3D "qcom,sc8180x-config-noc"; + reg =3D <0 0x01500000 0 0x7400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible =3D "qcom,sc8180x-system-noc"; + reg =3D <0 0x01620000 0 0x19400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,sc8180x-aggre1-noc"; + reg =3D <0 0x016e0000 0 0xd080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sc8180x-aggre2-noc"; + reg =3D <0 0x01700000 0 0x20000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + compute_noc: interconnect@1720000 { + compatible =3D "qcom,sc8180x-compute-noc"; + reg =3D <0 0x01720000 0 0x7000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible =3D "qcom,sc8180x-mmss-noc"; + reg =3D <0 0x01740000 0 0x1c100>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie0: pci@1c00000 { + compatible =3D "qcom,pcie-sc8180x", "snps,dw-pcie"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + iommus =3D <&apps_smmu 0x1d80 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + phys =3D <&pcie0_lane>; + phy-names =3D "pciephy"; + + status =3D "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,sc8180x-qmp-pcie-phy"; + reg =3D <0 0x1c06000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "ref", "refgen"; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie0_lane: lanes@1c06200 { + reg =3D <0 0x1c06200 0 0x170>, /* tx0 */ + <0 0x1c06400 0 0x200>, /* rx0 */ + <0 0x1c06a00 0 0x1f0>, /* pcs */ + <0 0x1c06600 0 0x170>, /* tx1 */ + <0 0x1c06800 0 0x200>, /* rx1 */ + <0 0x1c06e00 0 0xf4>; /* pcs_com */ + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_0_pipe_clk"; + }; + }; + + pcie3: pci@1c08000 { + compatible =3D "qcom,pcie-sc8180x", "snps,dw-pcie"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <3>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_3_PIPE_CLK>, + <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks =3D <&gcc GCC_PCIE_3_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + iommus =3D <&apps_smmu 0x1e00 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets =3D <&gcc GCC_PCIE_3_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_3_GDSC>; + + phys =3D <&pcie3_lane>; + phy-names =3D "pciephy"; + + status =3D "disabled"; + }; + + pcie3_phy: phy@1c0c000 { + compatible =3D "qcom,sc8180x-qmp-pcie-phy"; + reg =3D <0 0x1c0c000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_CLKREF_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "ref", "refgen"; + + resets =3D <&gcc GCC_PCIE_3_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie3_lane: lanes@1c0c200 { + reg =3D <0 0x1c0c200 0 0x170>, /* tx0 */ + <0 0x1c0c400 0 0x200>, /* rx0 */ + <0 0x1c0ca00 0 0x1f0>, /* pcs */ + <0 0x1c0c600 0 0x170>, /* tx1 */ + <0 0x1c0c800 0 0x200>, /* rx1 */ + <0 0x1c0ce00 0 0xf4>; /* pcs_com */ + clocks =3D <&gcc GCC_PCIE_3_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_3_pipe_clk"; + }; + }; + + pcie1: pci@1c10000 { + compatible =3D "qcom,pcie-sc8180x", "snps,dw-pcie"; + reg =3D <0 0x01c10000 0 0x3000>, + <0 0x68000000 0 0xf1d>, + <0 0x68000f20 0 0xa8>, + <0 0x68001000 0 0x1000>, + <0 0x68100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + iommus =3D <&apps_smmu 0x1c80 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_1_GDSC>; + + interconnects =3D <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0= >; + interconnect-names =3D "pcie-mem"; + + phys =3D <&pcie1_lane>; + phy-names =3D "pciephy"; + + status =3D "disabled"; + }; + + pcie1_phy: phy@1c16000 { + compatible =3D "qcom,sc8180x-qmp-pcie-phy"; + reg =3D <0 0x1c16000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "ref", "refgen"; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie1_lane: lanes@1c0e200 { + reg =3D <0 0x1c16200 0 0x170>, /* tx0 */ + <0 0x1c16400 0 0x200>, /* rx0 */ + <0 0x1c16a00 0 0x1f0>, /* pcs */ + <0 0x1c16600 0 0x170>, /* tx1 */ + <0 0x1c16800 0 0x200>, /* rx1 */ + <0 0x1c16e00 0 0xf4>; /* pcs_com */ + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_1_pipe_clk"; + }; + }; + + pcie2: pci@1c18000 { + compatible =3D "qcom,pcie-sc8180x", "snps,dw-pcie"; + reg =3D <0 0x01c18000 0 0x3000>, + <0 0x70000000 0 0xf1d>, + <0 0x70000f20 0 0xa8>, + <0 0x70001000 0 0x1000>, + <0 0x70100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + device_type =3D "pci"; + linux,pci-domain =3D <2>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <4>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks =3D <&gcc GCC_PCIE_2_PIPE_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + assigned-clocks =3D <&gcc GCC_PCIE_2_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + iommus =3D <&apps_smmu 0x1d00 0x7f>; + iommu-map =3D <0x0 &apps_smmu 0x1d00 0x1>, + <0x100 &apps_smmu 0x1d01 0x1>; + + resets =3D <&gcc GCC_PCIE_2_BCR>; + reset-names =3D "pci"; + + power-domains =3D <&gcc PCIE_2_GDSC>; + + phys =3D <&pcie2_lane>; + phy-names =3D "pciephy"; + + status =3D "disabled"; + }; + + pcie2_phy: phy@1c1c000 { + compatible =3D "qcom,sc8180x-qmp-pcie-phy"; + reg =3D <0 0x1c1c000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_CLKREF_CLK>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names =3D "aux", "cfg_ahb", "ref", "refgen"; + + resets =3D <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + + pcie2_lane: lanes@1c0e200 { + reg =3D <0 0x1c1c200 0 0x170>, /* tx0 */ + <0 0x1c1c400 0 0x200>, /* rx0 */ + <0 0x1c1ca00 0 0x1f0>, /* pcs */ + <0 0x1c1c600 0 0x170>, /* tx1 */ + <0 0x1c1c800 0 0x200>, /* rx1 */ + <0 0x1c1ce00 0 0xf4>; /* pcs_com */ + clocks =3D <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names =3D "pipe0"; + + #phy-cells =3D <0>; + clock-output-names =3D "pcie_2_pipe_clk"; + }; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible =3D "qcom,sc8180x-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0 0x01d84000 0 0x2500>; + interrupts =3D ; + phys =3D <&ufs_mem_phy_lanes>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + iommus =3D <&apps_smmu 0x300 0>; + + clock-names =3D + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks =3D + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz =3D + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,sc8180x-qmp-ufs-phy"; + reg =3D <0 0x01d87000 0 0x1c0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clock-names =3D "ref", + "ref_aux"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + status =3D "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg =3D <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells =3D <0>; + }; + }; + + ipa_virt: interconnect@1e00000 { + compatible =3D "qcom,sc8180x-ipa-virt"; + reg =3D <0 0x01e00000 0 0x1000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells =3D <1>; + }; + + gpu: gpu@2c00000 { + compatible =3D "qcom,adreno-680.1", "qcom,adreno"; + #stream-id-cells =3D <16>; + + reg =3D <0 0x02c00000 0 0x40000>; + reg-names =3D "kgsl_3d0_reg_memory"; + + interrupts =3D ; + + iommus =3D <&adreno_smmu 0 0xc01>; + + operating-points-v2 =3D <&gpu_opp_table>; + + interconnects =3D <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0= 0>; + interconnect-names =3D "gfx-mem"; + + qcom,gmu =3D <&gmu>; + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + opp-level =3D ; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-level =3D ; + }; + + opp-461000000 { + opp-hz =3D /bits/ 64 <461000000>; + opp-level =3D ; + }; + + opp-405000000 { + opp-hz =3D /bits/ 64 <405000000>; + opp-level =3D ; + }; + + opp-315000000 { + opp-hz =3D /bits/ 64 <315000000>; + opp-level =3D ; + }; + + opp-256000000 { + opp-hz =3D /bits/ 64 <256000000>; + opp-level =3D ; + }; + + opp-177000000 { + opp-hz =3D /bits/ 64 <177000000>; + opp-level =3D ; + }; + }; + }; + + gmu: gmu@2c6a000 { + compatible=3D"qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; + + reg =3D <0 0x02c6a000 0 0x30000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names =3D "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names =3D "ahb", "gmu", "cxo", "axi", "memnoc"; + + power-domains =3D <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names =3D "cx", "gx"; + + iommus =3D <&adreno_smmu 5 0xc00>; + + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-level =3D ; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + opp-level =3D ; + }; + }; + }; + + gpucc: clock-controller@2c90000 { + compatible =3D "qcom,sc8180x-gpucc"; + reg =3D <0 0x02c90000 0 0x9000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names =3D "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@2ca0000 { + compatible =3D "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", "arm,mmu-50= 0"; + reg =3D <0 0x02ca0000 0 0x10000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names =3D "ahb", "bus", "iface"; + + power-domains =3D <&gpucc GPU_CX_GDSC>; + }; + + tlmm: pinctrl@3100000 { + compatible =3D "qcom,sc8180x-tlmm"; + reg =3D <0 0x03100000 0 0x300000>, + <0 0x03500000 0 0x700000>, + <0 0x03d00000 0 0x300000>; + reg-names =3D "west", "east", "south"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 191>; + wakeup-parent =3D <&pdc>; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible =3D "qcom,sc8180x-mpss-pas"; + reg =3D <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended =3D <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8180X_CX>, + <&rpmhpd SC8180X_MSS>; + power-domain-names =3D "cx", "mss"; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&modem_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + glink-edge { + interrupts =3D ; + label =3D "modem"; + qcom,remote-pid =3D <1>; + mboxes =3D <&apss_shared 12>; + }; + }; + + remoteproc_cdsp: remoteproc@8300000 { + compatible =3D "qcom,sc8180x-cdsp-pas"; + reg =3D <0x0 0x08300000 0x0 0x4040>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8180X_CX>; + power-domain-names =3D "cx"; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&cdsp_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts =3D ; + label =3D "cdsp"; + qcom,remote-pid =3D <5>; + mboxes =3D <&apss_shared 4>; + }; + }; + + usb_prim_hsphy: phy@88e2000 { + compatible =3D "qcom,sc8180x-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg =3D <0 0x088e2000 0 0x400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_sec_hsphy: phy@88e3000 { + compatible =3D "qcom,sc8180x-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg =3D <0 0x088e3000 0 0x400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + resets =3D <&gcc GCC_QUSB2PHY_SEC_BCR>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_prim_qmpphy: phy@88e9000 { + compatible =3D "qcom,sc8180x-qmp-usb3-dp-phy"; + reg =3D <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x38>, + <0 0x088ea000 0 0x40>; + reg-names =3D "reg-base", "dp_com"; + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + resets =3D <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; + reset-names =3D "phy", "common"; + + #clock-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_prim_ssphy: usb3-phy@88e9200 { + reg =3D <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb3_prim_phy_pipe_clk_src"; + }; + + usb_prim_dpphy: dp-phy@88ea200 { + reg =3D <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eaa00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + }; + + usb_sec_qmpphy: phy@88ee000 { + compatible =3D "qcom,sc8180x-qmp-usb3-dp-phy"; + reg =3D <0 0x088ee000 0 0x18c>, + <0 0x088ed000 0 0x10>, + <0 0x088ef000 0 0x40>; + reg-names =3D "reg-base", "dp_com"; + clocks =3D <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names =3D "aux", "ref_clk_src", "ref", "com_aux"; + resets =3D <&gcc GCC_USB3_DP_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names =3D "phy", "common"; + + #clock-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_sec_ssphy: usb3-phy@88e9200 { + reg =3D <0 0x088ee200 0 0x200>, + <0 0x088ee400 0 0x200>, + <0 0x088eec00 0 0x218>, + <0 0x088ee600 0 0x200>, + <0 0x088ee800 0 0x200>, + <0 0x088eea00 0 0x100>; + #phy-cells =3D <0>; + clocks =3D <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names =3D "pipe0"; + clock-output-names =3D "usb3_sec_phy_pipe_clk_src"; + }; + + usb_sec_dpphy: dp-phy@88ef200 { + reg =3D <0 0x088ef200 0 0x200>, + <0 0x088ef400 0 0x200>, + <0 0x088efa00 0 0x200>, + <0 0x088ef600 0 0x200>, + <0 0x088ef800 0 0x200>; + #clock-cells =3D <1>; + #phy-cells =3D <0>; + clock-output-names =3D "qmp_dptx1_phy_pll_link_clk", "qmp_dptx1_phy_pl= l_vco_div_clk"; + }; + }; + + system-cache-controller@9200000 { + compatible =3D "qcom,sc8180x-llcc"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; + reg-names =3D "llcc_base", "llcc_broadcast_base"; + interrupts =3D ; + }; + + gem_noc: interconnect@9680000 { + compatible =3D "qcom,sc8180x-gem-noc"; + reg =3D <0 0x09680000 0 0x58200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + usb_prim: usb@a6f8800 { + compatible =3D "qcom,sc8180x-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a6f8800 0 0x400>; + interrupts =3D , + , + , + ; + interrupt-names =3D "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names =3D "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + power-domains =3D <&gcc USB30_PRIM_GDSC>; + + interconnects =3D <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-ranges; + + status =3D "disabled"; + + usb_prim_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a600000 0 0xcd00>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x140 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys =3D <&usb_prim_hsphy>, <&usb_prim_ssphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + }; + + usb_sec: usb@a8f8800 { + compatible =3D "qcom,sc8180x-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a8f8800 0 0x400>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names =3D "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + resets =3D <&gcc GCC_USB30_SEC_BCR>; + power-domains =3D <&gcc USB30_SEC_GDSC>; + interrupts =3D , + , + , + ; + interrupt-names =3D "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + assigned-clocks =3D <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interconnects =3D <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0= >, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-ranges; + + status =3D "disabled"; + + usb_sec_dwc3: usb@a800000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a800000 0 0xcd00>; + interrupts =3D ; + iommus =3D <&apps_smmu 0x160 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys =3D <&usb_sec_hsphy>, <&usb_sec_ssphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + }; + + mdss: mdss@ae00000 { + compatible =3D "qcom,sc8180x-mdss"; + reg =3D <0 0x0ae00000 0 0x1000>; + reg-names =3D "mdss"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "nrt_bus", "core"; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + interconnects =3D <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 = 0>, + <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + iommus =3D <&apps_smmu 0x800 0x420>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: mdp@ae01000 { + compatible =3D "qcom,sc8180x-dpu"; + reg =3D <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", "bus", "core", "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <460000000>, + <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SC8180X_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf0_out: endpoint { + remote-endpoint =3D <&dp0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@2 { + reg =3D <2>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + + port@4 { + reg =3D <4>; + dpu_intf4_out: endpoint { + remote-endpoint =3D <&dp1_in>; + }; + }; + + port@5 { + reg =3D <5>; + dpu_intf5_out: endpoint { + remote-endpoint =3D <&edp_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz =3D /bits/ 64 <345000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz =3D /bits/ 64 <460000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae94000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SC8180X_MMCX>; + + phys =3D <&dsi0_phy>; + phy-names =3D "dsi"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible =3D "qcom,dsi-phy-7nm"; + reg =3D <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae96000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SC8180X_MMCX>; + + phys =3D <&dsi1_phy>; + phy-names =3D "dsi"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible =3D "qcom,dsi-phy-7nm"; + reg =3D <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + mdss_dp0: displayport-controller@ae90000 { + compatible =3D "qcom,sc8180x-dp"; + reg =3D <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae90a00 0 0x400>; + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names =3D "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents =3D <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; + + phys =3D <&usb_prim_dpphy>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + operating-points-v2 =3D <&dp0_opp_table>; + power-domains =3D <&rpmhpd SC8180X_CX>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + }; + }; + + dp0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@ae98000 { + compatible =3D "qcom,sc8180x-dp"; + reg =3D <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae98a00 0 0x400>; + interrupt-parent =3D <&mdss>; + interrupts =3D <13>; + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; + clock-names =3D "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; + assigned-clock-parents =3D <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; + + phys =3D <&usb_sec_dpphy>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + operating-points-v2 =3D <&dp0_opp_table>; + power-domains =3D <&rpmhpd SC8180X_CX>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dp1_in: endpoint { + remote-endpoint =3D <&dpu_intf4_out>; + }; + }; + + port@1 { + reg =3D <1>; + }; + }; + + dp1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_edp: displayport-controller@ae9a000 { + compatible =3D "qcom,sc8180x-edp"; + reg =3D <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9aa00 0 0x400>; + interrupt-parent =3D <&mdss>; + interrupts =3D <14>; + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names =3D "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents =3D <&edp_phy 0>, <&edp_phy 1>; + + phys =3D <&edp_phy>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + operating-points-v2 =3D <&edp_opp_table>; + power-domains =3D <&rpmhpd SC8180X_CX>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + edp_in: endpoint { + remote-endpoint =3D <&dpu_intf5_out>; + }; + }; + }; + + edp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + edp_phy: phy@aec2a00 { + compatible =3D "qcom,sc8180x-edp-phy"; + reg =3D <0 0x0aec2a00 0 0x1c0>, + <0 0x0aec2200 0 0xa0>, + <0 0x0aec2600 0 0xa0>, + <0 0x0aec2000 0 0x19c>; + + clocks =3D <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names =3D "aux", "cfg_ahb"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sc8180x-dispcc"; + reg =3D <0 0x0af00000 0 0x20000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&usb_prim_dpphy 0>, + <&usb_prim_dpphy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + clock-names =3D "bi_tcxo", + "sleep_clk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk"; + power-domains =3D <&rpmhpd SC8180X_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + + status =3D "disabled"; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sc8180x-pdc", "qcom,pdc"; + reg =3D <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges =3D <0 480 94>, <94 609 31>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible =3D "qcom,sc8180x-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors =3D <16>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible =3D "qcom,sc8180x-tsens", "qcom,tsens-v2"; + reg =3D <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors =3D <9>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-controller@c300000 { + compatible =3D "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x100000>; + interrupts =3D ; + mboxes =3D <&apss_shared 0>; + + #clock-cells =3D <0>; + #power-domain-cells =3D <1>; + }; + + spmi_bus: spmi@c440000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x0c440000 0x0 0x0001100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x0100000>, + <0x0 0x0e700000 0x0 0x00a0000>, + <0x0 0x0c40a000 0x0 0x0026000>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts =3D ; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + cell-index =3D <0>; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sc8180x-smmu-500", "arm,mmu-500"; + reg =3D <0 0x15000000 0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + }; + + remoteproc_adsp: remoteproc@17300000 { + compatible =3D "qcom,sc8180x-adsp-pas"; + reg =3D <0x0 0x17300000 0x0 0x4040>; + + interrupts-extended =3D <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd SC8180X_CX>; + power-domain-names =3D "cx"; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&adsp_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts =3D ; + label =3D "lpass"; + qcom,remote-pid =3D <2>; + mboxes =3D <&apss_shared 8>; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts =3D ; + }; + + apss_shared: mailbox@17c00000 { + compatible =3D "qcom,sc8180x-apss-shared"; + reg =3D <0x0 0x17c00000 0x0 0x1000>; + #mbox-cells =3D <1>; + }; + + timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0x20000000>; + + frame@17c21000{ + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@17c23000 { + reg =3D <0x17c23000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c25000 { + reg =3D <0x17c25000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c27000 { + reg =3D <0x17c26000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c29000 { + reg =3D <0x17c29000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c2b000 { + reg =3D <0x17c2b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@17c2d000 { + reg =3D <0x17c2d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + label =3D "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sc8180x-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sc8180x-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level =3D ; + }; + }; + }; + }; + + osm_l3: interconnect@18321000 { + compatible =3D "qcom,sc8180x-osm-l3"; + reg =3D <0 0x18321000 0 0x1400>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #interconnect-cells =3D <1>; + }; + + lmh@18350800 { + compatible =3D "qcom,sc8180x-lmh"; + reg =3D <0 0x18350800 0 0x400>; + interrupts =3D ; + cpus =3D <&CPU4>; + qcom,lmh-temp-arm-millicelsius =3D <65000>; + qcom,lmh-temp-low-millicelsius =3D <94500>; + qcom,lmh-temp-high-millicelsius =3D <95000>; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + lmh@18358800 { + compatible =3D "qcom,sc8180x-lmh"; + reg =3D <0 0x18358800 0 0x400>; + interrupts =3D ; + cpus =3D <&CPU0>; + qcom,lmh-temp-arm-millicelsius =3D <65000>; + qcom,lmh-temp-low-millicelsius =3D <94500>; + qcom,lmh-temp-high-millicelsius =3D <95000>; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible =3D "qcom,cpufreq-hw"; + reg =3D <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names =3D "freq-domain0", "freq-domain1"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + }; + + wifi: wifi@18800000 { + compatible =3D "qcom,wcn3990-wifi"; + reg =3D <0 0x18800000 0 0x800000>; + reg-names =3D "membase"; + clock-names =3D "cxo_ref_clk_pin"; + clocks =3D <&rpmhcc RPMH_RF_CLK2>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + iommus =3D <&apps_smmu 0x0640 0x1>; + qcom,msa-fixed-perm; + status =3D "disabled"; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 1>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 2>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 3>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 4>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 7>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 8>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 9>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 10>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 11>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 12>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 13>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 14>; + + trips { + cpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 0>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 5>; + + trips { + cluster-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 6>; + + trips { + cluster-crit { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal-top { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens0 15>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 0>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 1>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + video-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 2>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + mem-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 3>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 4>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 5>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + compute-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 6>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + mdm-dsp-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 7>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + npu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 8>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + gpu-thermal-bottom { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens1 11>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.37.3 From nobody Fri Apr 3 03:54:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3F9DC6FA92 for ; Fri, 16 Sep 2022 12:13:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231465AbiIPMNG (ORCPT ); Fri, 16 Sep 2022 08:13:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231450AbiIPMMm (ORCPT ); Fri, 16 Sep 2022 08:12:42 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0DE0B0B0A; Fri, 16 Sep 2022 05:12:36 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 345B2B825ED; Fri, 16 Sep 2022 12:12:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8B160C4347C; Fri, 16 Sep 2022 12:12:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663330354; bh=LjtcPgXxF0+VZrtcJilydBrS6HItzd3uRTnnuRzWDgY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HIsbqmkvBaYfAl6VZnoh8h8b6TtwHIjn6MWI7l10ZMbS386DSD/wiwnCUTAMuAn16 cdM+EEEw2DmqTQcdOm6IUev/HOKAm/ltKQqsu3Vc0i3VuGR1XtP7/IZHmZ24S2hyJM 96MpJU0pKwwmxvETW8YFI4bOUKq3J6BTx1gv6v60juHiEA6Ui8HM8pH6S9Yy5eaEr6 CoJ4hnuJbPKNoRvXGafjaZ/7bBu4S4F4vQSwlDODmFMqeeH1uvoLlOffLL84h1ksKe 44CnjFxmsXWXaQ7chTrj4sxSCoMusqWhzsv1ix/X8sbiNDLKAj2CVSg+NBZni6UHnn 3vg6FhKeXWxgQ== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH 5/6] arm64: dts: qcom: sc8180x: Introduce Primus Date: Fri, 16 Sep 2022 17:42:03 +0530 Message-Id: <20220916121204.3880182-6-vkoul@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220916121204.3880182-1-vkoul@kernel.org> References: <20220916121204.3880182-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Andersson Introduce support for the SC8180X reference device, aka Primus, with debug UART, regulators, UFS and USB support. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 326 +++++++++ arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 706 ++++++++++++++++++++ 3 files changed, 1033 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-primus.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index d7669a7cee9f..f1c620bb078e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -112,6 +112,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine-villager-= r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc8180x-primus.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-lenovo-thinkpad-x13s.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sda660-inforce-ifc6560.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/= dts/qcom/sc8180x-pmics.dtsi new file mode 100644 index 000000000000..49c146b6f37f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022, Linaro Limited + */ + +#include +#include +#include +#include + +/ { + thermal-zones { + pmc8180-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pmc8180_temp>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + + trip2 { + temperature =3D <145000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmc8180c-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + + thermal-sensors =3D <&pmc8180c_temp>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + + trip2 { + temperature =3D <145000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmc8180_0: pmic@0 { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pon: power-on@800 { + compatible =3D "qcom,pm8916-pon"; + reg =3D <0x0800>; + pwrkey { + compatible =3D "qcom,pm8941-pwrkey"; + interrupts =3D <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; + debounce =3D <15625>; + bias-pull-up; + linux,code =3D ; + + status =3D "disabled"; + }; + }; + + pmc8180_temp: temp-alarm@2400 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0x2400>; + interrupts =3D <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels =3D <&pmc8180_adc ADC5_DIE_TEMP>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmc8180_adc: adc@3100 { + compatible =3D "qcom,spmi-adc5"; + reg =3D <0x3100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + interrupts =3D <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_gnd"; + }; + + vref-1p25@1 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "vref_1p25"; + }; + + die-temp@6 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "die_temp"; + }; + }; + + pmc8180_adc_tm: adc-tm@3500 { + compatible =3D "qcom,spmi-adc-tm5"; + reg =3D <0x3500>; + interrupts =3D <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + rtc@6000 { + compatible =3D "qcom,pm8941-rtc"; + reg =3D <0x6000>; + reg-names =3D "rtc", "alarm"; + interrupts =3D <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pmc8180_gpios: gpio@c000 { + compatible =3D "qcom,pmc8180-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmic@1 { + compatible =3D "qcom,pmc8180", "qcom,spmi-pmic"; + reg =3D <0x1 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + pmic@2 { + compatible =3D "qcom,smb2351", "qcom,spmi-pmic"; + reg =3D <0x2 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@3100 { + compatible =3D "qcom,spmi-adc-rev2"; + reg =3D <0x3100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + interrupts =3D <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_gnd"; + }; + + vref-1p25@1 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "vref_1p25"; + }; + + vcoin@85 { + reg =3D <0x85>; + qcom,pre-scaling =3D <1 1>; + label =3D "vcoin2"; + }; + }; + }; + + pmic@6 { + compatible =3D "qcom,pm8150c", "qcom,spmi-pmic"; + reg =3D <0x6 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + pmic@8 { + compatible =3D "qcom,pm8150", "qcom,spmi-pmic"; + reg =3D <0x8 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + pmic@a { + compatible =3D "qcom,smb2351", "qcom,spmi-pmic"; + reg =3D <0xa SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@3100 { + compatible =3D "qcom,spmi-adc-rev2"; + reg =3D <0x3100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + interrupts =3D <0xa 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_gnd"; + }; + + vref-1p25@1 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "vref_1p25"; + }; + + vcoin@85 { + reg =3D <0x85>; + qcom,pre-scaling =3D <1 1>; + label =3D "vcoin"; + }; + }; + }; + + pmic@4 { + compatible =3D "qcom,pm8150c", "qcom,spmi-pmic"; + reg =3D <0x4 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-on@800 { + compatible =3D "qcom,pm8916-pon"; + reg =3D <0x0800>; + + status =3D "disabled"; + }; + + pmc8180c_temp: temp-alarm@2400 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0x2400>; + interrupts =3D <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels =3D <&pmc8180c_adc ADC5_DIE_TEMP>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pmc8180c_adc: adc@3100 { + compatible =3D "qcom,spmi-adc5"; + reg =3D <0x3100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + interrupts =3D <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "ref_gnd"; + }; + + vref-1p25@1 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "vref_1p25"; + }; + + die-temp@6 { + reg =3D ; + qcom,pre-scaling =3D <1 1>; + label =3D "die_temp"; + }; + }; + + pmc8180c_adc_tm: adc-tm@3500 { + compatible =3D "qcom,spmi-adc-tm5"; + reg =3D <0x3500>; + interrupts =3D <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + pmc8180c_gpios: gpio@c000 { + compatible =3D "qcom,pmc8180c-gpio"; + reg =3D <0xc000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + pmic@5 { + compatible =3D "qcom,pmc8180c", "qcom,spmi-pmic"; + reg =3D <0x5 SPMI_USID>; + + pmc8180c_lpg: lpg { + compatible =3D "qcom,pmc8180c-lpg"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + #pwm-cells =3D <2>; + + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/= dts/qcom/sc8180x-primus.dts new file mode 100644 index 000000000000..14582dbe7155 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -0,0 +1,706 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sc8180x.dtsi" +#include "sc8180x-pmics.dtsi" + +/ { + model =3D "Qualcomm SC8180x Primus"; + compatible =3D "qcom,sc8180x-primus", "qcom,sc8180x"; + + aliases { + serial0 =3D &uart12; + serial1 =3D &uart13; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pmc8180c_lpg 4 1000000>; + enable-gpios =3D <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bl_pwm_default_state>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hall_int_active_state>; + + lid-switch { + gpios =3D <&tlmm 121 GPIO_ACTIVE_HIGH>; + linux,input-type =3D ; + linux,code =3D ; + wakeup-source; + wakeup-event-action =3D ; + }; + }; + + reserved-memory { + rmtfs_mem: rmtfs-region@85500000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x85500000 0x0 0x200000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D <15>; + }; + + wlan_mem: wlan-region@8bc00000 { + reg =3D <0x0 0x8bc00000 0x0 0x180000>; + no-map; + }; + + adsp_mem: adsp-region@96e00000 { + reg =3D <0x0 0x96e00000 0x0 0x1c00000>; + no-map; + }; + + mpss_mem: mpss-region@8d800000 { + reg =3D <0x0 0x8d800000 0x0 0x9600000>; + no-map; + }; + + gpu_mem: gpu-region@98a00000 { + reg =3D <0x0 0x98a00000 0x0 0x2000>; + no-map; + }; + + reserved-region@9a500000 { + reg =3D <0x0 0x9a500000 0x0 0x600000>; + no-map; + }; + }; + + vreg_nvme_0p9: nvme-0p9-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_nvme_0p9"; + + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-always-on; + }; + + vreg_nvme_3p3: nvme-3p3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_nvme_3p3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pmc8180c_gpios 11 0>; + enable-active-high; + + regulator-always-on; + }; + + vdd_kb_tp_3v3: vdd-kb-tp-3v3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_kb_tp_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-always-on; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&kb_tp_3v3_en_active_state>; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_s4a_1p8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vph_pwr>; + }; +}; + +&apps_rsc { + pmc8180-a-rpmh-regulators { + compatible =3D "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s5-supply =3D <&vph_pwr>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5a_2p0>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt =3D <2040000>; + regulator-max-microvolt =3D <2100000>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l9a_1p3: ldo9 { + regulator-min-microvolt =3D <1296000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + }; + + pmc8180c-rpmh-regulators { + compatible =3D "qcom,pmc8180c-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-s6-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-l2-l3-supply =3D <&vreg_s6c_1p35>; + vdd-bob-supply =3D <&vph_pwr>; + + vreg_s6c_1p35: smps6 { + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1372000>; + regulator-initial-mode =3D ; + }; + + vreg_s8c_1p8: smps8 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-always-on; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l4c_3p3: ldo4 { + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_bob: bob { + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3350000>; + regulator-initial-mode =3D ; + }; + }; + + pmc8180-e-rpmh-regulators { + compatible =3D "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-l2-l10-supply =3D <&vreg_bob>; + vdd-l3-l4-l5-l18-supply =3D <&vreg_s4e_0p98>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5e_2p05>; + vdd-l13-l16-l17-supply =3D <&vreg_bob>; + + vreg_s4e_0p98: smps4 { + regulator-min-microvolt =3D <992000>; + regulator-max-microvolt =3D <992000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_2p05: smps5 { + regulator-min-microvolt =3D <2040000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + + vreg_l1e_0p75: ldo1 { + regulator-min-microvolt =3D <752000>; + regulator-max-microvolt =3D <752000>; + regulator-initial-mode =3D ; + }; + + vreg_l5e_0p88: ldo5 { + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l7e_1p8: ldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l10e_2p9: ldo10 { + regulator-min-microvolt =3D <2904000>; + regulator-max-microvolt =3D <2904000>; + regulator-initial-mode =3D ; + }; + + vreg_l12e: ldo12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l16e_3p0: ldo16 { + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&dispcc { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; + + zap-shader { + memory-region =3D <&gpu_mem>; + firmware-name =3D "qcom/sc8180x/qcdxkmsuc8180.mbn"; + }; +}; + +&i2c1 { + clock-frequency =3D <100000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_i2c_active_state>; + + status =3D "okay"; + + touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + hid-descr-addr =3D <0x1>; + + vdd-supply =3D <&vreg_l4c_3p3>; + vddl-supply =3D <&vreg_l12e>; + + post-power-on-delay-ms =3D <20>; + + interrupts-extended =3D <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts_active_state>; + }; +}; + +&i2c7 { + clock-frequency =3D <100000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&aux_i2c_active_state>; + + status =3D "okay"; + + touchpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + hid-descr-addr =3D <0x1>; + + interrupts-extended =3D <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tp_int_active_state>; + + vdd-supply =3D <&vdd_kb_tp_3v3>; + }; + + keyboard@3a { + compatible =3D "hid-over-i2c"; + reg =3D <0x3a>; + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&kb_int_active_state>; + + vdd-supply =3D <&vdd_kb_tp_3v3>; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_edp { + data-lanes =3D <0 1 2 3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_hpd_active>; + + status =3D "okay"; + + aux-bus { + panel { + compatible =3D "edp-panel"; + + backlight =3D <&backlight>; + + ports { + port { + auo_b133han05_in: endpoint { + remote-endpoint =3D <&mdss_edp_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg =3D <1>; + mdss_edp_out: endpoint { + remote-endpoint =3D <&auo_b133han05_in>; + }; + }; + }; +}; + +&pcie1 { + perst-gpio =3D <&tlmm 175 GPIO_ACTIVE_LOW>; + wake-gpio =3D <&tlmm 177 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_default_state>; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l5e_0p88>; + vdda-pll-supply =3D <&vreg_l3c_1p2>; + + status =3D "okay"; +}; + +&pmc8180c_lpg { + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&qupv3_id_2 { + status =3D "okay"; +}; + +&remoteproc_adsp { + memory-region =3D <&adsp_mem>; + firmware-name =3D "qcom/sc8180x/qcadsp8180.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + memory-region =3D <&mpss_mem>; + firmware-name =3D "qcom/sc8180x/qcmpss8180.mbn"; + + status =3D "okay"; +}; + +&uart12 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + +&uart13 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart13_state>; + + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn3998-bt"; + + vddio-supply =3D <&vreg_s4a_1p8>; + vddxo-supply =3D <&vreg_l7a_1p8>; + vddrf-supply =3D <&vreg_l9a_1p3>; + vddch0-supply =3D <&vreg_l11c_3p3>; + max-speed =3D <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 190 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l10e_2p9>; + vcc-max-microamp =3D <155000>; + + vccq2-supply =3D <&vreg_l7e_1p8>; + vccq2-max-microamp =3D <425000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l5e_0p88>; + vdda-pll-supply =3D <&vreg_l3c_1p2>; + + status =3D "okay"; +}; + +&usb_prim_hsphy { + vdda-pll-supply =3D <&vreg_l5e_0p88>; + vdda18-supply =3D <&vreg_l12a_1p8>; + vdda33-supply =3D <&vreg_l16e_3p0>; + + status =3D "okay"; +}; + +&usb_prim_qmpphy { + vdda-phy-supply =3D <&vreg_l3c_1p2>; + vdda-pll-supply =3D <&vreg_l5e_0p88>; + + status =3D "okay"; +}; + +&usb_prim { + status =3D "okay"; +}; + +&usb_prim_dwc3 { + dr_mode =3D "host"; +}; + +&usb_sec_hsphy { + vdda-pll-supply =3D <&vreg_l5e_0p88>; + vdda18-supply =3D <&vreg_l12a_1p8>; + vdda33-supply =3D <&vreg_l16e_3p0>; + + status =3D "okay"; +}; + +&usb_sec_qmpphy { + vdda-phy-supply =3D <&vreg_l3c_1p2>; + vdda-pll-supply =3D <&vreg_l5e_0p88>; + + status =3D "okay"; +}; + +&usb_sec { + status =3D "okay"; +}; + +&usb_sec_dwc3 { + dr_mode =3D "host"; +}; + +&wifi { + memory-region =3D <&wlan_mem>; + + vdd-0.8-cx-mx-supply =3D <&vreg_l1e_0p75>; + vdd-1.8-xo-supply =3D <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply =3D <&vreg_l9a_1p3>; + vdd-3.3-ch0-supply =3D <&vreg_l11c_3p3>; + vdd-3.3-ch1-supply =3D <&vreg_l10c_3p3>; + + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; + +/* PINCTRL */ + +&pmc8180c_gpios { + bl_pwm_default_state: bl-pwm-default-state { + en { + pins =3D "gpio8"; + function =3D "normal"; + }; + + pwm { + pins =3D "gpio10"; + function =3D "func1"; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <0 4>, <47 4>, <126 4>; + + aux_i2c_active_state: aux-i2c-active-state { + pins =3D "gpio98", "gpio99"; + function =3D "qup7"; + + bias-disable; + drive-strength =3D <16>; + }; + + edp_hpd_active: epd-hpd-active-state { + pins =3D "gpio10"; + function =3D "edp_hot"; + }; + + hall_int_active_state: hall-int-active-state { + pins =3D "gpio121"; + function =3D "gpio"; + + input-enable; + bias-disable; + }; + + kb_int_active_state: kb-int-active-state { + int-n { + pins =3D "gpio37"; + function =3D "gpio"; + + bias-pull-up; + intput-enable; + }; + + kp-disable { + pins =3D "gpio135"; + function =3D "gpio"; + + output-high; + }; + }; + + kb_tp_3v3_en_active_state: kb-tp-3v3-en-active-state { + pins =3D "gpio4"; + function =3D "gpio"; + + bias-disable; + }; + + pcie2_default_state: pcie2-default-state { + clkreq { + pins =3D "gpio176"; + function =3D "pci_e2"; + bias-pull-up; + }; + + reset-n { + pins =3D "gpio175"; + function =3D "gpio"; + + drive-strength =3D <2>; + output-low; + bias-pull-down; + }; + + wake-n { + pins =3D "gpio177"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + tp_int_active_state: tp-int-active-state { + tp-int { + pins =3D "gpio24"; + function =3D "gpio"; + + bias-disable; + input-enable; + }; + + tp-close-n { + pins =3D "gpio116"; + function =3D "gpio"; + + bias-disable; + input-enable; + }; + }; + + ts_active_state: ts-active-state { + int-n { + pins =3D "gpio122"; + function =3D "gpio"; + + input-enable; + bias-disable; + }; + + reset-n { + pins =3D "gpio54"; + function =3D "gpio"; + + output-high; + }; + }; + + ts_i2c_active_state: ts-i2c-active-state { + pins =3D "gpio114", "gpio115"; + function =3D "qup1"; + + /* External pull up */ + bias-disable; + drive-strength =3D <2>; + }; + + uart13_state: uart13-state { + cts { + pins =3D "gpio43"; + function =3D "qup13"; + bias-pull-down; + }; + + rts-tx { + pins =3D "gpio44", "gpio45"; + function =3D "qup13"; + drive-strength =3D <2>; + bias-disable; + }; + + rx { + pins =3D "gpio46"; + function =3D "qup13"; + bias-pull-up; + }; + }; +}; --=20 2.37.3 From nobody Fri Apr 3 03:54:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47BCAECAAD8 for ; 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d=kernel.org; s=k20201202; t=1663330357; bh=fNsOeXh6ggzCOEx3wp9+SlB1U++Dh2ajfXiPtKvHX1s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jMkeyrmfYkRxgiHD8j897UW0xAC43ps5p8nE1K03aumN8Fe/DIh5E1Z5QsoNvLisW 1tpOmVVYeqb85JcRwADlkaXjviQqzHEP/5sWa43yfcEkybaVkRVRg5U1ktlGVE6EfF R3i22ip96RG49MYMGC5fbVddfHEUznTYWQ0eBpCcXtckFjr30nsaCxPbsNCMA3aXi4 G0jsA0hGGPqo4TRShwBfoIofwks4pBMmYn3xv6tzquf59BT+Nqe9DNuCWoygQp0CRy szIl+yj2kU6rjCErFYYyUiclmQRr7xnGGLG/tm8P6D1bQXKoyB6U5BB+SiB4Ac31dZ hkuIhpsH8Q2XQ== From: Vinod Koul To: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH 6/6] arm64: dts: qcom: sc8180x: Introduce Lenovo Flex 5G Date: Fri, 16 Sep 2022 17:42:04 +0530 Message-Id: <20220916121204.3880182-7-vkoul@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220916121204.3880182-1-vkoul@kernel.org> References: <20220916121204.3880182-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bjorn Andersson Introduce support for the Lenovo Flex 5G laptop, built on the Qualcomm SC8180X platform. Supported peripherals includes keyboard, touchpad, UFS storage, external USB and WiFi. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 590 ++++++++++++++++++ 2 files changed, 591 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f1c620bb078e..a9de6f50ca37 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -112,6 +112,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-herobrine-villager-= r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sc8180x-lenovo-flex-5g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc8180x-primus.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc8280xp-lenovo-thinkpad-x13s.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm= 64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts new file mode 100644 index 000000000000..559a1fb6173f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sc8180x.dtsi" +#include "sc8180x-pmics.dtsi" + +/ { + model =3D "Lenovo Flex 5G"; + compatible =3D "lenovo,flex-5g", "qcom,sc8180x"; + + aliases { + serial0 =3D &uart13; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pmc8180c_lpg 4 1000000>; + enable-gpios =3D <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bl_pwm_default_state>; + }; + + chosen { + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hall_int_active_state>; + + lid { + gpios =3D <&tlmm 121 GPIO_ACTIVE_LOW>; + linux,input-type =3D ; + linux,code =3D ; + wakeup-source; + wakeup-event-action =3D ; + }; + }; + + reserved-memory { + rmtfs_mem: rmtfs-region@85500000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x85500000 0x0 0x200000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D <15>; + }; + + wlan_mem: wlan-region@8bc00000 { + reg =3D <0x0 0x8bc00000 0x0 0x180000>; + no-map; + }; + + mpss_mem: mpss-region@8d800000 { + reg =3D <0x0 0x8d800000 0x0 0x3000000>; + no-map; + }; + + adsp_mem: adsp-region@90800000 { + reg =3D <0x0 0x90800000 0x0 0x1c00000>; + no-map; + }; + + gpu_mem: gpu-region@98715000 { + reg =3D <0x0 0x98715000 0x0 0x2000>; + no-map; + }; + + cdsp_mem: cdsp-region@98900000 { + reg =3D <0x0 0x98900000 0x0 0x1400000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_s4a_1p8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vph_pwr>; + }; +}; + +&apps_rsc { + pmc8180-a-rpmh-regulators { + compatible =3D "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s5-supply =3D <&vph_pwr>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5a_2p0>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt =3D <2040000>; + regulator-max-microvolt =3D <2100000>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l9a_1p3: ldo9 { + regulator-min-microvolt =3D <1296000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + }; + + pmc8180c-rpmh-regulators { + compatible =3D "qcom,pmc8180c-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-s6-supply =3D <&vph_pwr>; + vdd-l2-l3-supply =3D <&vreg_s6c_1p35>; + vdd-bob-supply =3D <&vph_pwr>; + + vreg_s6c_1p35: smps6 { + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1372000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_bob: bob { + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3350000>; + regulator-initial-mode =3D ; + }; + }; + + pmc8180-e-rpmh-regulators { + compatible =3D "qcom,pmc8180-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-l2-l10-supply =3D <&vreg_bob>; + vdd-l3-l4-l5-l18-supply =3D <&vreg_s4e_0p98>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5e_2p05>; + vdd-l13-l16-l17-supply =3D <&vreg_bob>; + + vreg_s4e_0p98: smps4 { + regulator-min-microvolt =3D <992000>; + regulator-max-microvolt =3D <992000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_2p05: smps5 { + regulator-min-microvolt =3D <2040000>; + regulator-max-microvolt =3D <2040000>; + regulator-initial-mode =3D ; + }; + + vreg_l1e_0p75: ldo1 { + regulator-min-microvolt =3D <752000>; + regulator-max-microvolt =3D <752000>; + regulator-initial-mode =3D ; + }; + + vreg_l5e_0p88: ldo5 { + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l7e_1p8: ldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l10e_2p9: ldo10 { + regulator-min-microvolt =3D <2904000>; + regulator-max-microvolt =3D <2904000>; + regulator-initial-mode =3D ; + }; + + vreg_l16e_3p0: ldo16 { + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&dispcc { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; + + zap-shader { + memory-region =3D <&gpu_mem>; + firmware-name =3D "qcom/sc8180x/qcdxkmsuc8180.mbn"; + }; +}; + +&i2c1 { + clock-frequency =3D <100000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_active>, <&i2c1_hid_active>; + + status =3D "okay"; + + hid@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + hid-descr-addr =3D <0x1>; + + interrupts-extended =3D <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c7 { + clock-frequency =3D <100000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c7_active>, <&i2c7_hid_active>; + + status =3D "okay"; + + hid@5 { + compatible =3D "hid-over-i2c"; + reg =3D <0x5>; + hid-descr-addr =3D <0x20>; + + interrupts-extended =3D <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + }; + + hid@2c { + compatible =3D "hid-over-i2c"; + reg =3D <0x2c>; + hid-descr-addr =3D <0x20>; + + interrupts-extended =3D <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_edp { + data-lanes =3D <0 1 2 3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_hpd_active>; + + status =3D "okay"; + + aux-bus { + panel { + compatible =3D "edp-panel"; + no-hpd; + + backlight =3D <&backlight>; + + ports { + port { + auo_b140han06_in: endpoint { + remote-endpoint =3D <&mdss_edp_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg =3D <1>; + mdss_edp_out: endpoint { + remote-endpoint =3D <&auo_b140han06_in>; + }; + }; + }; +}; + +&pcie3 { + perst-gpio =3D <&tlmm 178 GPIO_ACTIVE_LOW>; + wake-gpio =3D <&tlmm 180 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie3_default_state>; + + status =3D "okay"; +}; + +&pcie3_phy { + vdda-phy-supply =3D <&vreg_l5e_0p88>; + vdda-pll-supply =3D <&vreg_l3c_1p2>; + + status =3D "okay"; +}; + +&pmc8180c_lpg { + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&qupv3_id_2 { + status =3D "okay"; +}; + +&remoteproc_adsp { + memory-region =3D <&adsp_mem>; + firmware-name =3D "qcom/sc8180x/qcadsp8180.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + memory-region =3D <&cdsp_mem>; + firmware-name =3D "qcom/sc8180x/qccdsp8180.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + memory-region =3D <&mpss_mem>; + firmware-name =3D "qcom/sc8180x/qcmpss8180_nm.mbn"; + + status =3D "okay"; +}; + +&uart13 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart13_state>; + + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn3998-bt"; + + vddio-supply =3D <&vreg_s4a_1p8>; + vddxo-supply =3D <&vreg_l7a_1p8>; + vddrf-supply =3D <&vreg_l9a_1p3>; + vddch0-supply =3D <&vreg_l11c_3p3>; + max-speed =3D <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 190 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l10e_2p9>; + vcc-max-microamp =3D <155000>; + + vccq2-supply =3D <&vreg_l7e_1p8>; + vccq2-max-microamp =3D <425000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l5e_0p88>; + vdda-pll-supply =3D <&vreg_l3c_1p2>; + + status =3D "okay"; +}; + +&usb_prim_hsphy { + vdda-pll-supply =3D <&vreg_l5e_0p88>; + vdda18-supply =3D <&vreg_l12a_1p8>; + vdda33-supply =3D <&vreg_l16e_3p0>; + + status =3D "okay"; +}; + +&usb_prim_qmpphy { + vdda-phy-supply =3D <&vreg_l3c_1p2>; + vdda-pll-supply =3D <&vreg_l5e_0p88>; + + status =3D "okay"; +}; + +&usb_prim { + status =3D "okay"; +}; + +&usb_prim_dwc3 { + dr_mode =3D "host"; +}; + +&usb_sec_hsphy { + vdda-pll-supply =3D <&vreg_l5e_0p88>; + vdda18-supply =3D <&vreg_l12a_1p8>; + vdda33-supply =3D <&vreg_l16e_3p0>; + + status =3D "okay"; +}; + +&usb_sec_qmpphy { + vdda-phy-supply =3D <&vreg_l3c_1p2>; + vdda-pll-supply =3D <&vreg_l5e_0p88>; + + status =3D "okay"; +}; + +&usb_sec { + status =3D "okay"; +}; + +&usb_sec_dwc3 { + dr_mode =3D "host"; +}; + +&wifi { + memory-region =3D <&wlan_mem>; + + vdd-0.8-cx-mx-supply =3D <&vreg_l1e_0p75>; + vdd-1.8-xo-supply =3D <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply =3D <&vreg_l9a_1p3>; + vdd-3.3-ch0-supply =3D <&vreg_l11c_3p3>; + vdd-3.3-ch1-supply =3D <&vreg_l10c_3p3>; + + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; + +/* PINCTRL */ + +&pmc8180c_gpios { + bl_pwm_default_state: bl-pwm-default-state { + en { + pins =3D "gpio8"; + function =3D "normal"; + }; + + pwm { + pins =3D "gpio10"; + function =3D "func1"; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <0 4>, <47 4>, <126 4>; + + edp_hpd_active: epd-hpd-active-state { + pins =3D "gpio10"; + function =3D "edp_hot"; + }; + + hall_int_active_state: hall-int-active-state { + pins =3D "gpio121"; + function =3D "gpio"; + + input-enable; + bias-disable; + }; + + i2c1_active: i2c1-active-state { + pins =3D "gpio114", "gpio115"; + function =3D "qup1"; + + bias-pull-up =3D <1>; + drive-strength =3D <2>; + }; + + i2c1_hid_active: i2c1-hid-active-state { + pins =3D "gpio122"; + function =3D "gpio"; + + input-enable; + bias-pull-up; + drive-strength =3D <2>; + }; + + i2c7_active: i2c7-active-state { + pins =3D "gpio98", "gpio99"; + function =3D "qup7"; + + bias-pull-up; + drive-strength =3D <2>; + }; + + i2c7_hid_active: i2c7-hid-active-state { + pins =3D "gpio37", "gpio24"; + function =3D "gpio"; + + input-enable; + bias-pull-up; + drive-strength =3D <2>; + }; + + pcie3_default_state: pcie3-default-state { + clkreq { + pins =3D "gpio179"; + function =3D "pci_e3"; + bias-pull-up; + }; + + reset-n { + pins =3D "gpio178"; + function =3D "gpio"; + + drive-strength =3D <2>; + output-low; + bias-pull-down; + }; + + wake-n { + pins =3D "gpio180"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + uart13_state: uart13-state { + cts { + pins =3D "gpio43"; + function =3D "qup13"; + bias-pull-down; + }; + + rts-tx { + pins =3D "gpio44", "gpio45"; + function =3D "qup13"; + drive-strength =3D <2>; + bias-disable; + }; + + rx { + pins =3D "gpio46"; + function =3D "qup13"; + bias-pull-up; + }; + }; +}; --=20 2.37.3