From nobody Tue Dec 16 11:06:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D38EECAAD8 for ; Fri, 16 Sep 2022 11:27:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231381AbiIPL1n (ORCPT ); Fri, 16 Sep 2022 07:27:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231168AbiIPL1d (ORCPT ); Fri, 16 Sep 2022 07:27:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9141A4B0C; Fri, 16 Sep 2022 04:27:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663327647; x=1694863647; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hyLDKbNNI38wXrC5Tei7bV2mB9uLlpphPD5ViUjlS80=; b=Gu73X08GaNR79I2hTzf/awwLNnW/ob9SVkhBlo5FbEUVku5LTJcmV9Pt 4voqN7c2kiqBod5Su8F1FNoxI2atv/bDcwBAUJBudr2T7Vm+VdsSdqhGs AS1+MsGfCGT5ZtDWJLTtZJg8JopplrlEL5MEu3+A7MZEN+KY/GghqyPB1 XvAJBi8mXa9CFC0Jfq0vF1AHCi4NRZ3x4FB5MtBMp/rDsAnzYBt2EJb2x Ck7e7GngGvjM1IrQkBkGXBtuw0Wknb3IteH2xDu9u1l01CYMTjqTvR4ON 1vak8n1vl0RcRm6t5augz9/YJ30+v9cSvFJc0qBMQ8jxvPVBKlEcm2HmZ g==; X-IronPort-AV: E=Sophos;i="5.93,320,1654585200"; d="scan'208";a="180674454" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Sep 2022 04:27:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 16 Sep 2022 04:27:25 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 16 Sep 2022 04:27:22 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v5 04/10] riscv: dts: microchip: add pci dma ranges for the icicle kit Date: Fri, 16 Sep 2022 12:26:40 +0100 Message-ID: <20220916112645.567794-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220916112645.567794-1-conor.dooley@microchip.com> References: <20220916112645.567794-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The recently removed, accidentally included, "matr0" property was used in place of a dma-ranges property. The PCI controller is non-functional with mainline Linux in the v2022.02 or later reference designs and has not worked without configuration of address-translation since v2021.08. Add the address translation that will be used by the v2022.09 reference design & update the compatible used by the dts. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 7 ++++++- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..c0fb9dd7b2c8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,7 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { - compatible =3D "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpf= s"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; @@ -37,3 +38,7 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; }; + +&pcie { + dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index f3f87ed2007f..5e2b8aa2ff64 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -11,7 +11,8 @@ =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; - compatible =3D "microchip,mpfs-icicle-kit", "microchip,mpfs"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 aliases { ethernet0 =3D &mac1; --=20 2.36.1