From nobody Fri Apr 3 08:36:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8182CC54EE9 for ; Fri, 16 Sep 2022 07:58:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230166AbiIPH6U (ORCPT ); Fri, 16 Sep 2022 03:58:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230229AbiIPH6O (ORCPT ); Fri, 16 Sep 2022 03:58:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1805CA2A85; Fri, 16 Sep 2022 00:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663315094; x=1694851094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kgThLOh4QkWZRER1Ml08oPm7rzxh1NxPviLbjfoi9jI=; b=GlbzdRAvkjsxsPB4dEAnN5ykIA3gIjVEl3KEpbnaLQH8kIDqQTDgX2a0 TTpapAP63D92ebWSaLyHd1cGMVcmlPl4eXUAAvXq7xT7FXM0hi3CcmIyM Ii98ovwReRqUPJB0p8l3gUqEWlypoyA0772Dxr/X/5/3DvDfoEUjuQobr iRov5VH1AfsH3hAOc3MbValvETf//t+vGCxL0vaCfRl0O0ss7FZ/hhfb6 wAQIbGEi9kd6/oJHGV7mwUBhKL/0LMHpFfy15W/ShTHC7exKll3lZ1V9S 20sjEvuK8t8Cd7aTl2h4qVv4vr76xsDI330xNRiLTnHvPWYT5hTAc5FIS w==; X-IronPort-AV: E=Sophos;i="5.93,320,1654585200"; d="scan'208";a="180657366" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Sep 2022 00:58:13 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 16 Sep 2022 00:58:11 -0700 Received: from kavya.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 16 Sep 2022 00:58:07 -0700 From: Kavyasree Kotagiri To: , CC: , , , , , , , , , Rob Herring Subject: [PATCH v9 1/3] dt-bindings: mfd: Convert atmel-flexcom to json-schema Date: Fri, 16 Sep 2022 05:57:42 -0200 Message-ID: <20220916075744.1879428-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220916075744.1879428-1-kavyasree.kotagiri@microchip.com> References: <20220916075744.1879428-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the Atmel flexcom device tree bindings to json schema. Signed-off-by: Kavyasree Kotagiri Reviewed-by: Rob Herring Acked-by: Krzysztof Kozlowski --- v8 -> v9: - Use full schema path for i2c bindings. Changing reference to SPI yaml bindings is covered in below patch series: https://lore.kernel.org/linux-arm-kernel/20220913142205.162399-6-sergiu.mog= a@microchip.com/ https://lore.kernel.org/linux-arm-kernel/dad37ca0-a44b-59ec-0be9-fb121de122= 44@linaro.org/ v7 -> v8: - Added back patternProperties for child nodes. v6 -> v7: - Change filename to atmel,sama5d2-flexcom.yaml - Add #address-cells, #size-cells to flexcom node - Fixed warnings. v5 -> v6: - Removed spi node from example as suggested by Rob and also pattern properties(spi dt-bindings conversion to yaml patch is unde= r review). Once that is accepted, I will add back spi example through new patch. v4 -> v5: - Fixed indentations. v3 -> v4: - Corrected format of enum used for compatible string. v2 -> v3: - used enum for compatible string. - changed irq flag to IRQ_TYPE_LEVEL_HIGH in example. - fixed dtschema errors. v1 -> v2: - Fix title. .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 92 +++++++++++++++++++ .../devicetree/bindings/mfd/atmel-flexcom.txt | 63 ------------- 2 files changed, 92 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,sama5d2-fle= xcom.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.ya= ml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml new file mode 100644 index 000000000000..f28522cd987a --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,sama5d2-flexcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Flexcom (Flexible Serial Communication Unit) + +maintainers: + - Kavyasree Kotagiri + +description: + The Atmel Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. Only one function can be used at a + time and is chosen at boot time according to the device tree. + +properties: + compatible: + enum: + - atmel,sama5d2-flexcom + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + description: + One range for the full I/O register region. (including USART, + TWI and SPI registers). + items: + maxItems: 3 + + atmel,flexcom-mode: + description: | + Specifies the flexcom mode as follows: + 1: USART + 2: SPI + 3: I2C. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +patternProperties: + "^serial@[0-9a-f]+$": + type: object + description: + Child node describing USART. See atmel-usart.txt for details + of USART bindings. + + "^spi@[0-9a-f]+$": + type: object + description: + Child node describing SPI. See ../spi/spi_atmel.txt for details + of SPI bindings. + + "^i2c@[0-9a-f]+$": + $ref: /schemas/i2c/atmel,at91sam-i2c.yaml + description: + Child node describing I2C. + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + - atmel,flexcom-mode + +additionalProperties: false + +examples: + - | + #include + + flx0: flexcom@f8034000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8034000 0x200>; + clocks =3D <&flx0_clk>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8034000 0x800>; + atmel,flexcom-mode =3D <2>; + }; +... diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Docu= mentation/devicetree/bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index 9d837535637b..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Un= it) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is ch= osen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as on= e for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible =3D "atmel,sama5d2-flexcom"; - reg =3D <0xf8034000 0x200>; - clocks =3D <&flx0_clk>; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges =3D <0x0 0xf8034000 0x800>; - atmel,flexcom-mode =3D <2>; - - spi@400 { - compatible =3D "atmel,at91rm9200-spi"; - reg =3D <0x400 0x200>; - interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_flx0_default>; - #address-cells =3D <1>; - #size-cells =3D <0>; - clocks =3D <&flx0_clk>; - clock-names =3D "spi_clk"; - atmel,fifo-size =3D <32>; - - flash@0 { - compatible =3D "atmel,at25f512b"; - reg =3D <0>; - spi-max-frequency =3D <20000000>; - }; - }; -}; --=20 2.25.1 From nobody Fri Apr 3 08:36:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E57DECAAD8 for ; Fri, 16 Sep 2022 07:58:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230229AbiIPH63 (ORCPT ); Fri, 16 Sep 2022 03:58:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230237AbiIPH6W (ORCPT ); Fri, 16 Sep 2022 03:58:22 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A06C1A2866; Fri, 16 Sep 2022 00:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663315100; x=1694851100; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rO6H+J0Xghv6mHJ5wP/i3eWk4MOnt7Kwf+PxWbTBzE4=; b=gHiVEANFglqugM5t8I8hri7VmBc2GwmFpWq29l9Y1oyTOLBgmYBRaneJ J50Q5b4S/YCXQP9WNBYAlJRstmTeLrbqanIjjyiZnXDollB1p3uBGuNuI bY85MO2BheisW0S8VQM6BvkTrCe1UFRCUwxu80S4UMZwJkBp2+nAz3/ja LNM5mGzFhvyjY761xDqz86bKA+VyYENvPxQ/TkXMQj+jr+SX11jK45rDw AI3tz4gK39u48bFXco07hrBvBrXjj1WT/l8vKw5RrsvH+e0lyXpVRWF1q 3vc9QYSFtP4cQo9Wv6HVTRFbanZ/znC6Yg+IQxlPbY/50Ax0LnNM9eQd4 A==; X-IronPort-AV: E=Sophos;i="5.93,320,1654585200"; d="scan'208";a="177458380" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Sep 2022 00:58:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 16 Sep 2022 00:58:17 -0700 Received: from kavya.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 16 Sep 2022 00:58:13 -0700 From: Kavyasree Kotagiri To: , CC: , , , , , , , , , Rob Herring Subject: [PATCH v9 2/3] dt-bindings: mfd: atmel,sama5d2-flexcom: Add new compatible string for lan966x Date: Fri, 16 Sep 2022 05:57:43 -0200 Message-ID: <20220916075744.1879428-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220916075744.1879428-1-kavyasree.kotagiri@microchip.com> References: <20220916075744.1879428-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri Reviewed-by: Rob Herring --- v8 -> v9: - No changes. v7 -> v8: - Changed compatible string to microchip,lan9668-flexcom. v6 -> v7: - Add #address-cells, #size-cells to flx3 example. v5 -> v6: - Removed spi node from flx3 example. v4 -> v5: - Fixed indentations and dt-schema errors. - No errors seen with 'make dt_binding_check'. v3 -> v4: - Added else condition to allOf:if:then. v2 -> v3: - Add reg property of lan966x missed in v2. v1 -> v2: - Use allOf:if:then for lan966x dt properties .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 65 ++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.ya= ml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index f28522cd987a..0c80f4e98c54 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -18,9 +18,11 @@ properties: compatible: enum: - atmel,sama5d2-flexcom + - microchip,lan9668-flexcom =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clocks: maxItems: 1 @@ -47,6 +49,27 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3] =20 + microchip,flx-shrd-pins: + description: Specify the Flexcom shared pins to be used for flexcom + chip-selects. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 20 + + microchip,flx-cs: + description: Flexcom chip selects. Here, value of '0' represents "cts"= line + of flexcom USART or "cs0" line of flexcom SPI and value of '1' repre= sents + "rts" line of flexcom USART or "cs1" line of flexcom SPI. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + patternProperties: "^serial@[0-9a-f]+$": type: object @@ -74,6 +97,31 @@ required: - ranges - atmel,flexcom-mode =20 +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan9668-flexcom + + then: + properties: + reg: + items: + - description: Flexcom base registers map + - description: Flexcom shared registers map + required: + - microchip,flx-shrd-pins + - microchip,flx-cs + + else: + properties: + reg: + items: + - description: Flexcom base registers map + microchip,flx-shrd-pins: false + microchip,flx-cs: false + additionalProperties: false =20 examples: @@ -89,4 +137,19 @@ examples: ranges =3D <0x0 0xf8034000 0x800>; atmel,flexcom-mode =3D <2>; }; + - | + #include + + flx3: flexcom@e0064000 { + compatible =3D "microchip,lan9668-flexcom"; + reg =3D <0xe0064000 0x100>, + <0xe2004180 0x8>; + clocks =3D <&flx0_clk>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xe0040000 0x800>; + atmel,flexcom-mode =3D <2>; + microchip,flx-shrd-pins =3D <9>; + microchip,flx-cs =3D <0>; + }; ... --=20 2.25.1 From nobody Fri Apr 3 08:36:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A64D1ECAAD8 for ; Fri, 16 Sep 2022 07:59:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230284AbiIPH65 (ORCPT ); Fri, 16 Sep 2022 03:58:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230282AbiIPH6p (ORCPT ); Fri, 16 Sep 2022 03:58:45 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1045A2AAE; Fri, 16 Sep 2022 00:58:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663315121; x=1694851121; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+YZ5QAM3jH7WsbzMta1Kcg57pDJVYoZo5HIrRlxfl3k=; b=GPVHPmUX9wf1Z+a6nyh3muxaPjacLXfTlQuzRNjB8YWj4xm3g7I7fGuI AoVbMXwRYxHmsBc8MioGt3Nr1ZXS2TrSRda0fW+S8yo1RA6Lr9auvQL+a A+/5IztW+2D67dsudT0Cy/IOxZIZjdJN1yqA5+Cei2rAiiDtsyT1P878B NOmctSGGf6j5VKgN1D54diD9UugL2FYHAt+bl5vBoQMXOW6rulSpqT7SR 1lJBpQ5uOA/u1bz3v+AHSitKwEL+ZNXr2kn/wQaiUYYcMlkZAMpcMIrVQ bUVbJb1XjOJ8Umlz2i6hOntp6XA/CpIIP8EPScTibR3q3F1qi+e9O2hBQ g==; X-IronPort-AV: E=Sophos;i="5.93,320,1654585200"; d="scan'208";a="180770865" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Sep 2022 00:58:25 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 16 Sep 2022 00:58:24 -0700 Received: from kavya.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 16 Sep 2022 00:58:21 -0700 From: Kavyasree Kotagiri To: , CC: , , , , , , , , Subject: [PATCH v9 3/3] mfd: atmel-flexcom: Add support for lan966x flexcom chip-select configuration Date: Fri, 16 Sep 2022 05:57:44 -0200 Message-ID: <20220916075744.1879428-4-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220916075744.1879428-1-kavyasree.kotagiri@microchip.com> References: <20220916075744.1879428-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" LAN966x SoC have 5 flexcoms. Each flexcom has 2 chip-selects which are optional I/O lines. For each chip select of each flexcom there is a configuration register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration register is 21 because there are 21 shared pins on each of which the chip select can be mapped. Each bit of the register represents a different FLEXCOM_SHARED pin. Signed-off-by: Kavyasree Kotagiri Reviewed-by: Claudiu Beznea --- v8 -> v9: - No changes. v7 -> v8: - Changed compatible string to microchip,lan9668-flexcom. v6 -> v7: - No changes. v5 -> v6: - No changes. v4 -> v5: - No changes. v3 -> v4: - Add condition for a flexcom whether to configure chip-select lines or not, based on "microchip,flx-shrd-pins" property existence because chip-select lines are optional. v2 -> v3: - used goto label for clk_disable in error cases. v1 -> v2: - use GENMASK for mask, macros for maximum allowed values. - use u32 values for flexcom chipselects instead of strings. - disable clock in case of errors. drivers/mfd/atmel-flexcom.c | 94 ++++++++++++++++++++++++++++++++++++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 33caa4fba6af..92ea15d5fd72 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -28,15 +28,68 @@ #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ FLEX_MR_OPMODE_MASK) =20 +/* LAN966x flexcom shared register offsets */ +#define FLEX_SHRD_SS_MASK_0 0x0 +#define FLEX_SHRD_SS_MASK_1 0x4 +#define FLEX_SHRD_PIN_MAX 20 +#define FLEX_CS_MAX 1 +#define FLEX_SHRD_MASK GENMASK(20, 0) + +struct atmel_flex_caps { + bool has_flx_cs; +}; + struct atmel_flexcom { void __iomem *base; + void __iomem *flexcom_shared_base; u32 opmode; struct clk *clk; }; =20 +static int atmel_flexcom_lan966x_cs_config(struct platform_device *pdev) +{ + struct atmel_flexcom *ddata =3D dev_get_drvdata(&pdev->dev); + struct device_node *np =3D pdev->dev.of_node; + u32 flx_shrd_pins[2], flx_cs[2], val; + int err, i, count; + + count =3D of_property_count_u32_elems(np, "microchip,flx-shrd-pins"); + if (count <=3D 0 || count > 2) { + dev_err(&pdev->dev, "Invalid %s property (%d)\n", "flx-shrd-pins", + count); + return -EINVAL; + } + + err =3D of_property_read_u32_array(np, "microchip,flx-shrd-pins", flx_shr= d_pins, count); + if (err) + return err; + + err =3D of_property_read_u32_array(np, "microchip,flx-cs", flx_cs, count); + if (err) + return err; + + for (i =3D 0; i < count; i++) { + if (flx_shrd_pins[i] > FLEX_SHRD_PIN_MAX) + return -EINVAL; + + if (flx_cs[i] > FLEX_CS_MAX) + return -EINVAL; + + val =3D ~(1 << flx_shrd_pins[i]) & FLEX_SHRD_MASK; + + if (flx_cs[i] =3D=3D 0) + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_0); + else + writel(val, ddata->flexcom_shared_base + FLEX_SHRD_SS_MASK_1); + } + + return 0; +} + static int atmel_flexcom_probe(struct platform_device *pdev) { struct device_node *np =3D pdev->dev.of_node; + const struct atmel_flex_caps *caps; struct resource *res; struct atmel_flexcom *ddata; int err; @@ -76,13 +129,52 @@ static int atmel_flexcom_probe(struct platform_device = *pdev) */ writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); =20 + caps =3D of_device_get_match_data(&pdev->dev); + if (!caps) { + dev_err(&pdev->dev, "Could not retrieve flexcom caps\n"); + err =3D -EINVAL; + goto clk_disable; + } + + if (caps->has_flx_cs && of_property_read_bool(np, "microchip,flx-shrd-pin= s")) { + ddata->flexcom_shared_base =3D devm_platform_get_and_ioremap_resource(pd= ev, 1, NULL); + if (IS_ERR(ddata->flexcom_shared_base)) { + err =3D dev_err_probe(&pdev->dev, + PTR_ERR(ddata->flexcom_shared_base), + "failed to get flexcom shared base address\n"); + goto clk_disable; + } + + err =3D atmel_flexcom_lan966x_cs_config(pdev); + if (err) + goto clk_disable; + } + +clk_disable: clk_disable_unprepare(ddata->clk); + if (err) + return err; =20 return devm_of_platform_populate(&pdev->dev); } =20 +static const struct atmel_flex_caps atmel_flexcom_caps =3D {}; + +static const struct atmel_flex_caps lan966x_flexcom_caps =3D { + .has_flx_cs =3D true, +}; + static const struct of_device_id atmel_flexcom_of_match[] =3D { - { .compatible =3D "atmel,sama5d2-flexcom" }, + { + .compatible =3D "atmel,sama5d2-flexcom", + .data =3D &atmel_flexcom_caps, + }, + + { + .compatible =3D "microchip,lan9668-flexcom", + .data =3D &lan966x_flexcom_caps, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match); --=20 2.25.1