From nobody Fri Apr 3 08:14:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60CA5ECAAD8 for ; Fri, 16 Sep 2022 04:59:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229832AbiIPE7B (ORCPT ); Fri, 16 Sep 2022 00:59:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229637AbiIPE6y (ORCPT ); Fri, 16 Sep 2022 00:58:54 -0400 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BD4E77550 for ; Thu, 15 Sep 2022 21:58:54 -0700 (PDT) Received: by mail-pj1-x1049.google.com with SMTP id z8-20020a17090a014800b001fac4204c7eso8987857pje.8 for ; Thu, 15 Sep 2022 21:58:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date; bh=7KmHy9e59eVoSueoxg3f9FMizbHT1R3TBZY/FxQb18o=; b=S0kR8aRqGLfIuoWgSOPCbfay9hkfcmLaJTniiEy8SDMIt3AsSBj2kdLam9OSWlg/FA 7CznN2UhCf9KQ1eIdy7rZKlSY5BSgQ9SYhGwBbT5xLDf0Xk82IVJcmo9zqzh3x0qhA+5 XIyYGtQKLvlJs8tYP/FtjCXKQr88TIScLm43ZQZbh0nFoCxgh+WiNAWVi7EaULaljSJs dpw4KL/TYMyQJxOd7EksHiEFP7kHByD6FFdiUU8g62fhU5HUYIiCs+Z2D96prdBoUhLB ihG+zkzTaKW3wvp2YcweEab6HHxLdq32RMhqWlL1LHvqGoIQDccc8CO1zdRevLlvIGYb Bzlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date; bh=7KmHy9e59eVoSueoxg3f9FMizbHT1R3TBZY/FxQb18o=; b=glUMyujqDB/A00QkvB/49E67DDDABtmtDmawErLNVDgxlU3ziTBbRcHuOw3I+M6N5k c/VRZGjEFOCCDAYwuKxAkSNwW+s/ehprkbM16chtEWAVDH2PQJEpli5TFXo9OCqRmXc8 qaRxX6TXo82Vp3vK60jDfzxG/TfRP2iN5DEM96fERaXDRU7Wrd9E0aBDyFLQ3qr8r+2Q f9B5JptCsrj0OkC9Cg1uzsF+aTVCydkbatEqC3sayt83rCWi9Qbo/fKou2rz5L1m2Kee qbyATh0RD6qFSA3SY1sc19IqAczUiKtgD9OWVb+qI7bo7W8mR4g3W/SI5fqtyiW1oopk SsUA== X-Gm-Message-State: ACrzQf04c+Ot0nyzvWuNGOvFbCvpZOglY0K2qyUWBI4rftOucaKxNbJW eddh/PUYKsU2rITMs6zd1wt2RuG/nfs7Tg== X-Google-Smtp-Source: AMsMyM6vsC5QW2H5IDtqxbXq4QQ2j9p2rtYA2Rsx+YLBuIJm3SCXsGpJ4JdVKURzJ37B6CRXcLGs+UH/oA5vJA== X-Received: from loggerhead.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:29a]) (user=jmattson job=sendgmr) by 2002:a17:903:11d2:b0:172:6ea1:b6e6 with SMTP id q18-20020a17090311d200b001726ea1b6e6mr3047392plh.72.1663304333667; Thu, 15 Sep 2022 21:58:53 -0700 (PDT) Date: Thu, 15 Sep 2022 21:58:28 -0700 In-Reply-To: <20220916045832.461395-1-jmattson@google.com> Mime-Version: 1.0 References: <20220916045832.461395-1-jmattson@google.com> X-Mailer: git-send-email 2.37.3.968.ga6b4b080e4-goog Message-ID: <20220916045832.461395-2-jmattson@google.com> Subject: [PATCH 1/5] x86/cpufeatures: Introduce X86_FEATURE_NO_LMSLE From: Jim Mattson To: Avi Kivity , Babu Moger , Borislav Petkov , "Chang S. Bae" , Dave Hansen , "H. Peter Anvin" , Ingo Molnar , Joerg Roedel , Josh Poimboeuf , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Paolo Bonzini , Pawan Gupta , Peter Zijlstra , Sean Christopherson , Thomas Gleixner , Wyes Karny , x86@kernel.org Cc: Jim Mattson Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When AMD introduced "Long Mode Segment Limit Enable" (a.k.a. "VMware mode"), the feature was not enumerated by a CPUID bit. Now that VMware has abandoned binary translation, AMD has deprecated EFER.LMSLE. The absence of the feature *is* now enumerated by a CPUID bit (a la Intel's X86_FEATURE_ZERO_FCS_DCS and X86_FEATURE_FDP_EXCPTN_ONLY). This defeature bit is already present in feature word 13, but it was previously anonymous. Name it X86_FEATURE_NO_LMSLE, so that KVM can reference it when deciding whether or not EFER.LMSLE should be a reserved bit in a KVM guest. Since this bit indicates the absence of a feature, don't enumerate it in /proc/cpuinfo. Signed-off-by: Jim Mattson --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index ef4775c6db01..0f5a3285d8d8 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -319,6 +319,7 @@ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted = Speculation */ #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Bra= nch Predictors */ #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Ind= irect Branch Predictors always-on preferred */ +#define X86_FEATURE_NO_LMSLE (13*32+20) /* "" EFER_LMSLE is unsupported */ #define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory = Number */ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Di= sable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store= Bypass Disable */ --=20 2.37.3.968.ga6b4b080e4-goog