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[24.4.73.83]) by smtp.gmail.com with ESMTPSA id l16-20020a17090a071000b00200b2894648sm330518pjl.52.2022.09.15.20.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 20:06:02 -0700 (PDT) From: Vineet Gupta To: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Palmer Dabbelt , Christoph Muellner , linu@rivosinc.com, Vineet Gupta Subject: [PATCH] riscv: ztso: disallow elf binaries needing TSO Date: Thu, 15 Sep 2022 20:05:52 -0700 Message-Id: <20220916030552.1396820-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As of now the software stack needs work to support ztso. Until that work is finished, disallow binaries needing TSO. This patch is needed to help ztso ratification and prolifiration of tso bits in tooling. Signed-off-by: Vineet Gupta --- arch/riscv/include/asm/elf.h | 11 ++++++++++- arch/riscv/include/uapi/asm/elf.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f53c40026c7a..37a47352f633 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -26,10 +26,19 @@ =20 #define ELF_DATA ELFDATA2LSB =20 +/* + * Make sure the extensions are compatible. + * + * In the final incarnation this will get the features as provided by DT a= nd + * make sure kernel build is compatible. + * For now disallow TSO built binaries. + */ +#define rv_ext_ok(x) (!((x)->e_flags & EF_RISCV_TSO)) + /* * This is used to ensure we don't load something for the wrong architectu= re. */ -#define elf_check_arch(x) ((x)->e_machine =3D=3D EM_RISCV) +#define elf_check_arch(x) ((x)->e_machine =3D=3D EM_RISCV && rv_ext_ok()) =20 #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE (PAGE_SIZE) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/as= m/elf.h index d696d6610231..fa9e4c52c7ac 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -32,6 +32,8 @@ typedef union __riscv_fp_state elf_fpregset_t; #define ELF_RISCV_R_TYPE(r_info) ELF32_R_TYPE(r_info) #endif =20 +#define EF_RISCV_TSO (1 << 3) + /* * RISC-V relocation types */ --=20 2.34.1