From nobody Sat Sep 21 17:22:23 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64D54C32771 for ; Fri, 16 Sep 2022 02:51:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229553AbiIPCva (ORCPT ); Thu, 15 Sep 2022 22:51:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229772AbiIPCvO (ORCPT ); Thu, 15 Sep 2022 22:51:14 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 210B498C9D; Thu, 15 Sep 2022 19:51:09 -0700 (PDT) X-UUID: 7ca34679584b4ff5845b10ce81e95bf4-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oNoZT8GHmsYXrwIBJ4X7UKKmHGPDl6GG2bXgSJSl9OY=; b=UoriI0uAU24ILb9nfJUnXzbLRlzx1qwg2tEqt5bjkStwZATwX58J157Df0RfOzPeIgw0Y5BqEES/cnB9N8Zj0v+QyS2QCIhXr4O7Ucfik6bEE0WifukrQUfCXEEj3nThUwPDWlw20gK0jb/8mhl0Jg5lS3Ws0vZooYK24ifXuuI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:1d640cda-9f2b-4213-8fd9-4063be07e34d,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:dc58d17b-ea28-4199-b57e-003c7d60873a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 7ca34679584b4ff5845b10ce81e95bf4-20220916 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1467601953; Fri, 16 Sep 2022 10:51:02 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 16 Sep 2022 10:51:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 16 Sep 2022 10:51:00 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v3 2/4] arm64: dts: mt8195: Add edptx and dptx nodes Date: Fri, 16 Sep 2022 10:50:57 +0800 Message-ID: <20220916025059.16673-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220916025059.16673-1-rex-bc.chen@mediatek.com> References: <20220916025059.16673-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MT8195, we use edptx as the internal display interface and use dptx as the external display interface. Therefore, we need to add these nodes to support the internal display and the external display. - Add dp calibration data in the efuse node. - Add edptx and dptx nodes for MT8195. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 82d28e9f60c3..83567d90ede6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1241,6 +1241,9 @@ reg =3D <0x189 0x2>; bits =3D <7 5>; }; + dp_calibration: dp-data@1ac { + reg =3D <0x1ac 0x10>; + }; }; =20 u3phy2: t-phy@11c40000 { @@ -2178,5 +2181,27 @@ clock-names =3D "engine", "pixel", "pll"; status =3D "disabled"; }; + + edp_tx: edp-tx@1c500000 { + compatible =3D "mediatek,mt8195-edp-tx"; + reg =3D <0 0x1c500000 0 0x8000>; + nvmem-cells =3D <&dp_calibration>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts =3D ; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible =3D "mediatek,mt8195-dp-tx"; + reg =3D <0 0x1c600000 0 0x8000>; + nvmem-cells =3D <&dp_calibration>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts =3D ; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; }; }; --=20 2.18.0