From nobody Sat Sep 21 13:49:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3F06C32771 for ; Fri, 16 Sep 2022 02:51:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229784AbiIPCvO (ORCPT ); Thu, 15 Sep 2022 22:51:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229479AbiIPCvM (ORCPT ); Thu, 15 Sep 2022 22:51:12 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5D5A98A6E; Thu, 15 Sep 2022 19:51:07 -0700 (PDT) X-UUID: eca0733e52624733861866cb70429251-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=A2boyUMI62PGkfAXY8Q9C0h4jRd50SVJCo47zEUPaUc=; b=KzsstLbVABMMqzefmR8KTKWQ2fUSvn4ilDByCwhYfN+XAcsch6NoLFXIPyw8pT2cHDVsx9ci3Xp1jJsH5FPABZyR4ZuxFSRmRqC9jghygVocDghydBnrDeOox7ehnKiY7A4VA4IqBD3VjhbwrDhOLRsmZH9W+0sbG9R0gqpYX94=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:bb51bde2-5cac-4142-9f1b-b03e0da6bf02,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.11,REQID:bb51bde2-5cac-4142-9f1b-b03e0da6bf02,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:39a5ff1,CLOUDID:e158d17b-ea28-4199-b57e-003c7d60873a,B ulkID:220916105103EBM83LEM,BulkQuantity:0,Recheck:0,SF:28|17|19|48,TC:nil, Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: eca0733e52624733861866cb70429251-20220916 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1487704316; Fri, 16 Sep 2022 10:51:02 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 16 Sep 2022 10:51:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 16 Sep 2022 10:51:00 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v3 1/4] arm64: dts: mt8195: Add dp-intf nodes Date: Fri, 16 Sep 2022 10:50:56 +0800 Message-ID: <20220916025059.16673-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220916025059.16673-1-rex-bc.chen@mediatek.com> References: <20220916025059.16673-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 nodes. Dp-intf0 is for edptx and dp-intf1 is for dptx. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 905d1a90b406..82d28e9f60c3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2067,6 +2067,17 @@ mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; =20 + dp_intf0: dp-intf@1c015000 { + compatible =3D "mediatek,mt8195-dp-intf"; + reg =3D <0 0x1c015000 0 0x1000>; + interrupts =3D ; + clocks =3D <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names =3D "engine", "pixel", "pll"; + status =3D "disabled"; + }; + mutex: mutex@1c016000 { compatible =3D "mediatek,mt8195-disp-mutex"; reg =3D <0 0x1c016000 0 0x1000>; @@ -2155,5 +2166,17 @@ clock-names =3D "apb", "smi", "gals"; power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + + dp_intf1: dp-intf@1c113000 { + compatible =3D "mediatek,mt8195-dp-intf"; + reg =3D <0 0x1c113000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks =3D <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names =3D "engine", "pixel", "pll"; + status =3D "disabled"; + }; }; }; --=20 2.18.0 From nobody Sat Sep 21 13:49:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64D54C32771 for ; Fri, 16 Sep 2022 02:51:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229553AbiIPCva (ORCPT ); Thu, 15 Sep 2022 22:51:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229772AbiIPCvO (ORCPT ); Thu, 15 Sep 2022 22:51:14 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 210B498C9D; Thu, 15 Sep 2022 19:51:09 -0700 (PDT) X-UUID: 7ca34679584b4ff5845b10ce81e95bf4-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oNoZT8GHmsYXrwIBJ4X7UKKmHGPDl6GG2bXgSJSl9OY=; b=UoriI0uAU24ILb9nfJUnXzbLRlzx1qwg2tEqt5bjkStwZATwX58J157Df0RfOzPeIgw0Y5BqEES/cnB9N8Zj0v+QyS2QCIhXr4O7Ucfik6bEE0WifukrQUfCXEEj3nThUwPDWlw20gK0jb/8mhl0Jg5lS3Ws0vZooYK24ifXuuI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:1d640cda-9f2b-4213-8fd9-4063be07e34d,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:39a5ff1,CLOUDID:dc58d17b-ea28-4199-b57e-003c7d60873a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 7ca34679584b4ff5845b10ce81e95bf4-20220916 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1467601953; Fri, 16 Sep 2022 10:51:02 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 16 Sep 2022 10:51:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 16 Sep 2022 10:51:00 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v3 2/4] arm64: dts: mt8195: Add edptx and dptx nodes Date: Fri, 16 Sep 2022 10:50:57 +0800 Message-ID: <20220916025059.16673-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220916025059.16673-1-rex-bc.chen@mediatek.com> References: <20220916025059.16673-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MT8195, we use edptx as the internal display interface and use dptx as the external display interface. Therefore, we need to add these nodes to support the internal display and the external display. - Add dp calibration data in the efuse node. - Add edptx and dptx nodes for MT8195. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 82d28e9f60c3..83567d90ede6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1241,6 +1241,9 @@ reg =3D <0x189 0x2>; bits =3D <7 5>; }; + dp_calibration: dp-data@1ac { + reg =3D <0x1ac 0x10>; + }; }; =20 u3phy2: t-phy@11c40000 { @@ -2178,5 +2181,27 @@ clock-names =3D "engine", "pixel", "pll"; status =3D "disabled"; }; + + edp_tx: edp-tx@1c500000 { + compatible =3D "mediatek,mt8195-edp-tx"; + reg =3D <0 0x1c500000 0 0x8000>; + nvmem-cells =3D <&dp_calibration>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts =3D ; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible =3D "mediatek,mt8195-dp-tx"; + reg =3D <0 0x1c600000 0 0x8000>; + nvmem-cells =3D <&dp_calibration>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts =3D ; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; }; }; --=20 2.18.0 From nobody Sat Sep 21 13:49:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CCE4ECAAD3 for ; Fri, 16 Sep 2022 02:51:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229686AbiIPCvf (ORCPT ); Thu, 15 Sep 2022 22:51:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229774AbiIPCvO (ORCPT ); Thu, 15 Sep 2022 22:51:14 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2391098C80; Thu, 15 Sep 2022 19:51:08 -0700 (PDT) X-UUID: ede11568832943e0aee03cade5a981f5-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=g8vhFKeVZODszpNNdcs1n44q8B0+ixfLD0v3NWycG2k=; b=ur7oYMGFTjBoOEWmOCNF7+PRmYRlysJlo8T8HWBRGr+/HWXnfz3STkJ2bwPyT6ENj1oaJioGLZPd9oaqXe4GAh/fp53BxyDVbsqGLeVKlZsU4kefIIiVCofFe7gAxZ5yWNZ3ZiamLl2xo3zuyuGOJEb9mI7sb2ZagXEd2dR8fiA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:ed11782a-0338-4a69-bd12-13093c17df6c,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:39a5ff1,CLOUDID:d35bd65d-5ed4-4e28-8b00-66ed9f042fbd,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: ede11568832943e0aee03cade5a981f5-20220916 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1361737509; Fri, 16 Sep 2022 10:51:02 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 16 Sep 2022 10:51:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 16 Sep 2022 10:51:00 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v3 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports Date: Fri, 16 Sep 2022 10:50:58 +0800 Message-ID: <20220916025059.16673-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220916025059.16673-1-rex-bc.chen@mediatek.com> References: <20220916025059.16673-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 ports. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- .../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 9b62e161db26..303dc32c64dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -120,6 +120,24 @@ }; }; =20 +&dp_intf0 { + status =3D "okay"; + + port { + dp_intf0_out: endpoint { + }; + }; +}; + +&dp_intf1 { + status =3D "okay"; + + port { + dp_intf1_out: endpoint { + }; + }; +}; + &i2c0 { status =3D "okay"; =20 --=20 2.18.0 From nobody Sat Sep 21 13:49:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C7C4ECAAD3 for ; Fri, 16 Sep 2022 02:51:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229894AbiIPCvY (ORCPT ); Thu, 15 Sep 2022 22:51:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229783AbiIPCvO (ORCPT ); Thu, 15 Sep 2022 22:51:14 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9CC498A71; Thu, 15 Sep 2022 19:51:08 -0700 (PDT) X-UUID: 98d6e13a38484344b6306fc1dd2ee21a-20220916 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=o4SwcYmQeEsPhNZNiOlAz3LSIKt52BQiCkN0gMjK+lM=; b=GjhWbedZDVF/70SBb29RJFIaXfiDZxyenGtPssYc3Lu3Mqu3YnwMgnWXewr849KjU9uPONu33kLjX5zsbEczi35zZd465teaPvjxVvBwW9FnwXHeGZItqd2dVxRe8hR5o/LBfJVgJeV8C/sosZ1HID7cAmQG4LsW3egXXgewtmo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:0bbf3912-1f5c-4fe3-80df-5f368f312e3f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:0bbf3912-1f5c-4fe3-80df-5f368f312e3f,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:d65bd65d-5ed4-4e28-8b00-66ed9f042fbd,B ulkID:220916105103D597RE6C,BulkQuantity:0,Recheck:0,SF:28|17|19|48,TC:nil, Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 98d6e13a38484344b6306fc1dd2ee21a-20220916 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 211661015; Fri, 16 Sep 2022 10:51:02 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 16 Sep 2022 10:51:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 16 Sep 2022 10:51:01 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , Bo-Chen Chen Subject: [PATCH v3 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support Date: Fri, 16 Sep 2022 10:50:59 +0800 Message-ID: <20220916025059.16673-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220916025059.16673-1-rex-bc.chen@mediatek.com> References: <20220916025059.16673-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In cherry projects, we use edptx as the internal display interface and use dptx as the external display interface. To support this, we need to add more properties. - Add pinctrls for edptx and dptx. - Add ports for edptx and dptx. The port connections for the internal and external display: dp-intf0 -> edptx -> panel dp-intf1 -> dptx The edptx endpoint is kept empty for now, as the panel addition will come in a later commit. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 303dc32c64dc..560103e29017 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -125,6 +125,7 @@ =20 port { dp_intf0_out: endpoint { + remote-endpoint =3D <&edp_in>; }; }; }; @@ -134,6 +135,59 @@ =20 port { dp_intf1_out: endpoint { + remote-endpoint =3D <&dptx_in>; + }; + }; +}; + +&edp_tx { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edptx_pins_default>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + edp_in: endpoint { + remote-endpoint =3D <&dp_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + edp_out: endpoint { + data-lanes =3D <0 1 2 3>; + }; + }; + }; +}; + +&dp_tx { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dptx_pin>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dptx_in: endpoint { + remote-endpoint =3D <&dp_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dptx_out: endpoint { + data-lanes =3D <0 1 2 3>; + }; }; }; }; @@ -497,6 +551,20 @@ }; }; =20 + edptx_pins_default: edptx-default-pins { + pins-cmd-dat { + pinmux =3D ; + bias-pull-up; + }; + }; + + dptx_pin: dptx-default-pins { + pins-cmd-dat { + pinmux =3D ; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux =3D , --=20 2.18.0