From nobody Fri Apr 3 06:44:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E839C6FA8A for ; Thu, 15 Sep 2022 10:29:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229738AbiIOK3h (ORCPT ); Thu, 15 Sep 2022 06:29:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229696AbiIOK3c (ORCPT ); Thu, 15 Sep 2022 06:29:32 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7BABC43 for ; Thu, 15 Sep 2022 03:29:30 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id v185-20020a1cacc2000000b003b42e4f278cso14398033wme.5 for ; Thu, 15 Sep 2022 03:29:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=y4XRiTWvqgw8E7sxid7nxz5JdJQpRcJN2TxmeR9LcxI=; b=UskMr1TVUJPvARbAHGUNzn4UiwFMUZlB0Pg8EpP5zSDSP1fl6GzS2MqlHLQYjG71Kk mJ7i9ugJFQlFbTlIT1tX0Rt6B+7F40RcaExLSC/fxFBjFwn5XjtonqDUNtxECzOC0g5H RWAZzm+5cAbLo5v63fZaTyVBwskAbGpAkmbiVQWL6kfJviigzbCmsHG8RLsLUZG3kOsf 76TwZdJcnKsnEeVHvYnhPkVRV8AQLOpLP0C3cIIm8ATYtVaXEEdw5NmleWJD2HVcU7JY exEcoPpIJvFE3ilh07DDzOBJIpL4bnpiUoZr+b6SwT0RL3IIGIOruY7XSCK3NMzguzB+ qVNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=y4XRiTWvqgw8E7sxid7nxz5JdJQpRcJN2TxmeR9LcxI=; b=CrkCBNumbl38xh2EUBM7RZFROA/ZZGBSI5k8IJ0Mx6duI5gOlVykj3YVmgInYsvOW1 h6nZWjoSITDttrjwDM1Fh+Ao+RM1+GrF2BtvPiFScl3PuGmvTqVgfiW2O1i9h1qZ3MLA e48DYz7B2V1FCitLYdmKAlnTzGatzGteBw194mvQPpbi1LBQv/WYqGwoWPAQVRLPMoGD zkaLiN4FIETl2Ce6hryLci9d17Kauq7OM0YQelkLesf8W5wRdRLQ76xWv5tgapktNROC GVsWMQO/p8aWMMlCTZLwm4teKsvGj5EKt9w5IkdzSIJFX2MrUK83dHA/NnxbUcOeBuee 6OIQ== X-Gm-Message-State: ACgBeo3jUNY93TB6CiB78DRAdnoqdFOHHqaASJB7Vst526kOwFfYRzDX Z8v3DO3rR8DVELs/dcWgZCPsNQ== X-Google-Smtp-Source: AA6agR4ITHPf6PE0PpNsbQL8uu+SD5+Ipjy3UMkuh7QN1NNOw1P8DQLXtw9k5JAvWgJlo0dMBPEE3w== X-Received: by 2002:a05:600c:268f:b0:3b4:acef:34ab with SMTP id 15-20020a05600c268f00b003b4acef34abmr1427464wmt.176.1663237769154; Thu, 15 Sep 2022 03:29:29 -0700 (PDT) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id q17-20020adff951000000b00228dff8d975sm2098257wrr.109.2022.09.15.03.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 03:29:28 -0700 (PDT) From: Robert Foss To: andrzej.hajda@intel.com, narmstrong@baylibre.com, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@linux.ie, daniel@ffwll.ch, dianders@chromium.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Chris Morgan , devicetree@vger.kernel.org Subject: [PATCH v1 1/2] Revert "Revert "drm/bridge: ti-sn65dsi86: Implement bridge connector operations for DP"" Date: Thu, 15 Sep 2022 12:29:23 +0200 Message-Id: <20220915102924.370090-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220915102924.370090-1-robert.foss@linaro.org> References: <20220915102924.370090-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This commit was accidentally reverted instead of another commit, and therefore needs to be reinstated. This reverts commit 8c9c40ec83445b188fb6b59e119bf5c2de81b02d. Signed-off-by: Robert Foss --- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge= /ti-sn65dsi86.c index 6e053e2af229..3c3561942eb6 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,7 @@ #define BPP_18_RGB BIT(0) #define SN_HPD_DISABLE_REG 0x5C #define HPD_DISABLE BIT(0) +#define HPD_DEBOUNCED_STATE BIT(4) #define SN_GPIO_IO_REG 0x5E #define SN_GPIO_INPUT_SHIFT 4 #define SN_GPIO_OUTPUT_SHIFT 0 @@ -1158,10 +1160,33 @@ static void ti_sn_bridge_atomic_post_disable(struct= drm_bridge *bridge, pm_runtime_put_sync(pdata->dev); } =20 +static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *br= idge) +{ + struct ti_sn65dsi86 *pdata =3D bridge_to_ti_sn65dsi86(bridge); + int val =3D 0; + + pm_runtime_get_sync(pdata->dev); + regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); + pm_runtime_put_autosuspend(pdata->dev); + + return val & HPD_DEBOUNCED_STATE ? connector_status_connected + : connector_status_disconnected; +} + +static struct edid *ti_sn_bridge_get_edid(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct ti_sn65dsi86 *pdata =3D bridge_to_ti_sn65dsi86(bridge); + + return drm_get_edid(connector, &pdata->aux.ddc); +} + static const struct drm_bridge_funcs ti_sn_bridge_funcs =3D { .attach =3D ti_sn_bridge_attach, .detach =3D ti_sn_bridge_detach, .mode_valid =3D ti_sn_bridge_mode_valid, + .get_edid =3D ti_sn_bridge_get_edid, + .detect =3D ti_sn_bridge_detect, .atomic_pre_enable =3D ti_sn_bridge_atomic_pre_enable, .atomic_enable =3D ti_sn_bridge_atomic_enable, .atomic_disable =3D ti_sn_bridge_atomic_disable, @@ -1257,6 +1282,9 @@ static int ti_sn_bridge_probe(struct auxiliary_device= *adev, pdata->bridge.type =3D pdata->next_bridge->type =3D=3D DRM_MODE_CONNECTOR= _DisplayPort ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; =20 + if (pdata->bridge.type =3D=3D DRM_MODE_CONNECTOR_DisplayPort) + pdata->bridge.ops =3D DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; + drm_bridge_add(&pdata->bridge); =20 ret =3D ti_sn_attach_host(pdata); --=20 2.34.1 From nobody Fri Apr 3 06:44:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC5F8ECAAA1 for ; Thu, 15 Sep 2022 10:29:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229899AbiIOK3o (ORCPT ); Thu, 15 Sep 2022 06:29:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229797AbiIOK3d (ORCPT ); Thu, 15 Sep 2022 06:29:33 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2DDDD49 for ; Thu, 15 Sep 2022 03:29:31 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id n40-20020a05600c3ba800b003b49aefc35fso4227694wms.5 for ; Thu, 15 Sep 2022 03:29:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=t1tgoHzcuNz6608F9ral59980nRZm0iCe/jA9+SaWcw=; b=xfY46AXwiEIXzTNjMYfvBmoBvK4Okl/KzOSF3uSeGFm9POQCmX8JyovEnujiJcNHwM Q3BVJh22F5JuOT6W6BYomK3QVYIlZkz0XNt+sRs7eohfl2mDzwt9HSwzSjqL1+PF1j5C I99VRPz5qfWn/dIucemh/z/u9xxMc9BOy2JhbFIgxaaqqq3q9hJ6G5dA/ZIfbEJy5t0z zrTUFWM6+xc6gsr7KV0J85QlrOcwQ4zjeDX9eNA9jOm6bMTFUHS7HeImyzOvC1Kl9jea +QRxQhQeaOoNkcXJWMYW5xrvveb4Xy7B53oSinOGsWTXdBO0E9KnJAdbVNffCEsei0Jv kVRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=t1tgoHzcuNz6608F9ral59980nRZm0iCe/jA9+SaWcw=; b=HI29yQekojOIdlZfo5h+hXuUHK4JpfOiThIdO1C3hJtxFz2hU5db+4kGby5u6Wuxf0 X95o+c3dYkNbBJKzcXSDzmyqugyzF7K4Nwwz4t0veC1MuxbkFDNbzyLej6VxYHRzBptB y3gqeARpOXilt7WUcfOSaEEnovng4OR+y0dRu379Ujmlry1BvI+s5W+4cmimC4Ms4RMw oGDXuxafUBKMRQUFotOtRwm+hfKlhO6ZehrdKjZMJ4C3qWq1oWVYCenSiwXW/SnSYsGk jUyk9KwdGko0IRCTihhDu2aZLDzO1tRvHc0/FAZRFPT4ItXHYn+FbPqMVp92Jv3tLvX2 H0jg== X-Gm-Message-State: ACrzQf2ydQzmLcd1gsFvi5FqCEhs+pboYnw8O8eE73dkvsWuHtXb/lUb 4LDFivUFUdUQ45eupW/ILZZLHA== X-Google-Smtp-Source: AMsMyM6l0IFcUEUYMdFQtm6+1h40cpF70ZwsOEncfkwpO534Z60smPFIjDXh6oCkTPCcHe7qz5kDEg== X-Received: by 2002:a05:600c:5110:b0:3b4:b3d7:c30f with SMTP id o16-20020a05600c511000b003b4b3d7c30fmr333227wms.93.1663237770497; Thu, 15 Sep 2022 03:29:30 -0700 (PDT) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id q17-20020adff951000000b00228dff8d975sm2098257wrr.109.2022.09.15.03.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 03:29:29 -0700 (PDT) From: Robert Foss To: andrzej.hajda@intel.com, narmstrong@baylibre.com, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@linux.ie, daniel@ffwll.ch, dianders@chromium.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Chris Morgan , devicetree@vger.kernel.org Subject: [PATCH v1 2/2] Revert "drm/bridge: chrontel-ch7033: Add byteswap order setting" Date: Thu, 15 Sep 2022 12:29:24 +0200 Message-Id: <20220915102924.370090-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220915102924.370090-1-robert.foss@linaro.org> References: <20220915102924.370090-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Revert this patch since it depends on devicetree functionality that previously has been reverted in the below commit. commit e798ba3374a1 ("Revert "dt-bindings: Add byteswap order to chrontel c= h7033"") This reverts commit ce9564cfc9aea65e68eb343c599317633bc2321a. Signed-off-by: Robert Foss --- drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bri= dge/chrontel-ch7033.c index c5719908ce2d..ba060277c3fd 100644 --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c @@ -68,7 +68,6 @@ enum { BYTE_SWAP_GBR =3D 3, BYTE_SWAP_BRG =3D 4, BYTE_SWAP_BGR =3D 5, - BYTE_SWAP_MAX =3D 6, }; =20 /* Page 0, Register 0x19 */ @@ -356,8 +355,6 @@ static void ch7033_bridge_mode_set(struct drm_bridge *b= ridge, int hsynclen =3D mode->hsync_end - mode->hsync_start; int vbporch =3D mode->vsync_start - mode->vdisplay; int vsynclen =3D mode->vsync_end - mode->vsync_start; - u8 byte_swap; - int ret; =20 /* * Page 4 @@ -401,16 +398,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *= bridge, regmap_write(priv->regmap, 0x15, vbporch); regmap_write(priv->regmap, 0x16, vsynclen); =20 - /* Input color swap. Byte order is optional and will default to - * BYTE_SWAP_BGR to preserve backwards compatibility with existing - * driver. - */ - ret =3D of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap", - &byte_swap); - if (!ret && byte_swap < BYTE_SWAP_MAX) - regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap); - else - regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); + /* Input color swap. */ + regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR); =20 /* Input clock and sync polarity. */ regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16); --=20 2.34.1