From nobody Sat Sep 21 17:27:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98AEBECAAD3 for ; Thu, 15 Sep 2022 09:48:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230103AbiIOJsE (ORCPT ); Thu, 15 Sep 2022 05:48:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230196AbiIOJrc (ORCPT ); Thu, 15 Sep 2022 05:47:32 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BD679A6AD; Thu, 15 Sep 2022 02:46:46 -0700 (PDT) X-UUID: 16c3c200d88a4082ae612dba111d7e3f-20220915 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Tor+5YS9e1tL4DVGuo3cup/t5imwJhOqvWgh/Z8He4Q=; b=AkYzedXNCosK/TtG1QUvwRRbqiku0yb+3A+6Ul6wR99eo3M1G9tBUsDR59xelVhrQqSvKhv/s6mh2ZTdggCJ7Kf/PPDr+LBm2TTPNd2oYfrUEZTIMTa7VMj+ZIX9xLdOrsjnJ9Jhp1F/FU368QqM/mrVglcJecPeB6umuk8gapg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:dc1fe0a5-45f8-4603-a04d-1a0f9c577e7a,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:39a5ff1,CLOUDID:4a00be7b-ea28-4199-b57e-003c7d60873a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 16c3c200d88a4082ae612dba111d7e3f-20220915 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1666563191; Thu, 15 Sep 2022 17:46:43 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 15 Sep 2022 17:46:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 15 Sep 2022 17:46:41 +0800 From: Bo-Chen Chen To: , CC: , , , , , , , Bo-Chen Chen Subject: [PATCH v2 2/4] arm64: dts: mt8195: Add edptx and dptx nodes Date: Thu, 15 Sep 2022 17:46:38 +0800 Message-ID: <20220915094640.5571-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220915094640.5571-1-rex-bc.chen@mediatek.com> References: <20220915094640.5571-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MT8195, we use edptx as the internal display interface and use dptx as the external display interface. Therefore, we need to add these nodes to support the internal display and the external display. - Add dp calibration data in the efuse node. - Add edptx and dptx nodes for MT8195. Signed-off-by: Bo-Chen Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 82d28e9f60c3..83567d90ede6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1241,6 +1241,9 @@ reg =3D <0x189 0x2>; bits =3D <7 5>; }; + dp_calibration: dp-data@1ac { + reg =3D <0x1ac 0x10>; + }; }; =20 u3phy2: t-phy@11c40000 { @@ -2178,5 +2181,27 @@ clock-names =3D "engine", "pixel", "pll"; status =3D "disabled"; }; + + edp_tx: edp-tx@1c500000 { + compatible =3D "mediatek,mt8195-edp-tx"; + reg =3D <0 0x1c500000 0 0x8000>; + nvmem-cells =3D <&dp_calibration>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts =3D ; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible =3D "mediatek,mt8195-dp-tx"; + reg =3D <0 0x1c600000 0 0x8000>; + nvmem-cells =3D <&dp_calibration>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts =3D ; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; }; }; --=20 2.18.0