From nobody Fri Apr 3 09:59:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED5DFECAAD3 for ; Wed, 14 Sep 2022 09:40:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229993AbiINJkS (ORCPT ); Wed, 14 Sep 2022 05:40:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230488AbiINJj7 (ORCPT ); Wed, 14 Sep 2022 05:39:59 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 001CED67; Wed, 14 Sep 2022 02:39:46 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dVAj113545; Wed, 14 Sep 2022 04:39:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663148371; bh=Nu+6daNznh/b8uWXgMlJJ6knNdhWjxmmybMsKI7CSv8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DjQ6EkTWoYyIvajgqjdhoBr1nROL/OcxubFb26EKXllLDHTAL0kLHZ/rRBcf2uD2T Y46WjULT8umjseZZfNruEW3ExnQ9oDtXM/6yV7Pb6Xt0FNlrthzMqqyglTk+PC2ell GteDT1uux/wOZsiAh7ZZGiUkFrs2zNHRVMmB/k64= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28E9dVQT014825 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Sep 2022 04:39:31 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 14 Sep 2022 04:39:30 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 14 Sep 2022 04:39:30 -0500 Received: from uda0492258.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dBHG111966; Wed, 14 Sep 2022 04:39:26 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 3/6] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e Date: Wed, 14 Sep 2022 15:09:08 +0530 Message-ID: <20220914093911.187764-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914093911.187764-1-s-vadapalli@ti.com> References: <20220914093911.187764-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Each of the CPSW9G ports in J721e support additional modes like QSGMII. Add a new compatible for J721e to support the additional modes. In TI's J721e, each of the CPSW9G ethernet interfaces can act as a QSGMII main or QSGMII-SUB port. The QSGMII main interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. Signed-off-by: Siddharth Vadapalli --- drivers/phy/ti/phy-gmii-sel.c | 47 +++++++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index f0b2ba7a9c96..fdb1a7db123d 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -223,6 +223,13 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j= 7200 =3D { .extra_modes =3D BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_= SGMII), }; =20 +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e =3D { + .use_of_data =3D true, + .regfields =3D phy_gmii_sel_fields_am654, + .extra_modes =3D BIT(PHY_INTERFACE_MODE_QSGMII), +}; + static const struct of_device_id phy_gmii_sel_id_table[] =3D { { .compatible =3D "ti,am3352-phy-gmii-sel", @@ -248,6 +255,10 @@ static const struct of_device_id phy_gmii_sel_id_table= [] =3D { .compatible =3D "ti,j7200-cpsw5g-phy-gmii-sel", .data =3D &phy_gmii_sel_cpsw5g_soc_j7200, }, + { + .compatible =3D "ti,j721e-cpsw9g-phy-gmii-sel", + .data =3D &phy_gmii_sel_cpsw9g_soc_j721e, + }, {} }; MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); @@ -389,7 +400,7 @@ static int phy_gmii_sel_probe(struct platform_device *p= dev) struct device_node *node =3D dev->of_node; const struct of_device_id *of_id; struct phy_gmii_sel_priv *priv; - u32 main_ports =3D 1; + u32 main_ports[2] =3D {1, 1}; int ret; =20 of_id =3D of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node); @@ -403,15 +414,31 @@ static int phy_gmii_sel_probe(struct platform_device = *pdev) priv->dev =3D &pdev->dev; priv->soc_data =3D of_id->data; priv->num_ports =3D priv->soc_data->num_ports; - of_property_read_u32(node, "ti,qsgmii-main-ports", &main_ports); - /* - * Ensure that main_ports is within bounds. If the property - * ti,qsgmii-main-ports is not mentioned, or the value mentioned - * is out of bounds, default to 1. - */ - if (main_ports < 1 || main_ports > 4) - main_ports =3D 1; - priv->qsgmii_main_ports =3D PHY_GMII_PORT(main_ports); + /* Differentiate between J7200 CPSW5G and J721e CPSW9G */ + if (of_device_is_compatible(node, "ti,j7200-cpsw5g-phy-gmii-sel") > 0) { + of_property_read_u32(node, "ti,qsgmii-main-ports", &main_ports[0]); + /* + * Ensure that main_ports is within bounds. If the property + * ti,qsgmii-main-ports is not mentioned, or the value mentioned + * is out of bounds, default to 1. + */ + if (main_ports[0] < 1 || main_ports[0] > 4) + main_ports[0] =3D 1; + priv->qsgmii_main_ports =3D PHY_GMII_PORT(main_ports[0]); + } else if (of_device_is_compatible(node, "ti,j721e-cpsw9g-phy-gmii-sel") = > 0) { + of_property_read_u32_array(node, "ti,qsgmii-main-ports", &main_ports[0],= 2); + /* + * Ensure that main_ports is within bounds. If the property + * ti,qsgmii-main-ports is not mentioned, or the value mentioned + * is out of bounds, default to 1. + */ + if (main_ports[0] < 1 || main_ports[0] > 8) + main_ports[0] =3D 1; + if (main_ports[1] < 1 || main_ports[1] > 8) + main_ports[1] =3D 1; + priv->qsgmii_main_ports =3D PHY_GMII_PORT(main_ports[0]); + priv->qsgmii_main_ports |=3D PHY_GMII_PORT(main_ports[1]); + } =20 priv->regmap =3D syscon_node_to_regmap(node->parent); if (IS_ERR(priv->regmap)) { --=20 2.25.1