From nobody Fri Apr 3 08:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC503ECAAD3 for ; Wed, 14 Sep 2022 09:40:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231277AbiINJkg (ORCPT ); Wed, 14 Sep 2022 05:40:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231289AbiINJkE (ORCPT ); Wed, 14 Sep 2022 05:40:04 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F3501928C; Wed, 14 Sep 2022 02:39:45 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dLRW098641; Wed, 14 Sep 2022 04:39:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663148361; bh=voil66pq2xcvIlp0IN3QHMjFzxBwFruYToUKnjtNp2g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nG2m2MGGk0a8994Z679y16TG90Kcb88iVEhB+0nsaWqtKxa9qcEgJifNXjHaw+SvS c1b33/LmZULPMVMjK/gEnDPSS7FQ4KooyZmghuaSXir1HRtmAzMyvlMabQhHwh0m5z 28Hgj24HYrufibFaqZrQJAUJmttcjdXFFkdvn2dc= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28E9dLg2119194 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Sep 2022 04:39:21 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 14 Sep 2022 04:39:21 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 14 Sep 2022 04:39:21 -0500 Received: from uda0492258.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dBHE111966; Wed, 14 Sep 2022 04:39:17 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e Date: Wed, 14 Sep 2022 15:09:06 +0530 Message-ID: <20220914093911.187764-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914093911.187764-1-s-vadapalli@ti.com> References: <20220914093911.187764-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TI's J721e SoC supports additional PHY modes like QSGMII and SGMII that are not supported on earlier SoCs. Add a compatible for it. Extend ti,qsgmii-main-ports property to support selection of upto two main ports at once across the two QSGMII interfaces. Signed-off-by: Siddharth Vadapalli --- .../bindings/phy/ti,phy-gmii-sel.yaml | 52 ++++++++++++++++--- 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/D= ocumentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml index da7cac537e15..1e19efab018b 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml @@ -54,6 +54,7 @@ properties: - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel =20 reg: maxItems: 1 @@ -65,12 +66,19 @@ properties: description: | Required only for QSGMII mode. Array to select the port for QSGMII main mode. Rest of the ports are selected as QSGMII_SUB - ports automatically. Any one of the 4 CPSW5G ports can act as the - main port with the rest of them being the QSGMII_SUB ports. - maxItems: 1 - items: - minimum: 1 - maximum: 4 + ports automatically. For J7200 CPSW5G with the compatible: + ti,j7200-cpsw5g-phy-gmii-sel, ti,qsgmii-main-ports is an + array of only one element, which is the port number ranging from + 1 to 4. For J721e CPSW9G with the compatible: + ti,j721e-cpsw9g-phy-gmii-sel, ti,qsgmii-main-ports is an array + of two elements, which corresponds to two potential QSGMII main + ports. The first element and second element of the array can both + range from 1 to 8 each, corresponding to two QSGMII main ports. + For J721e CPSW9G, to configure port 2 as the first QSGMII main + port and port 7 as the second QSGMII main port, we specify: + ti,qsgmii-main-ports =3D <2>, <7>; + If only one QSGMII main port is desired, mention the same main + port twice. =20 allOf: - if: @@ -81,12 +89,43 @@ allOf: - ti,dra7xx-phy-gmii-sel - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel + - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel then: properties: '#phy-cells': const: 1 description: CPSW port number (starting from 1) =20 + - if: + properties: + compatible: + contains: + enum: + - ti,j7200-cpsw5g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: + maxItems: 1 + items: + minimum: 1 + maximum: 4 + + - if: + properties: + compatible: + contains: + enum: + - ti,j721e-cpsw9g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: + minItems: 2 + maxItems: 2 + items: + minimum: 1 + maximum: 8 + - if: not: properties: @@ -94,6 +133,7 @@ allOf: contains: enum: - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel then: properties: ti,qsgmii-main-ports: false --=20 2.25.1 From nobody Fri Apr 3 08:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A30FECAAD3 for ; Wed, 14 Sep 2022 09:40:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230488AbiINJkX (ORCPT ); Wed, 14 Sep 2022 05:40:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230370AbiINJj7 (ORCPT ); Wed, 14 Sep 2022 05:39:59 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 002CBEB3; Wed, 14 Sep 2022 02:39:45 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dQXg098677; Wed, 14 Sep 2022 04:39:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663148366; bh=IAIDS6zZRvqjsEEOsbFFjeDVR1Bx8cSXOYtHR8E1teA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=v22Fqjr6EPJwcx/34DmT+6Op9c/GhhDYLei1cSytdUijx5RodGrlKkgybdBaN6Scy 34HMibKvz8mLWPR4k4nc2C4my4ezTYzbZV9bkLCeM0dOQH5W1wA8CvY0iQQ15//9PP C4QNSecucGut/aa/KOVG41u4+O0+avMe2zTg/RZI= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28E9dQom063795 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Sep 2022 04:39:26 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 14 Sep 2022 04:39:26 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 14 Sep 2022 04:39:26 -0500 Received: from uda0492258.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dBHF111966; Wed, 14 Sep 2022 04:39:21 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 2/6] phy: ti: gmii-sel: Add support for configuring CPSW5G ports in SGMII mode Date: Wed, 14 Sep 2022 15:09:07 +0530 Message-ID: <20220914093911.187764-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914093911.187764-1-s-vadapalli@ti.com> References: <20220914093911.187764-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CPSW5G ports on J7200 support SGMII mode. Add support to the phy-gmii-sel driver to configure the CPSW5G ports in SGMII mode. Signed-off-by: Siddharth Vadapalli --- drivers/phy/ti/phy-gmii-sel.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index 0bcfd6d96b4d..f0b2ba7a9c96 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -23,6 +23,7 @@ #define AM33XX_GMII_SEL_MODE_RGMII 2 =20 /* J72xx SoC specific definitions for the CONTROL port */ +#define J72XX_GMII_SEL_MODE_SGMII 3 #define J72XX_GMII_SEL_MODE_QSGMII 4 #define J72XX_GMII_SEL_MODE_QSGMII_SUB 6 =20 @@ -105,6 +106,13 @@ static int phy_gmii_sel_mode(struct phy *phy, enum phy= _mode mode, int submode) gmii_sel_mode =3D J72XX_GMII_SEL_MODE_QSGMII_SUB; break; =20 + case PHY_INTERFACE_MODE_SGMII: + if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII))) + goto unsupported; + else + gmii_sel_mode =3D J72XX_GMII_SEL_MODE_SGMII; + break; + default: goto unsupported; } @@ -212,7 +220,7 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 =3D { .use_of_data =3D true, .regfields =3D phy_gmii_sel_fields_am654, - .extra_modes =3D BIT(PHY_INTERFACE_MODE_QSGMII), + .extra_modes =3D BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_= SGMII), }; =20 static const struct of_device_id phy_gmii_sel_id_table[] =3D { --=20 2.25.1 From nobody Fri Apr 3 08:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED5DFECAAD3 for ; Wed, 14 Sep 2022 09:40:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229993AbiINJkS (ORCPT ); Wed, 14 Sep 2022 05:40:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230488AbiINJj7 (ORCPT ); Wed, 14 Sep 2022 05:39:59 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 001CED67; Wed, 14 Sep 2022 02:39:46 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dVAj113545; Wed, 14 Sep 2022 04:39:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663148371; bh=Nu+6daNznh/b8uWXgMlJJ6knNdhWjxmmybMsKI7CSv8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DjQ6EkTWoYyIvajgqjdhoBr1nROL/OcxubFb26EKXllLDHTAL0kLHZ/rRBcf2uD2T Y46WjULT8umjseZZfNruEW3ExnQ9oDtXM/6yV7Pb6Xt0FNlrthzMqqyglTk+PC2ell GteDT1uux/wOZsiAh7ZZGiUkFrs2zNHRVMmB/k64= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28E9dVQT014825 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Sep 2022 04:39:31 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 14 Sep 2022 04:39:30 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 14 Sep 2022 04:39:30 -0500 Received: from uda0492258.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dBHG111966; Wed, 14 Sep 2022 04:39:26 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 3/6] phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e Date: Wed, 14 Sep 2022 15:09:08 +0530 Message-ID: <20220914093911.187764-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914093911.187764-1-s-vadapalli@ti.com> References: <20220914093911.187764-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Each of the CPSW9G ports in J721e support additional modes like QSGMII. Add a new compatible for J721e to support the additional modes. In TI's J721e, each of the CPSW9G ethernet interfaces can act as a QSGMII main or QSGMII-SUB port. The QSGMII main interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. Signed-off-by: Siddharth Vadapalli --- drivers/phy/ti/phy-gmii-sel.c | 47 +++++++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index f0b2ba7a9c96..fdb1a7db123d 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -223,6 +223,13 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j= 7200 =3D { .extra_modes =3D BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_= SGMII), }; =20 +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e =3D { + .use_of_data =3D true, + .regfields =3D phy_gmii_sel_fields_am654, + .extra_modes =3D BIT(PHY_INTERFACE_MODE_QSGMII), +}; + static const struct of_device_id phy_gmii_sel_id_table[] =3D { { .compatible =3D "ti,am3352-phy-gmii-sel", @@ -248,6 +255,10 @@ static const struct of_device_id phy_gmii_sel_id_table= [] =3D { .compatible =3D "ti,j7200-cpsw5g-phy-gmii-sel", .data =3D &phy_gmii_sel_cpsw5g_soc_j7200, }, + { + .compatible =3D "ti,j721e-cpsw9g-phy-gmii-sel", + .data =3D &phy_gmii_sel_cpsw9g_soc_j721e, + }, {} }; MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); @@ -389,7 +400,7 @@ static int phy_gmii_sel_probe(struct platform_device *p= dev) struct device_node *node =3D dev->of_node; const struct of_device_id *of_id; struct phy_gmii_sel_priv *priv; - u32 main_ports =3D 1; + u32 main_ports[2] =3D {1, 1}; int ret; =20 of_id =3D of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node); @@ -403,15 +414,31 @@ static int phy_gmii_sel_probe(struct platform_device = *pdev) priv->dev =3D &pdev->dev; priv->soc_data =3D of_id->data; priv->num_ports =3D priv->soc_data->num_ports; - of_property_read_u32(node, "ti,qsgmii-main-ports", &main_ports); - /* - * Ensure that main_ports is within bounds. If the property - * ti,qsgmii-main-ports is not mentioned, or the value mentioned - * is out of bounds, default to 1. - */ - if (main_ports < 1 || main_ports > 4) - main_ports =3D 1; - priv->qsgmii_main_ports =3D PHY_GMII_PORT(main_ports); + /* Differentiate between J7200 CPSW5G and J721e CPSW9G */ + if (of_device_is_compatible(node, "ti,j7200-cpsw5g-phy-gmii-sel") > 0) { + of_property_read_u32(node, "ti,qsgmii-main-ports", &main_ports[0]); + /* + * Ensure that main_ports is within bounds. If the property + * ti,qsgmii-main-ports is not mentioned, or the value mentioned + * is out of bounds, default to 1. + */ + if (main_ports[0] < 1 || main_ports[0] > 4) + main_ports[0] =3D 1; + priv->qsgmii_main_ports =3D PHY_GMII_PORT(main_ports[0]); + } else if (of_device_is_compatible(node, "ti,j721e-cpsw9g-phy-gmii-sel") = > 0) { + of_property_read_u32_array(node, "ti,qsgmii-main-ports", &main_ports[0],= 2); + /* + * Ensure that main_ports is within bounds. If the property + * ti,qsgmii-main-ports is not mentioned, or the value mentioned + * is out of bounds, default to 1. + */ + if (main_ports[0] < 1 || main_ports[0] > 8) + main_ports[0] =3D 1; + if (main_ports[1] < 1 || main_ports[1] > 8) + main_ports[1] =3D 1; + priv->qsgmii_main_ports =3D PHY_GMII_PORT(main_ports[0]); + priv->qsgmii_main_ports |=3D PHY_GMII_PORT(main_ports[1]); + } =20 priv->regmap =3D syscon_node_to_regmap(node->parent); if (IS_ERR(priv->regmap)) { --=20 2.25.1 From nobody Fri Apr 3 08:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2DCAC6FA86 for ; Wed, 14 Sep 2022 09:40:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230219AbiINJkN (ORCPT ); Wed, 14 Sep 2022 05:40:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230367AbiINJj7 (ORCPT ); Wed, 14 Sep 2022 05:39:59 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A3F764CF; Wed, 14 Sep 2022 02:39:46 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28E9daCQ113555; Wed, 14 Sep 2022 04:39:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663148376; bh=a4apSB/h90T1k9vFmgSKZJoOZmYmdIpWcb2Sl9ZcIKg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hN+N2VXDbclewoQrAD4GOu37k4pi8KfhTVQSOJWLGmiPHb1J6mvsrgpdOh1rPFOQN CPJEP+s3CXINlrmIDB+6nT8emmARkS/XHV+njFt0YvppVA+OZ2khp/EF1ppdzYuixN i1+6bd4/Ekj3siTarrj43HvjT70YW4eWr++1/f90= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28E9dZIg119263 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Sep 2022 04:39:35 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 14 Sep 2022 04:39:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 14 Sep 2022 04:39:35 -0500 Received: from uda0492258.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dBHH111966; Wed, 14 Sep 2022 04:39:31 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 4/6] phy: ti: gmii-sel: Enable SGMII mode configuration for J721E Date: Wed, 14 Sep 2022 15:09:09 +0530 Message-ID: <20220914093911.187764-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914093911.187764-1-s-vadapalli@ti.com> References: <20220914093911.187764-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CPSW9G ports on J721E support SGMII mode. Add SGMII mode to the extra_modes member of struct "phy_gmii_sel_cpsw9g_soc_j721e". Signed-off-by: Siddharth Vadapalli --- drivers/phy/ti/phy-gmii-sel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index fdb1a7db123d..13877d0d15e4 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -227,7 +227,7 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e =3D { .use_of_data =3D true, .regfields =3D phy_gmii_sel_fields_am654, - .extra_modes =3D BIT(PHY_INTERFACE_MODE_QSGMII), + .extra_modes =3D BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_= SGMII), }; =20 static const struct of_device_id phy_gmii_sel_id_table[] =3D { --=20 2.25.1 From nobody Fri Apr 3 08:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 786DDECAAD8 for ; Wed, 14 Sep 2022 09:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229949AbiINJkn (ORCPT ); Wed, 14 Sep 2022 05:40:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229832AbiINJkE (ORCPT ); Wed, 14 Sep 2022 05:40:04 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EF741ADBE; Wed, 14 Sep 2022 02:39:50 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28E9deER073476; Wed, 14 Sep 2022 04:39:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663148380; bh=irLXL59E4mT6LrYt3YZ8LsCgwANIbUY0MO6/Z2yRp4M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DCZ6b7CvUAnKL/gymxoPBepTdO7zKaw+RUZGUvlOKvHCmc2f0bwXTmS8MmL/ANZTy +N7gzF1GXfsCztfLXz180wNrDRrRaiakgmabDMlCkRD6wWABsdqB5kQeRxlL8rYBl7 /bcd9G9omH5692uhH93hdPfzhbKPM7NhZxGl76ws= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28E9de4P014867 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Sep 2022 04:39:40 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 14 Sep 2022 04:39:40 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 14 Sep 2022 04:39:40 -0500 Received: from uda0492258.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dBHI111966; Wed, 14 Sep 2022 04:39:36 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 5/6] phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J721E Date: Wed, 14 Sep 2022 15:09:10 +0530 Message-ID: <20220914093911.187764-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914093911.187764-1-s-vadapalli@ti.com> References: <20220914093911.187764-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable full rate divider configuration support for J721E_WIZ_16G for SGMII. Signed-off-by: Siddharth Vadapalli --- drivers/phy/ti/phy-j721e-wiz.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 20af142580ad..9a33aebdcbe5 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -1191,6 +1191,7 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int la= ne) return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); break; case J721E_WIZ_10G: + case J721E_WIZ_16G: case J7200_WIZ_10G: if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_SGMII) return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); --=20 2.25.1 From nobody Fri Apr 3 08:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31208ECAAD3 for ; Wed, 14 Sep 2022 09:40:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231580AbiINJkb (ORCPT ); Wed, 14 Sep 2022 05:40:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231277AbiINJkB (ORCPT ); Wed, 14 Sep 2022 05:40:01 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A31E17E09; Wed, 14 Sep 2022 02:39:58 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28E9djTO113572; Wed, 14 Sep 2022 04:39:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1663148385; bh=oVGNjubgA1LuX49FyuBwm5DlshfpTfeRSSrz1PSeRUU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L+6xwiaW222+H0ApV1nLDa+7lwNK1h8mVPL+/lwde7okpPmwdYqK0G0oTssGARPWA I1WWo0oQ7hxple8hGpLBxpnk9nbiaNQSMItRqwTm7yVmTUyxN+91tqQ/kzQh6GRItI wi9CVgFH62G0yPJJthoYNscXxOMLQqVEby/xhiSY= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28E9djFh014883 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Sep 2022 04:39:45 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 14 Sep 2022 04:39:45 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 14 Sep 2022 04:39:45 -0500 Received: from uda0492258.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28E9dBHJ111966; Wed, 14 Sep 2022 04:39:40 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 6/6] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration Date: Wed, 14 Sep 2022 15:09:11 +0530 Message-ID: <20220914093911.187764-7-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914093911.187764-1-s-vadapalli@ti.com> References: <20220914093911.187764-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Swapnil Jakhade Add register sequences for PCIe + SGMII PHY multilink configuration. Signed-off-by: Swapnil Jakhade Signed-off-by: Siddharth Vadapalli --- drivers/phy/cadence/phy-cadence-sierra.c | 141 ++++++++++++++++++++++- 1 file changed, 139 insertions(+), 2 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence= /phy-cadence-sierra.c index 6e86a6517f37..7c0daf3e8880 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -24,7 +24,7 @@ #include =20 #define NUM_SSC_MODE 3 -#define NUM_PHY_TYPE 4 +#define NUM_PHY_TYPE 5 =20 /* PHY register offsets */ #define SIERRA_COMMON_CDB_OFFSET 0x0 @@ -46,7 +46,9 @@ #define SIERRA_CMN_REFRCV_PREG 0x98 #define SIERRA_CMN_REFRCV1_PREG 0xB8 #define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 +#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3 #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA +#define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0 #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2 =20 @@ -74,6 +76,7 @@ #define SIERRA_PSC_RX_A1_PREG 0x031 #define SIERRA_PSC_RX_A2_PREG 0x032 #define SIERRA_PSC_RX_A3_PREG 0x033 +#define SIERRA_PLLCTRL_FBDIV_MODE01_PREG 0x039 #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A #define SIERRA_PLLCTRL_GEN_A_PREG 0x03B #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E @@ -298,6 +301,7 @@ enum cdns_sierra_phy_type { TYPE_NONE, TYPE_PCIE, TYPE_USB, + TYPE_SGMII, TYPE_QSGMII }; =20 @@ -936,6 +940,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_= inst *inst, case PHY_TYPE_USB3: inst->phy_type =3D TYPE_USB; break; + case PHY_TYPE_SGMII: + inst->phy_type =3D TYPE_SGMII; + break; case PHY_TYPE_QSGMII: inst->phy_type =3D TYPE_QSGMII; break; @@ -1339,7 +1346,7 @@ static int cdns_sierra_phy_configure_multilink(struct= cdns_sierra_phy *sp) } } =20 - if (phy_t1 =3D=3D TYPE_QSGMII) + if (phy_t1 =3D=3D TYPE_SGMII || phy_t1 =3D=3D TYPE_QSGMII) reset_control_deassert(sp->phys[node].lnk_rst); } =20 @@ -1537,6 +1544,71 @@ static int cdns_sierra_phy_remove(struct platform_de= vice *pdev) return 0; } =20 +/* SGMII PHY PMA lane configuration */ +static struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] =3D { + {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} +}; + +static struct cdns_sierra_vals sgmii_phy_pma_ln_vals =3D { + .reg_pairs =3D sgmii_phy_pma_ln_regs, + .num_regs =3D ARRAY_SIZE(sgmii_phy_pma_ln_regs), +}; + +/* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */ +static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[]= =3D { + {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG}, + {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, + {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG}, + {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, + {0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} +}; + +static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = =3D { + {0x688E, SIERRA_DET_STANDEC_D_PREG}, + {0x0004, SIERRA_PSC_LN_IDLE_PREG}, + {0x0FFE, SIERRA_PSC_RX_A0_PREG}, + {0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG}, + {0x0013, SIERRA_PLLCTRL_SUBRATE_PREG}, + {0x0003, SIERRA_PLLCTRL_GEN_A_PREG}, + {0x0106, SIERRA_PLLCTRL_GEN_D_PREG}, + {0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG }, + {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, + {0x9702, SIERRA_DRVCTRL_BOOST_PREG}, + {0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, + {0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG}, + {0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG}, + {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, + {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, + {0x0186, SIERRA_DEQ_GLUT0}, + {0x0186, SIERRA_DEQ_GLUT1}, + {0x0186, SIERRA_DEQ_GLUT2}, + {0x0186, SIERRA_DEQ_GLUT3}, + {0x0186, SIERRA_DEQ_GLUT4}, + {0x0861, SIERRA_DEQ_ALUT0}, + {0x07E0, SIERRA_DEQ_ALUT1}, + {0x079E, SIERRA_DEQ_ALUT2}, + {0x071D, SIERRA_DEQ_ALUT3}, + {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, + {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, + {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, + {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, + {0x0033, SIERRA_DEQ_PICTRL_PREG}, + {0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG}, + {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, + {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, + {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} +}; + +static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals =3D { + .reg_pairs =3D sgmii_100_no_ssc_plllc1_opt3_cmn_regs, + .num_regs =3D ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs), +}; + +static struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals =3D { + .reg_pairs =3D sgmii_100_no_ssc_plllc1_opt3_ln_regs, + .num_regs =3D ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs), +}; + /* QSGMII PHY PMA lane configuration */ static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] =3D { {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} @@ -2363,6 +2435,11 @@ static const struct cdns_sierra_data cdns_map_sierra= =3D { [EXTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, [INTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, }, + [TYPE_SGMII] =3D { + [NO_SSC] =3D &pcie_phy_pcs_cmn_vals, + [EXTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, + [INTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, + }, [TYPE_QSGMII] =3D { [NO_SSC] =3D &pcie_phy_pcs_cmn_vals, [EXTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, @@ -2377,6 +2454,11 @@ static const struct cdns_sierra_data cdns_map_sierra= =3D { [EXTERNAL_SSC] =3D &pcie_100_ext_ssc_cmn_vals, [INTERNAL_SSC] =3D &pcie_100_int_ssc_cmn_vals, }, + [TYPE_SGMII] =3D { + [NO_SSC] =3D &pcie_100_no_ssc_plllc_cmn_vals, + [EXTERNAL_SSC] =3D &pcie_100_ext_ssc_plllc_cmn_vals, + [INTERNAL_SSC] =3D &pcie_100_int_ssc_plllc_cmn_vals, + }, [TYPE_QSGMII] =3D { [NO_SSC] =3D &pcie_100_no_ssc_plllc_cmn_vals, [EXTERNAL_SSC] =3D &pcie_100_ext_ssc_plllc_cmn_vals, @@ -2388,6 +2470,13 @@ static const struct cdns_sierra_data cdns_map_sierra= =3D { [EXTERNAL_SSC] =3D &usb_100_ext_ssc_cmn_vals, }, }, + [TYPE_SGMII] =3D { + [TYPE_PCIE] =3D { + [NO_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, + [EXTERNAL_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, + [INTERNAL_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, + }, + }, [TYPE_QSGMII] =3D { [TYPE_PCIE] =3D { [NO_SSC] =3D &qsgmii_100_no_ssc_plllc1_cmn_vals, @@ -2403,6 +2492,11 @@ static const struct cdns_sierra_data cdns_map_sierra= =3D { [EXTERNAL_SSC] =3D &pcie_100_ext_ssc_ln_vals, [INTERNAL_SSC] =3D &pcie_100_int_ssc_ln_vals, }, + [TYPE_SGMII] =3D { + [NO_SSC] =3D &ml_pcie_100_no_ssc_ln_vals, + [EXTERNAL_SSC] =3D &ml_pcie_100_ext_ssc_ln_vals, + [INTERNAL_SSC] =3D &ml_pcie_100_int_ssc_ln_vals, + }, [TYPE_QSGMII] =3D { [NO_SSC] =3D &ml_pcie_100_no_ssc_ln_vals, [EXTERNAL_SSC] =3D &ml_pcie_100_ext_ssc_ln_vals, @@ -2414,6 +2508,13 @@ static const struct cdns_sierra_data cdns_map_sierra= =3D { [EXTERNAL_SSC] =3D &usb_100_ext_ssc_ln_vals, }, }, + [TYPE_SGMII] =3D { + [TYPE_PCIE] =3D { + [NO_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_ln_vals, + [EXTERNAL_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_ln_vals, + [INTERNAL_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_ln_vals, + }, + }, [TYPE_QSGMII] =3D { [TYPE_PCIE] =3D { [NO_SSC] =3D &qsgmii_100_no_ssc_plllc1_ln_vals, @@ -2435,6 +2536,11 @@ static const struct cdns_sierra_data cdns_ti_map_sie= rra =3D { [EXTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, [INTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, }, + [TYPE_SGMII] =3D { + [NO_SSC] =3D &pcie_phy_pcs_cmn_vals, + [EXTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, + [INTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, + }, [TYPE_QSGMII] =3D { [NO_SSC] =3D &pcie_phy_pcs_cmn_vals, [EXTERNAL_SSC] =3D &pcie_phy_pcs_cmn_vals, @@ -2443,6 +2549,13 @@ static const struct cdns_sierra_data cdns_ti_map_sie= rra =3D { }, }, .phy_pma_ln_vals =3D { + [TYPE_SGMII] =3D { + [TYPE_PCIE] =3D { + [NO_SSC] =3D &sgmii_phy_pma_ln_vals, + [EXTERNAL_SSC] =3D &sgmii_phy_pma_ln_vals, + [INTERNAL_SSC] =3D &sgmii_phy_pma_ln_vals, + }, + }, [TYPE_QSGMII] =3D { [TYPE_PCIE] =3D { [NO_SSC] =3D &qsgmii_phy_pma_ln_vals, @@ -2458,6 +2571,11 @@ static const struct cdns_sierra_data cdns_ti_map_sie= rra =3D { [EXTERNAL_SSC] =3D &pcie_100_ext_ssc_cmn_vals, [INTERNAL_SSC] =3D &pcie_100_int_ssc_cmn_vals, }, + [TYPE_SGMII] =3D { + [NO_SSC] =3D &pcie_100_no_ssc_plllc_cmn_vals, + [EXTERNAL_SSC] =3D &pcie_100_ext_ssc_plllc_cmn_vals, + [INTERNAL_SSC] =3D &pcie_100_int_ssc_plllc_cmn_vals, + }, [TYPE_QSGMII] =3D { [NO_SSC] =3D &pcie_100_no_ssc_plllc_cmn_vals, [EXTERNAL_SSC] =3D &pcie_100_ext_ssc_plllc_cmn_vals, @@ -2469,6 +2587,13 @@ static const struct cdns_sierra_data cdns_ti_map_sie= rra =3D { [EXTERNAL_SSC] =3D &usb_100_ext_ssc_cmn_vals, }, }, + [TYPE_SGMII] =3D { + [TYPE_PCIE] =3D { + [NO_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, + [EXTERNAL_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, + [INTERNAL_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, + }, + }, [TYPE_QSGMII] =3D { [TYPE_PCIE] =3D { [NO_SSC] =3D &qsgmii_100_no_ssc_plllc1_cmn_vals, @@ -2484,6 +2609,11 @@ static const struct cdns_sierra_data cdns_ti_map_sie= rra =3D { [EXTERNAL_SSC] =3D &pcie_100_ext_ssc_ln_vals, [INTERNAL_SSC] =3D &pcie_100_int_ssc_ln_vals, }, + [TYPE_SGMII] =3D { + [NO_SSC] =3D &ti_ml_pcie_100_no_ssc_ln_vals, + [EXTERNAL_SSC] =3D &ti_ml_pcie_100_ext_ssc_ln_vals, + [INTERNAL_SSC] =3D &ti_ml_pcie_100_int_ssc_ln_vals, + }, [TYPE_QSGMII] =3D { [NO_SSC] =3D &ti_ml_pcie_100_no_ssc_ln_vals, [EXTERNAL_SSC] =3D &ti_ml_pcie_100_ext_ssc_ln_vals, @@ -2495,6 +2625,13 @@ static const struct cdns_sierra_data cdns_ti_map_sie= rra =3D { [EXTERNAL_SSC] =3D &usb_100_ext_ssc_ln_vals, }, }, + [TYPE_SGMII] =3D { + [TYPE_PCIE] =3D { + [NO_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_ln_vals, + [EXTERNAL_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_ln_vals, + [INTERNAL_SSC] =3D &sgmii_100_no_ssc_plllc1_opt3_ln_vals, + }, + }, [TYPE_QSGMII] =3D { [TYPE_PCIE] =3D { [NO_SSC] =3D &qsgmii_100_no_ssc_plllc1_ln_vals, --=20 2.25.1