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Tue, 13 Sep 2022 08:53:13 -0700 From: Akhil R To: , , , , , , , CC: Subject: [PATCH 1/3] dt-bindings: dmaengine: Add dma-channel-mask to Tegra GPCDMA Date: Tue, 13 Sep 2022 21:22:49 +0530 Message-ID: <20220913155251.59375-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913155251.59375-1-akhilrajeev@nvidia.com> References: <20220913155251.59375-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT029:EE_|DM6PR12MB4283:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ee8e161-9d23-4fe0-74ff-08da95a0133e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WIArLFGC+WXtK/T6+jncOvm4zQRdija8kdac93MbgBQwyaHG0i/jWpXh5cPEsDhfuwmITIgtx09NnS+OavBkDcJaCNgocVS92Sa2kBimET2MMmEXUAZqeHW8K9vKcaqUZfkSteMaW7RET9GPk/NOSdFX1aRJC0A+IPFpsSO54+Ome3VpX0Ak4X1mfmEGJ4rTfPeRdhKxb1dQRka4Usse7O5bnxO7SByehyV1pRm0SQ1pRjfa7QwPLmy9yiIfRdqvsJaFI6BnrBrvRb4Sd2nPOl/OQrDCOiJO8Wwrhb26R0aPNeILHcD8jgu91AIdKLw4sHB+QihEpyoAGBvdSk/UQar0eiNSD7wA9MhHsYl4CBF4kcg6taW4XQIe4n526cQxnl8INbGJdnNAwRImRzjLxqnlUa9LBwieaxL+lgwhemLAJ2cp5fdjfuJYvMEcHgjc8Ixhb9I5QiMzzT2vyaJbhFEAPXwzyAaEGrTeMr3K3+66ObXVtrz3IYqXMiXwH20V2HovJW5c6mZv5BEQPtfKrQuisCWshZNk2jCHUCyLXUASUGFAOhIjWMhb1IXccP07SInQ7+s+GxM20IEv4B4Oskqz4bXEFwDEaO6VYfdfsHl4WfOTxUyD9Osf38Cx0XevUQMXlSQjC29tlP/yYVVt49vYr3v325FIZUgfMV65W0MMU7qEgFd3QJIki3Aya8k1HZEbZv8Yk3ks1aCTBLYoIzcki9PvmJg6UN7LxmNJAytTKBUaXHgfxNjfb4xKRELZemBVaHFwj85iXIdU0ZMXavlz1l603B0iBWi/zvBUG3MAjWTkrRQdtLa7bw+wL98t X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(346002)(136003)(376002)(451199015)(46966006)(40470700004)(36840700001)(82740400003)(47076005)(6666004)(110136005)(186003)(83380400001)(4326008)(426003)(40460700003)(82310400005)(40480700001)(86362001)(356005)(8676002)(2616005)(36756003)(41300700001)(8936002)(36860700001)(70586007)(5660300002)(81166007)(1076003)(70206006)(478600001)(336012)(7696005)(107886003)(316002)(26005)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2022 15:53:17.4637 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ee8e161-9d23-4fe0-74ff-08da95a0133e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4283 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dma-channel-mask property in Tegra GPCDMA document. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. Now since we can list all 32 channels, update the interrupts property as well to list all 32 interrupts. Signed-off-by: Akhil R Acked-by: Thierry Reding --- .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.= yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 7e575296df0c..31724cda074e 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -39,7 +39,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 31 + maxItems: 32 =20 resets: maxItems: 1 @@ -52,6 +52,9 @@ properties: =20 dma-coherent: true =20 + dma-channel-mask: + maxItems: 1 + required: - compatible - reg @@ -60,6 +63,7 @@ required: - reset-names - "#dma-cells" - iommus + - dma-channel-mask =20 additionalProperties: false =20 @@ -108,5 +112,6 @@ examples: #dma-cells =3D <1>; iommus =3D <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask =3D <0xfffffffe>; }; ... --=20 2.17.1