From nobody Fri Dec 19 07:48:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18A4DC6FA82 for ; Tue, 13 Sep 2022 14:21:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233411AbiIMOV2 (ORCPT ); Tue, 13 Sep 2022 10:21:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233387AbiIMOSz (ORCPT ); Tue, 13 Sep 2022 10:18:55 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA771422DB; Tue, 13 Sep 2022 07:13:38 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 23E0C614AD; Tue, 13 Sep 2022 14:13:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 301D6C433C1; Tue, 13 Sep 2022 14:13:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1663078417; bh=7B95i/Mb08UkbcQ6VvPgvAfVgeCIGs4fxEhdVSLHigs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kgvDnNFW6LXmidcmoUTqUgsBMibcedrhVNcOXXT8CR7DXSAWtFqioOGrcG+84REOv L+RPK1UZ3FqixQMB+M+R8pVmXgd1v0OEyRBl6EyEVtjdbKa8samC3vt/gFGB3gmEmZ mACuUTW1CkKmozevPE3CtRr6LkTXSquzwi6ukWsQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Heinrich Schuchardt , Conor Dooley , Sasha Levin Subject: [PATCH 5.19 105/192] riscv: dts: microchip: use an mpfs specific l2 compatible Date: Tue, 13 Sep 2022 16:03:31 +0200 Message-Id: <20220913140415.200343560@linuxfoundation.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220913140410.043243217@linuxfoundation.org> References: <20220913140410.043243217@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley [ Upstream commit 0dec364ffeb6149aae572ded1e34d4b444c23be6 ] PolarFire SoC does not have the same l2 cache controller as the fu540, featuring an extra interrupt. Appease the devicetree checker overlords by adding a PolarFire SoC specific compatible to fix the below sort of warnings: mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], = [2]] is too long Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts") Reviewed-by: Heinrich Schuchardt Signed-off-by: Conor Dooley Signed-off-by: Sasha Levin --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 9f5bce1488d93..9bf37ef379509 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -161,7 +161,7 @@ ranges; =20 cctrllr: cache-controller@2010000 { - compatible =3D "sifive,fu540-c000-ccache", "cache"; + compatible =3D "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "ca= che"; reg =3D <0x0 0x2010000 0x0 0x1000>; cache-block-size =3D <64>; cache-level =3D <2>; --=20 2.35.1