From nobody Fri Dec 19 07:47:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88488C54EE9 for ; Tue, 13 Sep 2022 14:11:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232813AbiIMOLO (ORCPT ); Tue, 13 Sep 2022 10:11:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232726AbiIMOKC (ORCPT ); Tue, 13 Sep 2022 10:10:02 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E7A85C34E; Tue, 13 Sep 2022 07:09:16 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5AD9BB80EF7; Tue, 13 Sep 2022 14:09:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 93F48C433B5; Tue, 13 Sep 2022 14:09:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1663078154; bh=5MbtQP/uBiDAzlP/MQTmHh2C6T6vAfc4ERxjYaKaQWE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bd3yUG2AwERPGIWnSclOg0LflHzEYJjowe4bp0iydmrVFdu6u+gwM6q/4wTYs+19k XmFfUrEZFbz57WYsf7CDNnOAfv8r+zJTqzW8JpHF4ybdpQk8dZkzOqpa1eAICMmWlf 31MMuTOnsqaSpiv6FH0BGNK9i8C5UEcNyxFUG9M8= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Tim Huang , Yifan Zhang , Alex Deucher , Sasha Levin Subject: [PATCH 5.19 033/192] drm/amdgpu: add sdma instance check for gfx11 CGCG Date: Tue, 13 Sep 2022 16:02:19 +0200 Message-Id: <20220913140411.566794110@linuxfoundation.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220913140410.043243217@linuxfoundation.org> References: <20220913140410.043243217@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tim Huang [ Upstream commit 00047c3d967d7ef8adf8bac3c3579294a3bc0bb1 ] For some ASICs, like GFX IP v11.0.1, only have one SDMA instance, so not need to configure SDMA1_RLC_CGCG_CTRL for this case. Signed-off-by: Tim Huang Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v11_0.c index a4a6751b1e449..30998ac47707c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -5090,9 +5090,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gati= ng(struct amdgpu_device *ade data =3D REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); =20 - data =3D RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); - data =3D REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); - WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); + /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ + if (adev->sdma.num_instances > 1) { + data =3D RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); + data =3D REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1); + WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); + } } else { /* Program RLC_CGCG_CGLS_CTRL */ def =3D data =3D RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); @@ -5121,9 +5124,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gati= ng(struct amdgpu_device *ade data &=3D ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); =20 - data =3D RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); - data &=3D ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; - WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); + /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */ + if (adev->sdma.num_instances > 1) { + data =3D RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); + data &=3D ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; + WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); + } } } =20 --=20 2.35.1