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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id z11-20020a170902cccb00b00173cfaed233sm7296332ple.62.2022.09.12.23.18.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:18:26 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v5 1/7] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Date: Tue, 13 Sep 2022 06:18:11 +0000 Message-Id: <20220913061817.22564-2-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com> References: <20220913061817.22564-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li Suggested-by: Conor Dooley Suggested-by: Ben Dooks Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- ...five-l2-cache.yaml =3D> sifive,ccache0.yaml} | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml =3D> = sifive,ccache0.yaml} (83%) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b= /Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml similarity index 83% rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index ca3b9be58058..bf3f07421f7e 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -2,18 +2,18 @@ # Copyright (C) 2020 SiFive, Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: SiFive L2 Cache Controller +title: SiFive Composable Cache Controller =20 maintainers: - Sagar Kadam - Paul Walmsley =20 description: - The SiFive Level 2 Cache Controller is used to provide access to fast co= pies - of memory for masters in a Core Complex. The Level 2 Cache Controller al= so + The SiFive Composable Cache Controller is used to provide access to fast= copies + of memory for masters in a Core Complex. The Composable Cache Controller= also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this pl= atform. =20 @@ -22,6 +22,7 @@ select: compatible: contains: enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache =20 @@ -33,6 +34,7 @@ properties: oneOf: - items: - enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache - const: cache @@ -45,7 +47,7 @@ properties: const: 64 =20 cache-level: - const: 2 + enum: [2, 3] =20 cache-sets: enum: [1024, 2048] @@ -115,6 +117,22 @@ allOf: cache-sets: const: 1024 =20 + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + additionalProperties: false =20 required: --=20 2.17.1 From nobody Mon Apr 6 00:29:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEDEEC6FA82 for ; Tue, 13 Sep 2022 06:19:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230280AbiIMGSn (ORCPT ); Tue, 13 Sep 2022 02:18:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230213AbiIMGSb (ORCPT ); Tue, 13 Sep 2022 02:18:31 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E30456BA4 for ; Mon, 12 Sep 2022 23:18:30 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id x1so10789298plv.5 for ; Mon, 12 Sep 2022 23:18:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=5SuaG6Ukq0CemB7A8qUbJlhfLaxFef4FQZrGHxKHG2c=; b=BxnwPf+fpcuUeoMOBFiIVF6GHPwR8N7wtmhjkzuwd7S85bMbwBTG04SyBwGazBpOhm UIBnJYNyO9BSMWCfUhGqzBZ80JRPT0UtNPOB5Gekgqw+/iskn9MtKSBwqWX30ZmFVj61 brbnf1r0JJj5DXBT3nyyySMJG6q2a8fbiqwz8U4ksoJRvQvYAwbd1v/sRCw0kaRbpbwT SrWujwSh9rvHxtEwv2jJSWS3eXcRt/icUylIx99blrpFCA2uVuWeYmRkTrOtPQExCdUt +oNiLSXbOYy2EjDouY3rfg+miWdcuTX4fUvlT5s/0YZ7mLfVlrZQWPjBSWBE/EgCJHFN zmBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=5SuaG6Ukq0CemB7A8qUbJlhfLaxFef4FQZrGHxKHG2c=; b=AA5XDTbLwjx9SxB1lCcxxTChJYeBsSX+DPoRC9NSFvymOoskuUeEBC8ApzDc7XKLPx oUREhhQKDbcdDFWN2CvANssh7076bK8xoI9cGUAOSGoSDfnejv8q9mnjWuBg+goabFEr s5lWM6W5UExzklZsi9O3viI2swO7f92epEUI8POsCAhJx6BTDBzjSalKRmqwKna5IOVu ME3V/wnKVLNnMrhbtRl5acD7yNE4C2RsizHtKeMHK4K1YsmrsybWiqWRiSQ/Uv79Nc0X uneOdV2VCyxhgiTLnb4CcP7YCVqhbVQpWZx9W+ZQqS5HwZRSzPwWZ1kLbQEcgOKo73RP zDYw== X-Gm-Message-State: ACgBeo0TBkpiEoYI8irsXX0ukjmBtdcw8i3wVNvyQzPEUQTdmAyBZkOK dFUyYveyRG+UGZC1sGaS3w+Paw== X-Google-Smtp-Source: AA6agR6OlwHyk8FJs7XtdkGIwg05Lw3uAr7G0cfBqHKHB1V/b4v5zp7wXLbOrI85NU3c9iRG2Os2LQ== X-Received: by 2002:a17:90b:4d12:b0:202:f027:557e with SMTP id mw18-20020a17090b4d1200b00202f027557emr2339267pjb.1.1663049910178; Mon, 12 Sep 2022 23:18:30 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id z11-20020a170902cccb00b00173cfaed233sm7296332ple.62.2022.09.12.23.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:18:29 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v5 2/7] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. Date: Tue, 13 Sep 2022 06:18:12 +0000 Message-Id: <20220913061817.22564-3-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com> References: <20220913061817.22564-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Greentime Hu Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu Signed-off-by: Zong Li Co-developed-by: Zong Li Reviewed-by: Conor Dooley --- drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 12 +- drivers/soc/sifive/Kconfig | 6 +- drivers/soc/sifive/Makefile | 2 +- .../{sifive_l2_cache.c =3D> sifive_ccache.c} | 174 +++++++++--------- .../{sifive_l2_cache.h =3D> sifive_ccache.h} | 16 +- 6 files changed, 110 insertions(+), 102 deletions(-) rename drivers/soc/sifive/{sifive_l2_cache.c =3D> sifive_ccache.c} (34%) rename include/soc/sifive/{sifive_l2_cache.h =3D> sifive_ccache.h} (12%) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 17562cf1fe97..456602d373b7 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC =20 config EDAC_SIFIVE bool "Sifive platform EDAC driver" - depends on EDAC=3Dy && SIFIVE_L2 + depends on EDAC=3Dy && SIFIVE_CCACHE help Support for error detection and correction on the SiFive SoCs. =20 diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c index ee800aec7d47..b844e2626fd5 100644 --- a/drivers/edac/sifive_edac.c +++ b/drivers/edac/sifive_edac.c @@ -2,7 +2,7 @@ /* * SiFive Platform EDAC Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * * This driver is partially based on octeon_edac-pc.c * @@ -10,7 +10,7 @@ #include #include #include "edac_module.h" -#include +#include =20 #define DRVNAME "sifive_edac" =20 @@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned l= ong event, void *ptr) =20 p =3D container_of(this, struct sifive_edac_priv, notifier); =20 - if (event =3D=3D SIFIVE_L2_ERR_TYPE_UE) + if (event =3D=3D SIFIVE_CCACHE_ERR_TYPE_UE) edac_device_handle_ue(p->dci, 0, 0, msg); - else if (event =3D=3D SIFIVE_L2_ERR_TYPE_CE) + else if (event =3D=3D SIFIVE_CCACHE_ERR_TYPE_CE) edac_device_handle_ce(p->dci, 0, 0, msg); =20 return NOTIFY_OK; @@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev) goto err; } =20 - register_sifive_l2_error_notifier(&p->notifier); + register_sifive_ccache_error_notifier(&p->notifier); =20 return 0; =20 @@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev) { struct sifive_edac_priv *p =3D platform_get_drvdata(pdev); =20 - unregister_sifive_l2_error_notifier(&p->notifier); + unregister_sifive_ccache_error_notifier(&p->notifier); edac_device_del_device(&pdev->dev); edac_device_free_ctl_info(p->dci); =20 diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index 58cf8c40d08d..ed4c571f8771 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -2,9 +2,9 @@ =20 if SOC_SIFIVE =20 -config SIFIVE_L2 - bool "Sifive L2 Cache controller" +config SIFIVE_CCACHE + bool "Sifive Composable Cache controller" help - Support for the L2 cache controller on SiFive platforms. + Support for the composable cache controller on SiFive platforms. =20 endif diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile index b5caff77938f..1f5dc339bf82 100644 --- a/drivers/soc/sifive/Makefile +++ b/drivers/soc/sifive/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 =20 -obj-$(CONFIG_SIFIVE_L2) +=3D sifive_l2_cache.o +obj-$(CONFIG_SIFIVE_CCACHE) +=3D sifive_ccache.o diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifi= ve_ccache.c similarity index 34% rename from drivers/soc/sifive/sifive_l2_cache.c rename to drivers/soc/sifive/sifive_ccache.c index 59640a1d0b28..949b824e89ad 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * SiFive L2 cache controller Driver + * SiFive composable cache controller Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * */ #include @@ -11,33 +11,33 @@ #include #include #include -#include +#include =20 -#define SIFIVE_L2_DIRECCFIX_LOW 0x100 -#define SIFIVE_L2_DIRECCFIX_HIGH 0x104 -#define SIFIVE_L2_DIRECCFIX_COUNT 0x108 +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 =20 -#define SIFIVE_L2_DIRECCFAIL_LOW 0x120 -#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124 -#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128 +#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120 +#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124 +#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128 =20 -#define SIFIVE_L2_DATECCFIX_LOW 0x140 -#define SIFIVE_L2_DATECCFIX_HIGH 0x144 -#define SIFIVE_L2_DATECCFIX_COUNT 0x148 +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 =20 -#define SIFIVE_L2_DATECCFAIL_LOW 0x160 -#define SIFIVE_L2_DATECCFAIL_HIGH 0x164 -#define SIFIVE_L2_DATECCFAIL_COUNT 0x168 +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 =20 -#define SIFIVE_L2_CONFIG 0x00 -#define SIFIVE_L2_WAYENABLE 0x08 -#define SIFIVE_L2_ECCINJECTERR 0x40 +#define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_WAYENABLE 0x08 +#define SIFIVE_CCACHE_ECCINJECTERR 0x40 =20 -#define SIFIVE_L2_MAX_ECCINTR 4 +#define SIFIVE_CCACHE_MAX_ECCINTR 4 =20 -static void __iomem *l2_base; -static int g_irq[SIFIVE_L2_MAX_ECCINTR]; -static struct riscv_cacheinfo_ops l2_cache_ops; +static void __iomem *ccache_base; +static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops ccache_cache_ops; =20 enum { DIR_CORR =3D 0, @@ -49,83 +49,84 @@ enum { #ifdef CONFIG_DEBUG_FS static struct dentry *sifive_test; =20 -static ssize_t l2_write(struct file *file, const char __user *data, - size_t count, loff_t *ppos) +static ssize_t ccache_write(struct file *file, const char __user *data, + size_t count, loff_t *ppos) { unsigned int val; =20 if (kstrtouint_from_user(data, count, 0, &val)) return -EINVAL; if ((val < 0xFF) || (val >=3D 0x10000 && val < 0x100FF)) - writel(val, l2_base + SIFIVE_L2_ECCINJECTERR); + writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); else return -EINVAL; return count; } =20 -static const struct file_operations l2_fops =3D { +static const struct file_operations ccache_fops =3D { .owner =3D THIS_MODULE, .open =3D simple_open, - .write =3D l2_write + .write =3D ccache_write }; =20 static void setup_sifive_debug(void) { - sifive_test =3D debugfs_create_dir("sifive_l2_cache", NULL); + sifive_test =3D debugfs_create_dir("sifive_ccache_cache", NULL); =20 debugfs_create_file("sifive_debug_inject_error", 0200, - sifive_test, NULL, &l2_fops); + sifive_test, NULL, &ccache_fops); } #endif =20 -static void l2_config_read(void) +static void ccache_config_read(void) { u32 regval, val; =20 - regval =3D readl(l2_base + SIFIVE_L2_CONFIG); + regval =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG); val =3D regval & 0xFF; - pr_info("L2CACHE: No. of Banks in the cache: %d\n", val); + pr_info("CCACHE: No. of Banks in the cache: %d\n", val); val =3D (regval & 0xFF00) >> 8; - pr_info("L2CACHE: No. of ways per bank: %d\n", val); + pr_info("CCACHE: No. of ways per bank: %d\n", val); val =3D (regval & 0xFF0000) >> 16; - pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val); + pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); val =3D (regval & 0xFF000000) >> 24; - pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); + pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); =20 - regval =3D readl(l2_base + SIFIVE_L2_WAYENABLE); - pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval); + regval =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); } =20 -static const struct of_device_id sifive_l2_ids[] =3D { +static const struct of_device_id sifive_ccache_ids[] =3D { { .compatible =3D "sifive,fu540-c000-ccache" }, { .compatible =3D "sifive,fu740-c000-ccache" }, - { /* end of table */ }, + { .compatible =3D "sifive,ccache0" }, + { /* end of table */ } }; =20 -static ATOMIC_NOTIFIER_HEAD(l2_err_chain); +static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); =20 -int register_sifive_l2_error_notifier(struct notifier_block *nb) +int register_sifive_ccache_error_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_register(&l2_err_chain, nb); + return atomic_notifier_chain_register(&ccache_err_chain, nb); } -EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier); +EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); =20 -int unregister_sifive_l2_error_notifier(struct notifier_block *nb) +int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_unregister(&l2_err_chain, nb); + return atomic_notifier_chain_unregister(&ccache_err_chain, nb); } -EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); =20 -static int l2_largest_wayenabled(void) +static int ccache_largest_wayenabled(void) { - return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF; + return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; } =20 static ssize_t number_of_ways_enabled_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%u\n", l2_largest_wayenabled()); + return sprintf(buf, "%u\n", ccache_largest_wayenabled()); } =20 static DEVICE_ATTR_RO(number_of_ways_enabled); @@ -139,99 +140,106 @@ static const struct attribute_group priv_attr_group = =3D { .attrs =3D priv_attrs, }; =20 -static const struct attribute_group *l2_get_priv_group(struct cacheinfo *t= his_leaf) +static const struct attribute_group *ccache_get_priv_group(struct cacheinfo + *this_leaf) { - /* We want to use private group for L2 cache only */ + /* We want to use private group for composable cache only */ if (this_leaf->level =3D=3D 2) return &priv_attr_group; else return NULL; } =20 -static irqreturn_t l2_int_handler(int irq, void *device) +static irqreturn_t ccache_int_handler(int irq, void *device) { unsigned int add_h, add_l; =20 if (irq =3D=3D g_irq[DIR_CORR]) { - add_h =3D readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH); - add_l =3D readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW); - pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + add_h =3D readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); + add_l =3D readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); + pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, + readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_CE, "DirECCFix"); } if (irq =3D=3D g_irq[DIR_UNCORR]) { - add_h =3D readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH); - add_l =3D readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW); + add_h =3D readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); + add_l =3D readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); /* Reading this register clears the DirFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, + readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_UE, "DirECCFail"); - panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); + panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); } if (irq =3D=3D g_irq[DATA_CORR]) { - add_h =3D readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH); - add_l =3D readl(l2_base + SIFIVE_L2_DATECCFIX_LOW); - pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + add_h =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); + add_l =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); + pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, + readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_CE, "DatECCFix"); } if (irq =3D=3D g_irq[DATA_UNCORR]) { - add_h =3D readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH); - add_l =3D readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW); - pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + add_h =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); + add_l =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); + pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, + readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, + SIFIVE_CCACHE_ERR_TYPE_UE, "DatECCFail"); } =20 return IRQ_HANDLED; } =20 -static int __init sifive_l2_init(void) +static int __init sifive_ccache_init(void) { struct device_node *np; struct resource res; int i, rc, intr_num; =20 - np =3D of_find_matching_node(NULL, sifive_l2_ids); + np =3D of_find_matching_node(NULL, sifive_ccache_ids); if (!np) return -ENODEV; =20 if (of_address_to_resource(np, 0, &res)) return -ENODEV; =20 - l2_base =3D ioremap(res.start, resource_size(&res)); - if (!l2_base) + ccache_base =3D ioremap(res.start, resource_size(&res)); + if (!ccache_base) return -ENOMEM; =20 intr_num =3D of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { - pr_err("L2CACHE: no interrupts property\n"); + pr_err("CCACHE: no interrupts property\n"); return -ENODEV; } =20 for (i =3D 0; i < intr_num; i++) { g_irq[i] =3D irq_of_parse_and_map(np, i); - rc =3D request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); + rc =3D request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", + NULL); if (rc) { - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); + pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); return rc; } } =20 - l2_config_read(); + ccache_config_read(); =20 - l2_cache_ops.get_priv_group =3D l2_get_priv_group; - riscv_set_cacheinfo_ops(&l2_cache_ops); + ccache_cache_ops.get_priv_group =3D ccache_get_priv_group; + riscv_set_cacheinfo_ops(&ccache_cache_ops); =20 #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif return 0; } -device_initcall(sifive_l2_init); + +device_initcall(sifive_ccache_init); diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifi= ve_ccache.h similarity index 12% rename from include/soc/sifive/sifive_l2_cache.h rename to include/soc/sifive/sifive_ccache.h index 92ade10ed67e..4d4ed49388a0 100644 --- a/include/soc/sifive/sifive_l2_cache.h +++ b/include/soc/sifive/sifive_ccache.h @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * SiFive L2 Cache Controller header file + * SiFive Composable Cache Controller header file * */ =20 -#ifndef __SOC_SIFIVE_L2_CACHE_H -#define __SOC_SIFIVE_L2_CACHE_H +#ifndef __SOC_SIFIVE_CCACHE_H +#define __SOC_SIFIVE_CCACHE_H =20 -extern int register_sifive_l2_error_notifier(struct notifier_block *nb); -extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); +extern int register_sifive_ccache_error_notifier(struct notifier_block *nb= ); +extern int unregister_sifive_ccache_error_notifier(struct notifier_block *= nb); =20 -#define SIFIVE_L2_ERR_TYPE_CE 0 -#define SIFIVE_L2_ERR_TYPE_UE 1 +#define SIFIVE_CCACHE_ERR_TYPE_CE 0 +#define SIFIVE_CCACHE_ERR_TYPE_UE 1 =20 -#endif /* __SOC_SIFIVE_L2_CACHE_H */ +#endif /* __SOC_SIFIVE_CCACHE_H */ --=20 2.17.1 From nobody Mon Apr 6 00:29:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 828B3C6FA86 for ; Tue, 13 Sep 2022 06:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230213AbiIMGTJ (ORCPT ); Tue, 13 Sep 2022 02:19:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229916AbiIMGSe (ORCPT ); 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id z11-20020a170902cccb00b00173cfaed233sm7296332ple.62.2022.09.12.23.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:18:32 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v5 3/7] soc: sifive: ccache: determine the cache level from dts Date: Tue, 13 Sep 2022 06:18:13 +0000 Message-Id: <20220913061817.22564-4-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com> References: <20220913061817.22564-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive= _ccache.c index 949b824e89ad..b361b661ea09 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -38,6 +38,7 @@ static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; static struct riscv_cacheinfo_ops ccache_cache_ops; +static int level; =20 enum { DIR_CORR =3D 0, @@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_gr= oup(struct cacheinfo *this_leaf) { /* We want to use private group for composable cache only */ - if (this_leaf->level =3D=3D 2) + if (this_leaf->level =3D=3D level) return &priv_attr_group; else return NULL; @@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void) if (!ccache_base) return -ENOMEM; =20 + if (of_property_read_u32(np, "cache-level", &level)) + return -ENOENT; + intr_num =3D of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("CCACHE: no interrupts property\n"); --=20 2.17.1 From nobody Mon Apr 6 00:29:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2A25C6FA8B for ; Tue, 13 Sep 2022 06:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230305AbiIMGTM (ORCPT ); Tue, 13 Sep 2022 02:19:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230242AbiIMGSj (ORCPT ); Tue, 13 Sep 2022 02:18:39 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3F9E57546 for ; Mon, 12 Sep 2022 23:18:36 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id j12so10768065pfi.11 for ; Mon, 12 Sep 2022 23:18:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=6Xe3R/apOfj9yPTgHstXk1duLFBJjDM/Rtwt0f9H5Eo=; b=IgoMd+u3Sm/bJS7kCMLfQkYbB0LDum24SEmPzf81Dli83n/7DWclAijuMnc2ag70Dj C8p4BqoBvQuAuLEz6gUs8vSbA5gGTEafAglSpKreyZuFw2ZX63tqtZ8U/dHkSyygD5fG Yfo0PXzP7PvU5CVP8Ddfrlgksld0VirTSAP30glA91Q7ZhFXwsMMUkR+d+JY/qB5+GQL qIYUs5FVpgRIWY72xdriOzcJKiXQ4/I12hNhcpWveBIPHQRhS/psJkE7lT/37q9dZy0R fmI1kyNum/HPtVCrJwaXU+M8o9K8EWxGWltQfz24RbeL/+YS/FYNF9qYVxz9lESgCbWr yu/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=6Xe3R/apOfj9yPTgHstXk1duLFBJjDM/Rtwt0f9H5Eo=; b=zOytmO0GEIhU1UKx9Z/17v7iSsUr0M+ammtd4mUZo+WkVAbvxO25t0bFrt7UnaI/Cs yrSEqG9DvXF5qIsdvHwmp5WXHD06v+0CAOCbN8eqcgYxYAQYWd02wTFW2WSKiPM3BIWE jf6siMlLyY2xxCe5EFm94AJO41zAkSH5thc3ABJgrvXEPjpBrrhsdEyyYkMnejPWHbPr p/C4Ue+AOtcJyvQnHi/JeDbZiqOb0WSZe4VcMftrTy7Y4jGYxKt8Wg4Nj3Sjf42EWVq6 g4ei0XM3+8o4CjMyrMEXT0G54bR9awnR7+74F2QS3KTpACtOmchQeNXE5G0zMJAt/vqQ 0Zqg== X-Gm-Message-State: ACgBeo223V+Z1Ygxq3HsWcC/jMZNilJzsFvdNIaiYdmZbQZ5XcdT9+/Z WZONkC5EV4u4sthuvYSztiPj6g== X-Google-Smtp-Source: AA6agR4wJMWC1gO3gMaes8hVyStuNQfqovIqF+q7yPPAeBfyztWmRp9gIz2JfroB/V12MFPD76hGfQ== X-Received: by 2002:a05:6a00:2181:b0:51b:560b:dd30 with SMTP id h1-20020a056a00218100b0051b560bdd30mr31748430pfi.44.1663049916137; Mon, 12 Sep 2022 23:18:36 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id z11-20020a170902cccb00b00173cfaed233sm7296332ple.62.2022.09.12.23.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:18:35 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v5 4/7] soc: sifive: ccache: reduce printing on init Date: Tue, 13 Sep 2022 06:18:14 +0000 Message-Id: <20220913061817.22564-5-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com> References: <20220913061817.22564-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Ben Dooks The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive= _ccache.c index b361b661ea09..17080af7dfa0 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -81,20 +81,17 @@ static void setup_sifive_debug(void) =20 static void ccache_config_read(void) { - u32 regval, val; - - regval =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG); - val =3D regval & 0xFF; - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); - val =3D (regval & 0xFF00) >> 8; - pr_info("CCACHE: No. of ways per bank: %d\n", val); - val =3D (regval & 0xFF0000) >> 16; - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); - val =3D (regval & 0xFF000000) >> 24; - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - - regval =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); + u32 cfg; + + cfg =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG); + + pr_info("CCACHE: %u banks, %u ways, sets/bank=3D%llu, bytes/block=3D%llu\= n", + (cfg & 0xff), (cfg >> 8) & 0xff, + BIT_ULL((cfg >> 16) & 0xff), + BIT_ULL((cfg >> 24) & 0xff)); + + cfg =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); } =20 static const struct of_device_id sifive_ccache_ids[] =3D { --=20 2.17.1 From nobody Mon Apr 6 00:29:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8127C6FA90 for ; Tue, 13 Sep 2022 06:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230320AbiIMGTO (ORCPT ); Tue, 13 Sep 2022 02:19:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230101AbiIMGSk (ORCPT ); Tue, 13 Sep 2022 02:18:40 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E25D57542 for ; Mon, 12 Sep 2022 23:18:39 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id d82so10769595pfd.10 for ; Mon, 12 Sep 2022 23:18:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=KI8GGOYVJ30lpXYNmzlWaq92ei+up8qB7deF01pAkE4=; b=CZ+teBhlhis5wFUYdxdcaWhEgOEww+/Db4CC4fbPu9/xi2buOMzifHhDyLjViSrSW1 4LEDGvKRsB2t1fX4qyDlRaKfszPSOC/JDYqLVU13V9CibT1P5fsjYuhA8wnc/mELjdpQ p3R2r+ZZ363BoLJp8AxyyyDCp47W1fDmTPKVMvLjTjR/IEUss0jXx0A3DUjNgiR9hxM6 TizW5hVag/yLzs2dSsnA8MGIZOwz4mXxfAYXQedGlQHwoj4Fjs5WlhZXxPI9UJ9bKaTu ovjYEDVdshxcAJ8+0xgV58BiFJAuLTX1xNFPtSerANdu5gbUK0BBkdJVMbOvLrXPUAVb Y4Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=KI8GGOYVJ30lpXYNmzlWaq92ei+up8qB7deF01pAkE4=; b=tK46hJGhMrLCaWp/LOzote8HtZwieW5QHUNPdqY9zuQOL1klK6PhTnNECFoKQ8Xnhl NT43vM9MtNR7JtUQdE8j6u+dzWZTFfHMKLMTCTXDgzJCND0KpusdJeIAArbcTslooH9/ i1z14yEK50vpT2lvo/2YoC/GxnyP7ENInosINCTEK/GRJEttuZcuAXGmEa+AGr0VLqW1 7rMsx9KiMQHBI/1dL6EP5xrzV3ZbvSHA2HLchoXqVCvbPQ0Mmm+oxoFd+O0+iEp6DhGT UGUbg4jGrOYTn3yNlkh4hNYavLERXckIdrtF7KGk+JzxNVJiNCXAEoSeDZSXNAR20Nug eO1Q== X-Gm-Message-State: ACgBeo1lucHrOOM/FpvnHOvM6/ZnGUFR20SGdhK2MyXN/CCaJh3JhxRo qBqbcFkL65wq2ujO3Z41t2hM7w== X-Google-Smtp-Source: AA6agR5lAPSERiuwyxmqPgFoLJ1TQBeoJcDfyodPk4tCaG6Q3ueHdqIL7Mw7gf8jctkZyHhapVK8Tw== X-Received: by 2002:a05:6a00:1ac7:b0:537:4186:c106 with SMTP id f7-20020a056a001ac700b005374186c106mr31355839pfv.76.1663049919084; Mon, 12 Sep 2022 23:18:39 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id z11-20020a170902cccb00b00173cfaed233sm7296332ple.62.2022.09.12.23.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:18:38 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v5 5/7] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Date: Tue, 13 Sep 2022 06:18:15 +0000 Message-Id: <20220913061817.22564-6-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com> References: <20220913061817.22564-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Ben Dooks Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive= _ccache.c index 17080af7dfa0..91f0c2b32ea2 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -5,6 +5,9 @@ * Copyright (C) 2018-2022 SiFive, Inc. * */ + +#define pr_fmt(fmt) "CCACHE: " fmt + #include #include #include @@ -85,13 +88,13 @@ static void ccache_config_read(void) =20 cfg =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG); =20 - pr_info("CCACHE: %u banks, %u ways, sets/bank=3D%llu, bytes/block=3D%llu\= n", + pr_info("%u banks, %u ways, sets/bank=3D%llu, bytes/block=3D%llu\n", (cfg & 0xff), (cfg >> 8) & 0xff, BIT_ULL((cfg >> 16) & 0xff), BIT_ULL((cfg >> 24) & 0xff)); =20 cfg =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %u\n", cfg); + pr_info("Index of the largest way enabled: %u\n", cfg); } =20 static const struct of_device_id sifive_ccache_ids[] =3D { @@ -155,7 +158,7 @@ static irqreturn_t ccache_int_handler(int irq, void *de= vice) if (irq =3D=3D g_irq[DIR_CORR]) { add_h =3D readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); add_l =3D readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); - pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -175,7 +178,7 @@ static irqreturn_t ccache_int_handler(int irq, void *de= vice) if (irq =3D=3D g_irq[DATA_CORR]) { add_h =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); add_l =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); - pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -185,7 +188,7 @@ static irqreturn_t ccache_int_handler(int irq, void *de= vice) if (irq =3D=3D g_irq[DATA_UNCORR]) { add_h =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); add_l =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); - pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); atomic_notifier_call_chain(&ccache_err_chain, @@ -218,7 +221,7 @@ static int __init sifive_ccache_init(void) =20 intr_num =3D of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { - pr_err("CCACHE: no interrupts property\n"); + pr_err("No interrupts property\n"); return -ENODEV; } =20 @@ -227,7 +230,7 @@ static int __init sifive_ccache_init(void) rc =3D request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL); if (rc) { - pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); + pr_err("Could not request IRQ %d\n", g_irq[i]); return rc; } } --=20 2.17.1 From nobody Mon Apr 6 00:29:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6969C6FA8E for ; Tue, 13 Sep 2022 06:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbiIMGTR (ORCPT ); Tue, 13 Sep 2022 02:19:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230283AbiIMGSn (ORCPT ); Tue, 13 Sep 2022 02:18:43 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A2095727B for ; Mon, 12 Sep 2022 23:18:42 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id b21so10787079plz.7 for ; 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charset="utf-8" Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive= _ccache.c index 91f0c2b32ea2..1c171150e878 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -33,6 +34,11 @@ #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 =20 #define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0) +#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8) +#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) +#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) + #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 =20 @@ -87,11 +93,11 @@ static void ccache_config_read(void) u32 cfg; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id z11-20020a170902cccb00b00173cfaed233sm7296332ple.62.2022.09.12.23.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:18:44 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v5 7/7] riscv: Add cache information in AUX vector Date: Tue, 13 Sep 2022 06:18:17 +0000 Message-Id: <20220913061817.22564-8-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com> References: <20220913061817.22564-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Greentime Hu There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. sysconf syscall could use them to get information of cache through AUX vector. The result of 'getconf -a|grep -i cache' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC 2 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC 4 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 524288 LEVEL2_CACHE_ASSOC 8 LEVEL2_CACHE_LINESIZE 64 LEVEL3_CACHE_SIZE 4194304 LEVEL3_CACHE_ASSOC 16 LEVEL3_CACHE_LINESIZE 64 LEVEL4_CACHE_SIZE 0 LEVEL4_CACHE_ASSOC 0 LEVEL4_CACHE_LINESIZE 0 Signed-off-by: Greentime Hu Signed-off-by: Zong Li Suggested-by: Zong Li --- arch/riscv/include/asm/elf.h | 4 ++++ arch/riscv/include/uapi/asm/auxvec.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index 14fc7342490b..e7acffdf21d2 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -99,6 +99,10 @@ do { \ get_cache_size(2, CACHE_TYPE_UNIFIED)); \ NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ + NEW_AUX_ENT(AT_L3_CACHESIZE, \ + get_cache_size(3, CACHE_TYPE_UNIFIED)); \ + NEW_AUX_ENT(AT_L3_CACHEGEOMETRY, \ + get_cache_geometry(3, CACHE_TYPE_UNIFIED)); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi= /asm/auxvec.h index 32c73ba1d531..fb187a33ce58 100644 --- a/arch/riscv/include/uapi/asm/auxvec.h +++ b/arch/riscv/include/uapi/asm/auxvec.h @@ -30,8 +30,10 @@ #define AT_L1D_CACHEGEOMETRY 43 #define AT_L2_CACHESIZE 44 #define AT_L2_CACHEGEOMETRY 45 +#define AT_L3_CACHESIZE 46 +#define AT_L3_CACHEGEOMETRY 47 =20 /* entries in ARCH_DLINFO */ -#define AT_VECTOR_SIZE_ARCH 7 +#define AT_VECTOR_SIZE_ARCH 9 =20 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ --=20 2.17.1