From nobody Mon Apr 6 03:13:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F16BC6FA82 for ; Mon, 12 Sep 2022 16:01:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229511AbiILQBm (ORCPT ); Mon, 12 Sep 2022 12:01:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229982AbiILQBX (ORCPT ); Mon, 12 Sep 2022 12:01:23 -0400 Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF2173BC5A for ; Mon, 12 Sep 2022 09:01:13 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx1.riseup.net (Postfix) with ESMTPS id 4MRBCr2SdxzDrTZ; Mon, 12 Sep 2022 16:01:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1662998472; bh=HyJ/Hhe0IBlk/zIjWnliYZ2iULMuLhEtLRHxxENi4nQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wei4RU3SWW6xRsN6iLo/yTYxiwGG7gK9ermDt1krat8f6wuM8dwZ6wfHWlYxdD1HW 5rmOjBPEa22E/MIiS4yIem86fh/4y4hcGO8eN8Qqu3ToyEMk7G+boEXWcn4lH8ZPF3 8xh7c8f8Rf/qE1ZipSySwH0mWntnNOEFgBVhiD9o= X-Riseup-User-ID: EFDF76168C216C5EE1D3843711117306A4A54C53BF578A4966DF025C700FA0B6 Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4MRBCj1xf9z5vRK; Mon, 12 Sep 2022 16:01:05 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Harry Wentland , Leo Li , Rodrigo Siqueira , Nicholas Choi , Daniel Latypov , David Gow Cc: andrealmeid@riseup.net, mwen@igalia.com, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, Trevor Woerner , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, kunit-dev@googlegroups.com, linux-kernel@vger.kernel.org, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH v3 7/8] drm/amd/display: Introduce KUnit tests to dc_dmub_srv library Date: Mon, 12 Sep 2022 12:59:18 -0300 Message-Id: <20220912155919.39877-8-mairacanal@riseup.net> In-Reply-To: <20220912155919.39877-1-mairacanal@riseup.net> References: <20220912155919.39877-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add unit test to the SubVP feature in order to avoid possible regressions and assure the code robustness. Signed-off-by: Ma=C3=ADra Canal Reported-by: kernel test robot --- drivers/gpu/drm/amd/display/Kconfig | 13 + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 + .../gpu/drm/amd/display/tests/.kunitconfig | 1 + .../amd/display/tests/dc/dc_dmub_srv_test.c | 285 ++++++++++++++++++ 4 files changed, 303 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/disp= lay/Kconfig index 039227baedfa..f667b954f89f 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -93,4 +93,17 @@ config AMD_DC_BASICS_KUNIT_TEST =20 If unsure, say N. =20 +config AMD_DC_KUNIT_TEST + bool "Enable KUnit tests for the 'utils' sub-component of DAL" if !KUNIT_= ALL_TESTS + depends on DRM_AMD_DC && KUNIT + default KUNIT_ALL_TESTS + help + Enables unit tests for the basics folder of Display Core. Only useful for + kernel devs running KUnit. + + For more information on KUnit and unit tests in general please refer to + the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + endmenu diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm= /amd/display/dc/dc_dmub_srv.c index 7b765efe0825..2e8d5549a087 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -858,3 +858,7 @@ void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv= *dc_dmub_srv) diag_data.is_cw0_enabled, diag_data.is_cw6_enabled); } + +#if IS_ENABLED(CONFIG_AMD_DC_KUNIT_TEST) +#include "../tests/dc/dc_dmub_srv_test.c" +#endif diff --git a/drivers/gpu/drm/amd/display/tests/.kunitconfig b/drivers/gpu/d= rm/amd/display/tests/.kunitconfig index eb6f81601757..4c5861ad58bd 100644 --- a/drivers/gpu/drm/amd/display/tests/.kunitconfig +++ b/drivers/gpu/drm/amd/display/tests/.kunitconfig @@ -4,5 +4,6 @@ CONFIG_DRM=3Dy CONFIG_DRM_AMDGPU=3Dy CONFIG_DRM_AMD_DC=3Dy CONFIG_AMD_DC_BASICS_KUNIT_TEST=3Dy +CONFIG_AMD_DC_KUNIT_TEST=3Dy CONFIG_DCE_KUNIT_TEST=3Dy CONFIG_DML_KUNIT_TEST=3Dy diff --git a/drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c b/driv= ers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c new file mode 100644 index 000000000000..3f1f15397090 --- /dev/null +++ b/drivers/gpu/drm/amd/display/tests/dc/dc_dmub_srv_test.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: MIT +/* + * KUnit tests for dc_dmub_srv.c + * + * Copyright (C) 2022, Ma=C3=ADra Canal + */ + +#include +#include "dc_dmub_srv.h" + +struct populate_subvp_cmd_drr_info_test_case { + const char *desc; + struct dc *dc; + struct pipe_ctx *subvp_pipe; + struct pipe_ctx *vblank_pipe; + const u8 drr_in_use; + const u8 drr_window_size_ms; + const u16 min_vtotal_supported; + const u16 max_vtotal_supported; + const u8 use_ramping; +}; + +struct populate_subvp_cmd_drr_info_test_case populate_subvp_cmd_drr_info_c= ases[] =3D { + { + .desc =3D "Same Clock Frequency", + .dc =3D &(struct dc) { + .caps =3D { + .subvp_prefetch_end_to_mall_start_us =3D 0, + } + }, + .subvp_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 2784, + .v_addressable =3D 1080, + .pix_clk_100hz =3D 1855800, + }, + .mall_stream_config =3D { + .paired_stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 3600, + .v_total =3D 1111, + .v_addressable =3D 1080, + .v_front_porch =3D 3, + .pix_clk_100hz =3D 1855800, + }, + }, + }, + }, + }, + .vblank_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 2784, + .v_total =3D 1111, + .v_addressable =3D 1080, + .pix_clk_100hz =3D 1855800, + }, + }, + }, + .drr_in_use =3D true, + .use_ramping =3D false, + .drr_window_size_ms =3D 4, + .min_vtotal_supported =3D 63709, + .max_vtotal_supported =3D 363, + }, + { + .desc =3D "Same Clock Frequency with Prefetch End to Mall Start", + .dc =3D &(struct dc) { + .caps =3D { + .subvp_prefetch_end_to_mall_start_us =3D 500, + } + }, + .subvp_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 2784, + .v_addressable =3D 1080, + .pix_clk_100hz =3D 1855800, + }, + .mall_stream_config =3D { + .paired_stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 3600, + .v_total =3D 1111, + .v_addressable =3D 1080, + .v_front_porch =3D 3, + .pix_clk_100hz =3D 1855800, + }, + }, + }, + }, + }, + .vblank_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 2784, + .v_total =3D 1111, + .v_addressable =3D 1080, + .pix_clk_100hz =3D 1855800, + }, + }, + }, + .drr_in_use =3D true, + .use_ramping =3D false, + .drr_window_size_ms =3D 4, + .min_vtotal_supported =3D 63709, + .max_vtotal_supported =3D 346, + }, + { + .desc =3D "Same Clock Frequency Not Multiple of 2", + .dc =3D &(struct dc) { + .caps =3D { + .subvp_prefetch_end_to_mall_start_us =3D 0, + } + }, + .subvp_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 2784, + .v_addressable =3D 1080, + .pix_clk_100hz =3D 1866743, + }, + .mall_stream_config =3D { + .paired_stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 3600, + .v_total =3D 2400, + .v_addressable =3D 2360, + .v_front_porch =3D 4, + .pix_clk_100hz =3D 1866743, + }, + }, + }, + }, + }, + .vblank_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 3600, + .v_total =3D 2400, + .v_addressable =3D 2360, + .pix_clk_100hz =3D 1866743, + }, + }, + }, + .drr_in_use =3D true, + .use_ramping =3D false, + .drr_window_size_ms =3D 4, + .min_vtotal_supported =3D 1387, + .max_vtotal_supported =3D 399, + }, + { + .desc =3D "Different Clock Frequency for smaller h_total and v_total", + .dc =3D &(struct dc) { + .caps =3D { + .subvp_prefetch_end_to_mall_start_us =3D 300, + } + }, + .subvp_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 1280, + .v_addressable =3D 600, + .pix_clk_100hz =3D 1855800, + }, + .mall_stream_config =3D { + .paired_stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 1280, + .v_total =3D 720, + .v_addressable =3D 600, + .v_front_porch =3D 4, + .pix_clk_100hz =3D 1866743, + }, + }, + }, + }, + }, + .vblank_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 1280, + .v_total =3D 720, + .v_addressable =3D 600, + .pix_clk_100hz =3D 2100800, + }, + }, + }, + .drr_in_use =3D true, + .use_ramping =3D false, + .drr_window_size_ms =3D 4, + .min_vtotal_supported =3D 1477, + .max_vtotal_supported =3D 212, + }, + { + .desc =3D "Different Clock Frequency for approximately 1920x1080", + .dc =3D &(struct dc) { + .caps =3D { + .subvp_prefetch_end_to_mall_start_us =3D 0, + } + }, + .subvp_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 1920, + .v_addressable =3D 1000, + .pix_clk_100hz =3D 1855800, + }, + .mall_stream_config =3D { + .paired_stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 1911, + .v_total =3D 1080, + .v_addressable =3D 1000, + .v_front_porch =3D 7, + .pix_clk_100hz =3D 1866743, + }, + }, + }, + }, + }, + .vblank_pipe =3D &(struct pipe_ctx) { + .stream =3D &(struct dc_stream_state) { + .timing =3D { + .h_total =3D 1280, + .v_total =3D 720, + .v_addressable =3D 600, + .pix_clk_100hz =3D 2100800, + }, + }, + }, + .drr_in_use =3D true, + .use_ramping =3D false, + .drr_window_size_ms =3D 4, + .min_vtotal_supported =3D 2482, + .max_vtotal_supported =3D 247, + }, +}; + +static void populate_subvp_cmd_drr_info_test_to_desc(struct + populate_subvp_cmd_drr_info_test_case * t, char *desc) +{ + strcpy(desc, t->desc); +} + +KUNIT_ARRAY_PARAM(populate_subvp_cmd_drr_info, populate_subvp_cmd_drr_info= _cases, + populate_subvp_cmd_drr_info_test_to_desc); + +static void populate_subvp_cmd_drr_info_test(struct kunit *test) +{ + const struct populate_subvp_cmd_drr_info_test_case *test_param =3D + test->param_value; + struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data; + + pipe_data =3D kunit_kzalloc(test, + sizeof(struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2), + GFP_KERNEL); + + populate_subvp_cmd_drr_info(test_param->dc, test_param->subvp_pipe, + test_param->vblank_pipe, pipe_data); + + KUNIT_EXPECT_EQ(test, test_param->drr_in_use, + pipe_data->pipe_config.vblank_data.drr_info.drr_in_use); + KUNIT_EXPECT_EQ(test, test_param->drr_window_size_ms, + pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms); + KUNIT_EXPECT_EQ(test, test_param->use_ramping, + pipe_data->pipe_config.vblank_data.drr_info.use_ramping); + KUNIT_EXPECT_EQ(test, test_param->min_vtotal_supported, + pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported); + KUNIT_EXPECT_EQ(test, test_param->max_vtotal_supported, + pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported); +} + +static struct kunit_case dc_dmub_srv_cases[] =3D { + KUNIT_CASE_PARAM(populate_subvp_cmd_drr_info_test, populate_subvp_cmd_drr= _info_gen_params), + { } +}; + +static struct kunit_suite dc_dmub_srv_suite =3D { + .name =3D "dc_dmub_srv", + .test_cases =3D dc_dmub_srv_cases, +}; + +kunit_test_suite(dc_dmub_srv_suite); --=20 2.37.3