From nobody Mon Apr 6 03:13:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D10C6FA82 for ; Mon, 12 Sep 2022 16:01:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229801AbiILQBb (ORCPT ); Mon, 12 Sep 2022 12:01:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229929AbiILQBR (ORCPT ); Mon, 12 Sep 2022 12:01:17 -0400 Received: from mx0.riseup.net (mx0.riseup.net [198.252.153.6]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB71F3BC56 for ; Mon, 12 Sep 2022 09:01:02 -0700 (PDT) Received: from fews1.riseup.net (fews1-pn.riseup.net [10.0.1.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mail.riseup.net", Issuer "R3" (not verified)) by mx0.riseup.net (Postfix) with ESMTPS id 4MRBCd2PXrz9sLj; Mon, 12 Sep 2022 16:01:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=riseup.net; s=squak; t=1662998461; bh=Zj8lZlB17QSesE4crmsZoGH0WSHlMlR1UgiHzhX8W04=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AjQ+5JwC7KHmhpjtJ/LUnSsANVJBN1q8erE5dyIjnUrZpUPgxp0wJYf9s7IinFyBL aTtLMN0XAUqgOs+f7oJ3BcXMlF58xenUxzKh9Y+c8YgFA+8yOzxF4NYGXFfrrOHTmv QTPpSHQrDd9wYI0jqIEurV0Eom84P0YQbCFu3RGY= X-Riseup-User-ID: 98211E5FB4F5632ACB729F2BC44D36B79EC1C5E2BCC2929BA5012AE8DA66B4BA Received: from [127.0.0.1] (localhost [127.0.0.1]) by fews1.riseup.net (Postfix) with ESMTPSA id 4MRBCV1Xyvz5vRK; Mon, 12 Sep 2022 16:00:53 +0000 (UTC) From: =?UTF-8?q?Ma=C3=ADra=20Canal?= To: Alex Deucher , christian.koenig@amd.com, Xinhui.Pan@amd.com, David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Harry Wentland , Leo Li , Rodrigo Siqueira , Nicholas Choi , Daniel Latypov , David Gow Cc: andrealmeid@riseup.net, mwen@igalia.com, Isabella Basso , magalilemes00@gmail.com, tales.aparecida@gmail.com, Trevor Woerner , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, kunit-dev@googlegroups.com, linux-kernel@vger.kernel.org, =?UTF-8?q?Ma=C3=ADra=20Canal?= Subject: [PATCH v3 6/8] drm/amd/display: Introduce KUnit tests for dcn20_fpu Date: Mon, 12 Sep 2022 12:59:17 -0300 Message-Id: <20220912155919.39877-7-mairacanal@riseup.net> In-Reply-To: <20220912155919.39877-1-mairacanal@riseup.net> References: <20220912155919.39877-1-mairacanal@riseup.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magali Lemes This commit adds unit tests to the functions dcn20_cap_soc_clocks and dcn21_update_bw_bounding_box from dcn20/dcn20_fpu. Signed-off-by: Magali Lemes Signed-off-by: Ma=C3=ADra Canal --- drivers/gpu/drm/amd/display/tests/Makefile | 3 +- .../tests/dc/dml/dcn20/dcn20_fpu_test.c | 561 ++++++++++++++++++ 2 files changed, 563 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/display/tests/dc/dml/dcn20/dcn20_fp= u_test.c diff --git a/drivers/gpu/drm/amd/display/tests/Makefile b/drivers/gpu/drm/a= md/display/tests/Makefile index cc1e9edd38c3..a34677808e48 100644 --- a/drivers/gpu/drm/amd/display/tests/Makefile +++ b/drivers/gpu/drm/amd/display/tests/Makefile @@ -9,7 +9,8 @@ endif =20 ifdef CONFIG_DML_KUNIT_TEST CFLAGS_$(AMDDALPATH)/tests/dc/dml/display_mode_vba_test.o :=3D $(dml_ccfl= ags) - DC_TESTS +=3D dc/dml/display_mode_vba_test.o + CFLAGS_$(AMDDALPATH)/tests/dc/dml/dcn20/dcn20_fpu_test.o :=3D $(dml_ccfla= gs) + DC_TESTS +=3D dc/dml/display_mode_vba_test.o dc/dml/dcn20/dcn20_fpu_test.o endif =20 AMD_DAL_DC_TESTS =3D $(addprefix $(AMDDALPATH)/tests/,$(DC_TESTS)) diff --git a/drivers/gpu/drm/amd/display/tests/dc/dml/dcn20/dcn20_fpu_test.= c b/drivers/gpu/drm/amd/display/tests/dc/dml/dcn20/dcn20_fpu_test.c new file mode 100644 index 000000000000..6b7ebb78fec9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/tests/dc/dml/dcn20/dcn20_fpu_test.c @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: MIT +/* + * KUnit tests for dml/dcn20/dcn20_fpu.h + * + * Copyright (C) 2022, Magali Lemes + */ + +#include + +#include "dc/inc/resource.h" +#include "dc/inc/hw/clk_mgr.h" +#include "dc/dcn21/dcn21_resource.h" + +#include "dml/dcn20/dcn20_fpu.h" + +/** + * DOC: Unit tests for AMDGPU DML dcn20/dcn20_fpu.h + */ + +struct dcn20_cap_soc_clocks_test_case { + const char *desc; + struct _vcs_dpi_soc_bounding_box_st bb; + struct pp_smu_nv_clock_table max_clocks; + const int clock_states; + const struct _vcs_dpi_voltage_scaling_st expected_clock_limits[DC__VOLTAG= E_STATES]; +}; + +struct dcn21_update_bw_bounding_box_test_case { + const char *desc; + struct dc dc; + struct clk_bw_params bw_params; + const int clocks_to_compare; + const struct _vcs_dpi_voltage_scaling_st expected_clock_limits[DC__VOLTAG= E_STATES]; +}; + +struct dcn20_cap_soc_clocks_test_case dcn20_cap_soc_clocks_test_cases[] = =3D { + { + .desc =3D "4-state bounding box clock limits ", + .bb =3D { + .clock_limits =3D { + { + .dcfclk_mhz =3D 506.0, + .fabricclk_mhz =3D 506.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 506.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 1600.0, + }, + { + .dcfclk_mhz =3D 540.0, + .fabricclk_mhz =3D 540.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 540.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 8000.0, + }, + { + .dcfclk_mhz =3D 675.0, + .fabricclk_mhz =3D 675.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 675.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 10000.0, + }, + { + .dcfclk_mhz =3D 1265.0, + .fabricclk_mhz =3D 1266.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 1266.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 15000.0, + }, + }, + .num_states =3D 4, + }, + .max_clocks =3D { + .dcfClockInKhz =3D 1265000, + .uClockInKhz =3D 875000, + .fabricClockInKhz =3D 0, + .displayClockInKhz =3D 1284000, + .dppClockInKhz =3D 0, + .phyClockInKhz =3D 810000, + .socClockInKhz =3D 1266000, + .dscClockInKhz =3D 0, + }, + .clock_states =3D 4, + .expected_clock_limits =3D { + { + .dcfclk_mhz =3D 506.0, + .fabricclk_mhz =3D 506.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 506.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 1600.0, + }, + { + .dcfclk_mhz =3D 540.0, + .fabricclk_mhz =3D 540.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 540.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 8000.0, + }, + { + .dcfclk_mhz =3D 675.0, + .fabricclk_mhz =3D 675.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 675.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 10000.0, + }, + { + .dcfclk_mhz =3D 1265.0, + .fabricclk_mhz =3D 1266.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 1266.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 14000.0, + }, + }, + }, + { + .desc =3D "One duplicate clock state", + .bb =3D { + .clock_limits =3D { + { + .dcfclk_mhz =3D 506.0, + .fabricclk_mhz =3D 506.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 506.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 1600.0, + }, + { + .dcfclk_mhz =3D 675.0, + .fabricclk_mhz =3D 675.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 675.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 10000.0, + }, + { + .dcfclk_mhz =3D 675.0, + .fabricclk_mhz =3D 675.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 675.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 10000.0, + }, + { + .dcfclk_mhz =3D 1265.0, + .fabricclk_mhz =3D 1266.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 1266.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 15000.0, + }, + }, + .num_states =3D 4, + }, + .max_clocks =3D { + .dcfClockInKhz =3D 1265000, + .uClockInKhz =3D 875000, + .fabricClockInKhz =3D 0, + .displayClockInKhz =3D 1284000, + .dppClockInKhz =3D 0, + .phyClockInKhz =3D 810000, + .socClockInKhz =3D 1266000, + .dscClockInKhz =3D 0, + }, + .clock_states =3D 3, + .expected_clock_limits =3D { + { + .dcfclk_mhz =3D 506.0, + .fabricclk_mhz =3D 506.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 506.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 1600.0, + }, + { + .dcfclk_mhz =3D 675.0, + .fabricclk_mhz =3D 675.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 675.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 10000.0, + }, + { + .dcfclk_mhz =3D 675.0, + .fabricclk_mhz =3D 675.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 1284.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 675.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 10000.0, + }, + }, + }, + { + .desc =3D "Zeroed max clocks", + .bb =3D { + .clock_limits =3D { + { + .dcfclk_mhz =3D 506.0, + .fabricclk_mhz =3D 506.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 506.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 1600.0, + }, + }, + .num_states =3D 1, + }, + .max_clocks =3D { + .dcfClockInKhz =3D 0, + .uClockInKhz =3D 0, + .fabricClockInKhz =3D 0, + .displayClockInKhz =3D 0, + .dppClockInKhz =3D 0, + .phyClockInKhz =3D 0, + .socClockInKhz =3D 0, + .dscClockInKhz =3D 0, + }, + .clock_states =3D 1, + .expected_clock_limits =3D { + { + .dcfclk_mhz =3D 506.0, + .fabricclk_mhz =3D 506.0, + .dispclk_mhz =3D 1284.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 810.0, + .socclk_mhz =3D 506.0, + .dscclk_mhz =3D 428.0, + .dram_speed_mts =3D 1600.0, + }, + }, + }, +}; + +struct dcn21_update_bw_bounding_box_test_case dcn21_update_bw_bounding_box= _test_data[] =3D { + { + .desc =3D "5-entry bounding box clocks table", + .dc =3D { + .res_pool =3D &(struct resource_pool) { + .pipe_count =3D 2, + .res_cap =3D &(struct resource_caps) { + .num_timing_generator =3D 3 + }, + }, + }, + .bw_params =3D { + .num_channels =3D 1, + .clk_table =3D { + .entries =3D { + { + .voltage =3D 0, + .dcfclk_mhz =3D 200, + .fclk_mhz =3D 400, + .memclk_mhz =3D 800, + .socclk_mhz =3D 0, + }, + { + .voltage =3D 0, + .dcfclk_mhz =3D 201, + .fclk_mhz =3D 800, + .memclk_mhz =3D 1600, + .socclk_mhz =3D 0, + }, + { + .voltage =3D 0, + .dcfclk_mhz =3D 553, + .fclk_mhz =3D 1067, + .memclk_mhz =3D 1067, + .socclk_mhz =3D 0, + }, + { + .voltage =3D 0, + .dcfclk_mhz =3D 602, + .fclk_mhz =3D 1333, + .memclk_mhz =3D 1600, + .socclk_mhz =3D 0, + }, + { + .voltage =3D 0, + .dispclk_mhz =3D 1372, + .dppclk_mhz =3D 1372, + .phyclk_mhz =3D 810, + .phyclk_d18_mhz =3D 667, + .dtbclk_mhz =3D 600, + }, + }, + + .num_entries =3D 5, + }, + }, + .expected_clock_limits =3D { + { + .state =3D 0, + .dcfclk_mhz =3D 200.0, + .fabricclk_mhz =3D 400.0, + .dispclk_mhz =3D 600.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 600.0, + .socclk_mhz =3D 0.0, + .dscclk_mhz =3D 205.67, + .dram_speed_mts =3D 1600.0, + }, + { + .state =3D 1, + .dcfclk_mhz =3D 200.0, + .fabricclk_mhz =3D 400.0, + .dispclk_mhz =3D 600.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 600.0, + .socclk_mhz =3D 0.0, + .dscclk_mhz =3D 205.67, + .dram_speed_mts =3D 1600.0, + }, + { + .state =3D 2, + .dcfclk_mhz =3D 201, + .fabricclk_mhz =3D 800.0, + .dispclk_mhz =3D 600.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 600.0, + .socclk_mhz =3D 0.0, + .dscclk_mhz =3D 205.67, + .dram_speed_mts =3D 3200.0, + }, + { + .state =3D 3, + .dcfclk_mhz =3D 553.0, + .fabricclk_mhz =3D 1067.0, + .dispclk_mhz =3D 757.89, + .dppclk_mhz =3D 685.71, + .phyclk_mhz =3D 600.0, + .socclk_mhz =3D 0.0, + .dscclk_mhz =3D 287.67, + .dram_speed_mts =3D 2134.0, + }, + { + .state =3D 4, + .dcfclk_mhz =3D 602.0, + .fabricclk_mhz =3D 1333.0, + .dispclk_mhz =3D 847.06, + .dppclk_mhz =3D 757.89, + .phyclk_mhz =3D 600.0, + .socclk_mhz =3D 0.0, + .dscclk_mhz =3D 318.334, + .dram_speed_mts =3D 3200.0, + }, + { + .state =3D 5, + .dcfclk_mhz =3D 0.0, + .fabricclk_mhz =3D 0.0, + .dispclk_mhz =3D 600.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 600.0, + .socclk_mhz =3D 0.0, + .dscclk_mhz =3D 205.67, + .dram_speed_mts =3D 0.0, + }, + { + .state =3D 6, + .dcfclk_mhz =3D 0.0, + .fabricclk_mhz =3D 0.0, + .dispclk_mhz =3D 600.0, + .dppclk_mhz =3D 400.0, + .phyclk_mhz =3D 600.0, + .socclk_mhz =3D 0.0, + .dscclk_mhz =3D 205.67, + .dram_speed_mts =3D 0.0, + }, + }, + .clocks_to_compare =3D 6, + }, +}; + +/** + * dcn20_cap_soc_clocks_test - KUnit test for dcn20_cap_soc_clocks + * @test: represents a running instance of a test. + */ +static void dcn20_cap_soc_clocks_test(struct kunit *test) +{ + struct dcn20_cap_soc_clocks_test_case *test_param =3D + (struct dcn20_cap_soc_clocks_test_case *)test->param_value; + int i; + + DC_FP_START(); + dcn20_cap_soc_clocks(&test_param->bb, test_param->max_clocks); + DC_FP_END(); + + /* Check if no clock limit is higher than the specified maximum */ + for (i =3D 0; i < test_param->bb.num_states; i++) { + KUNIT_EXPECT_EQ(test, test_param->bb.clock_limits[i].dcfclk_mhz, + test_param->expected_clock_limits[i].dcfclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->bb.clock_limits[i].fabricclk_mhz, + test_param->expected_clock_limits[i].fabricclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->bb.clock_limits[i].dispclk_mhz, + test_param->expected_clock_limits[i].dispclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->bb.clock_limits[i].dppclk_mhz, + test_param->expected_clock_limits[i].dppclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->bb.clock_limits[i].phyclk_mhz, + test_param->expected_clock_limits[i].phyclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->bb.clock_limits[i].socclk_mhz, + test_param->expected_clock_limits[i].socclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->bb.clock_limits[i].dscclk_mhz, + test_param->expected_clock_limits[i].dscclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->bb.clock_limits[i].dram_speed_mts, + test_param->expected_clock_limits[i].dram_speed_mts); + } + + KUNIT_EXPECT_EQ(test, test_param->clock_states, test_param->bb.num_states= ); +} + +static struct _vcs_dpi_soc_bounding_box_st original_dcn2_1_soc; +static struct _vcs_dpi_ip_params_st original_dcn2_1_ip; + +/** + * dcn20_fpu_dcn21_update_bw_bounding_box_test_init - Store backup copies = of DCN global structures + * @test: represents a running instance of a test. + */ +int dcn20_fpu_dcn21_update_bw_bounding_box_test_init(struct kunit *test) +{ + memcpy(&original_dcn2_1_soc, &dcn2_1_soc, sizeof(struct _vcs_dpi_soc_boun= ding_box_st)); + memcpy(&original_dcn2_1_ip, &dcn2_1_ip, sizeof(struct _vcs_dpi_ip_params_= st)); + + return 0; +} + +/** + * dcn20_fpu_dcn21_update_bw_bounding_box_test_exit - Restore original val= ues + * of DCN global structures + * @test: represents a running instance of a test. + */ +static void dcn20_fpu_dcn21_update_bw_bounding_box_test_exit(struct kunit = *test) +{ + memcpy(&dcn2_1_soc, &original_dcn2_1_soc, sizeof(struct _vcs_dpi_soc_boun= ding_box_st)); + memcpy(&dcn2_1_ip, &original_dcn2_1_ip, sizeof(struct _vcs_dpi_ip_params_= st)); +} + +/** + * dcn21_update_bw_bounding_box_test - KUnit test for dcn21_update_bw_boun= ding_box + * @test: represents a running instance of a test. + */ +static void dcn21_update_bw_bounding_box_test(struct kunit *test) +{ + struct dcn21_update_bw_bounding_box_test_case *test_param =3D + (struct dcn21_update_bw_bounding_box_test_case *)test->param_value; + int i; + + DC_FP_START(); + dcn21_update_bw_bounding_box(&test_param->dc, &test_param->bw_params); + DC_FP_END(); + + KUNIT_EXPECT_EQ(test, test_param->dc.res_pool->res_cap->num_timing_genera= tor, + dcn2_1_ip.max_num_otg); + KUNIT_EXPECT_EQ(test, test_param->dc.res_pool->pipe_count, dcn2_1_ip.max_= num_dpp); + KUNIT_EXPECT_EQ(test, test_param->bw_params.num_channels, dcn2_1_soc.num_= chans); + + for (i =3D 0; i <=3D test_param->clocks_to_compare; i++) { + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].state, + dcn2_1_soc.clock_limits[i].state); + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].dcfclk_mhz, + dcn2_1_soc.clock_limits[i].dcfclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].fabricclk_mhz, + dcn2_1_soc.clock_limits[i].fabricclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].dispclk_mhz, + dcn2_1_soc.clock_limits[i].dispclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].dppclk_mhz, + dcn2_1_soc.clock_limits[i].dppclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].phyclk_mhz, + dcn2_1_soc.clock_limits[i].phyclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].socclk_mhz, + dcn2_1_soc.clock_limits[i].socclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].dscclk_mhz, + dcn2_1_soc.clock_limits[i].dscclk_mhz); + KUNIT_EXPECT_EQ(test, test_param->expected_clock_limits[i].dram_speed_mt= s, + dcn2_1_soc.clock_limits[i].dram_speed_mts); + } + + if (test_param->bw_params.clk_table.num_entries) + KUNIT_EXPECT_EQ(test, test_param->bw_params.clk_table.num_entries, + dcn2_1_soc.num_states); +} + +static void dcn20_cap_soc_clocks_test_to_desc(struct dcn20_cap_soc_clocks_= test_case *t, char *desc) +{ + strcpy(desc, t->desc); +} + +static void dcn21_update_bw_bounding_box_test_to_desc +(struct dcn21_update_bw_bounding_box_test_case *t, char *desc) +{ + strcpy(desc, t->desc); +} + +KUNIT_ARRAY_PARAM(dcn20_cap_soc_clocks, + dcn20_cap_soc_clocks_test_cases, + dcn20_cap_soc_clocks_test_to_desc); + +static struct kunit_case dcn20_fpu_test_cases[] =3D { + KUNIT_CASE_PARAM(dcn20_cap_soc_clocks_test, dcn20_cap_soc_clocks_gen_para= ms), + { } +}; + +static struct kunit_suite dcn20_fpu_test_suite =3D { + .name =3D "dml_dcn20_fpu", + .test_cases =3D dcn20_fpu_test_cases, +}; + +KUNIT_ARRAY_PARAM(dcn21_update_bw_bounding_box, + dcn21_update_bw_bounding_box_test_data, + dcn21_update_bw_bounding_box_test_to_desc); + +static struct kunit_case dcn20_fpu_dcn21_update_bw_bounding_box_test_cases= [] =3D { + KUNIT_CASE_PARAM(dcn21_update_bw_bounding_box_test, + dcn21_update_bw_bounding_box_gen_params), + { } +}; + +static struct kunit_suite dcn21_update_bw_bounding_box_test_suite =3D { + .name =3D "dml_dcn20_fpu_dcn21_update_bw_bounding_box_test", + .init =3D dcn20_fpu_dcn21_update_bw_bounding_box_test_init, + .exit =3D dcn20_fpu_dcn21_update_bw_bounding_box_test_exit, + .test_cases =3D dcn20_fpu_dcn21_update_bw_bounding_box_test_cases, +}; + +kunit_test_suites(&dcn20_fpu_test_suite, &dcn21_update_bw_bounding_box_tes= t_suite); --=20 2.37.3