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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id v62-20020a632f41000000b00430c6fd7ffbsm4705716pgv.84.2022.09.11.23.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Sep 2022 23:50:38 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v4 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Date: Mon, 12 Sep 2022 06:50:24 +0000 Message-Id: <20220912065029.1793-2-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220912065029.1793-1-zong.li@sifive.com> References: <20220912065029.1793-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li Suggested-by: Conor Dooley Suggested-by: Ben Dooks Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- ...five-l2-cache.yaml =3D> sifive,ccache0.yaml} | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml =3D> = sifive,ccache0.yaml} (83%) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b= /Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml similarity index 83% rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index ca3b9be58058..bf3f07421f7e 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -2,18 +2,18 @@ # Copyright (C) 2020 SiFive, Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: SiFive L2 Cache Controller +title: SiFive Composable Cache Controller =20 maintainers: - Sagar Kadam - Paul Walmsley =20 description: - The SiFive Level 2 Cache Controller is used to provide access to fast co= pies - of memory for masters in a Core Complex. The Level 2 Cache Controller al= so + The SiFive Composable Cache Controller is used to provide access to fast= copies + of memory for masters in a Core Complex. The Composable Cache Controller= also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this pl= atform. =20 @@ -22,6 +22,7 @@ select: compatible: contains: enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache =20 @@ -33,6 +34,7 @@ properties: oneOf: - items: - enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache - const: cache @@ -45,7 +47,7 @@ properties: const: 64 =20 cache-level: - const: 2 + enum: [2, 3] =20 cache-sets: enum: [1024, 2048] @@ -115,6 +117,22 @@ allOf: cache-sets: const: 1024 =20 + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + additionalProperties: false =20 required: --=20 2.17.1