From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA526ECAAD3 for ; Fri, 9 Sep 2022 19:36:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231178AbiIITgk (ORCPT ); Fri, 9 Sep 2022 15:36:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229690AbiIITgc (ORCPT ); Fri, 9 Sep 2022 15:36:32 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B23CC2AE33; Fri, 9 Sep 2022 12:36:30 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 456C9DBA; Fri, 9 Sep 2022 22:40:18 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 456C9DBA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752418; bh=Y7WwfSNSVFN6DsOTitXYalfVMtQs4BD5nZyMmYc6YaA=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=byxrOwQKUSaVkjsY4+AShszBhf69GjL1+2IvIB5D3rPggLK/WnHarHbIsqRDb/qJL v65ZQgcyp8TqHRghsBnurbKX4Gkz5K1GLJ1/vw6t+7isZHVguQHRSp4IyyBQuryDax Ux6u2YsIn4Qth1RKZoM0uLNVvwF+i0CBjbn2+vZU= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:29 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Rob Herring , Krzysztof Kozlowski , Florian Fainelli , Linus Walleij CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , , Rob Herring Subject: [PATCH v8 01/23] dt-bindings: ata: ahci-platform: Move dma-coherent to sata-common.yaml Date: Fri, 9 Sep 2022 22:35:59 +0300 Message-ID: <20220909193621.17380-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Seeing doubtfully any SATA device working without embedded DMA engine let's permit the device nodes being equipped with the dma-coherent property in case if the platform is capable of cache-coherent DMAs. As a side-effect we can drop the explicit dma-coherent property definition from the particular device schemas. Currently it concerns the Broadcom SATA AHCI controller only. Signed-off-by: Serge Semin Reviewed-by: Florian Fainelli Reviewed-by: Rob Herring --- Changelog v2: - This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel. Changelog v4: - Move the dma-coherent property to the sata-common.yaml schema instead of removing it. - Remove the Hannes' rb tag. --- Documentation/devicetree/bindings/ata/ahci-platform.yaml | 2 -- Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml | 2 -- Documentation/devicetree/bindings/ata/sata-common.yaml | 2 ++ 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Doc= umentation/devicetree/bindings/ata/ahci-platform.yaml index c146ab8e14e5..9304e4731965 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml @@ -87,8 +87,6 @@ properties: description: regulator for AHCI controller =20 - dma-coherent: true - phy-supply: description: regulator for PHY power diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml b/Do= cumentation/devicetree/bindings/ata/brcm,sata-brcm.yaml index 235a93ac86b0..4ee74df8e58a 100644 --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml @@ -41,8 +41,6 @@ properties: interrupts: maxItems: 1 =20 - dma-coherent: true - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/ata/sata-common.yaml b/Docum= entation/devicetree/bindings/ata/sata-common.yaml index 7ac77b1c5850..cb88d3e25e73 100644 --- a/Documentation/devicetree/bindings/ata/sata-common.yaml +++ b/Documentation/devicetree/bindings/ata/sata-common.yaml @@ -31,6 +31,8 @@ properties: "#size-cells": const: 0 =20 + dma-coherent: true + patternProperties: "^sata-port@[0-9a-e]$": description: | --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13150C6FA89 for ; Fri, 9 Sep 2022 19:37:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231602AbiIIThP (ORCPT ); Fri, 9 Sep 2022 15:37:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231200AbiIITgp (ORCPT ); Fri, 9 Sep 2022 15:36:45 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0276C2AE33; Fri, 9 Sep 2022 12:36:33 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 47FDEDBB; Fri, 9 Sep 2022 22:40:19 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 47FDEDBB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752419; bh=tUP+TC6hVDP8Bs3TtlKqKnuOaCO758BhT30UXUMVVrY=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=RZrxTmuINzrOofMv2jDk7xWPi0VtcaDJJf+Qy0ClhUsTxRdpqiJr+1YTWCo6oqo1S wL1YCJZcaAT8HdQJ8t5HiL0T/HWu9cnB63BM+VNbJ77KGgDj1UEby0y5YwBudYDHys gyoSMhuvmp8z0FGkEojBHh2FlQ6hWQdYoJqnjY48= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:30 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Rob Herring , Krzysztof Kozlowski , Linus Walleij CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , , Rob Herring Subject: [PATCH v8 02/23] dt-bindings: ata: ahci-platform: Detach common AHCI bindings Date: Fri, 9 Sep 2022 22:36:00 +0300 Message-ID: <20220909193621.17380-3-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to create a more sophisticated AHCI controller DT bindings let's divide the already available generic AHCI platform YAML schema into the platform part and a set of the common AHCI properties. The former part will be used to evaluate the AHCI DT nodes mainly compatible with the generic AHCI controller while the later schema will be used for more thorough AHCI DT nodes description. For instance such YAML schemas design will be useful for our DW AHCI SATA controller derivative with four clock sources, two reset lines, one system controller reference and specific max Rx/Tx DMA xfers size constraints. Note the phys and target-supply property requirement is preserved in the generic AHCI platform bindings because some platforms can lack of the explicitly specified PHYs or target device power regulators. Also note the SATA/AHCI ports properties have been moved to the $defs-paragraph of the schemas. It's done in order to create the extendable properties hierarchy such that particular AHCI-controller could add vendor-specific port properties. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Folks, I don't really see why the phys/target-supply requirement has been added to the generic AHCI DT schema in the first place. Probably just to imply some meaning for the sub-nodes definition. Anyway in one of the further patches I am adding the DW AHCI SATA controller DT bindings which won't require having these properties specified in the sub-nodes, but will describe additional port-specific properties. That's why I get to keep the constraints in the ahci-platform.yaml schema instead of moving them to the common schema. Changelog v2: - This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel. Changelog v3: - Replace Jens's email address with Damien's one in the list of the schema maintainers. (@Damien) Changelog v4: - Drop clocks, clock-names, resets, reset-names and power-domains properties from the common schema. (@Rob) - Create sata/ahci-port properties definition hierarchy so the sub-schemas would inherit and extend the ports properties of the super-schema. (@Rob) --- .../devicetree/bindings/ata/ahci-common.yaml | 100 ++++++++++++++++++ .../bindings/ata/ahci-platform.yaml | 72 ++----------- .../devicetree/bindings/ata/sata-common.yaml | 8 +- 3 files changed, 115 insertions(+), 65 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/ahci-common.yaml diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Docum= entation/devicetree/bindings/ata/ahci-common.yaml new file mode 100644 index 000000000000..e89bda3b62cc --- /dev/null +++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/ahci-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Serial ATA AHCI controllers + +maintainers: + - Hans de Goede + - Damien Le Moal + +description: + This document defines device tree properties for a common AHCI SATA + controller implementation. It's hardware interface is supposed to + conform to the technical standard defined by Intel (see Serial ATA + Advanced Host Controller Interface specification for details). The + document doesn't constitute a DT-node binding by itself but merely + defines a set of common properties for the AHCI-compatible devices. + +select: false + +allOf: + - $ref: sata-common.yaml# + +properties: + reg: + description: + Generic AHCI registers space conforming to the Serial ATA AHCI + specification. + + reg-names: + description: CSR space IDs + + interrupts: + description: + Generic AHCI state change interrupt. Can be implemented either as a + single line attached to the controller or as a set of the signals + indicating the particular port events. + + ahci-supply: + description: Power regulator for AHCI controller + + target-supply: + description: Power regulator for SATA target device + + phy-supply: + description: Power regulator for SATA PHY + + phys: + description: Reference to the SATA PHY node + maxItems: 1 + + phy-names: + maxItems: 1 + + ports-implemented: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + Mask that indicates which ports the HBA supports. Useful if PI is not + programmed by the BIOS, which is true for some embedded SoC's. + maximum: 0x1f + +patternProperties: + "^sata-port@[0-9a-f]+$": + $ref: '#/$defs/ahci-port' + description: + It is optionally possible to describe the ports as sub-nodes so + to enable each port independently when dealing with multiple PHYs. + +required: + - reg + - interrupts + +additionalProperties: true + +$defs: + ahci-port: + $ref: /schemas/ata/sata-common.yaml#/$defs/sata-port + + properties: + reg: + description: AHCI SATA port identifier + maxItems: 1 + + phys: + description: Individual AHCI SATA port PHY + maxItems: 1 + + phy-names: + description: AHCI SATA port PHY ID + maxItems: 1 + + target-supply: + description: Power regulator for SATA port target device + + required: + - reg + +... diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Doc= umentation/devicetree/bindings/ata/ahci-platform.yaml index 9304e4731965..15be98e0385b 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml @@ -36,8 +36,7 @@ select: - compatible =20 allOf: - - $ref: "sata-common.yaml#" - + - $ref: "ahci-common.yaml#" =20 properties: compatible: @@ -69,90 +68,37 @@ properties: maxItems: 1 =20 clocks: - description: - Clock IDs array as required by the controller. minItems: 1 maxItems: 3 =20 clock-names: - description: - Names of clocks corresponding to IDs in the clock property. minItems: 1 maxItems: 3 =20 interrupts: maxItems: 1 =20 - ahci-supply: - description: - regulator for AHCI controller - - phy-supply: - description: - regulator for PHY power - - phys: - description: - List of all PHYs on this controller - maxItems: 1 - - phy-names: - description: - Name specifier for the PHYs - maxItems: 1 - - ports-implemented: - $ref: '/schemas/types.yaml#/definitions/uint32' - description: | - Mask that indicates which ports that the HBA supports - are available for software to use. Useful if PORTS_IMPL - is not programmed by the BIOS, which is true with - some embedded SoCs. - maximum: 0x1f - power-domains: maxItems: 1 =20 resets: maxItems: 1 =20 - target-supply: - description: - regulator for SATA target power - -required: - - compatible - - reg - - interrupts - patternProperties: "^sata-port@[0-9a-f]+$": - type: object - additionalProperties: false - description: - Subnode with configuration of the Ports. - - properties: - reg: - maxItems: 1 - - phys: - maxItems: 1 - - phy-names: - maxItems: 1 - - target-supply: - description: - regulator for SATA target power - - required: - - reg + $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port =20 anyOf: - required: [ phys ] - required: [ target-supply ] =20 + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + unevaluatedProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/ata/sata-common.yaml b/Docum= entation/devicetree/bindings/ata/sata-common.yaml index cb88d3e25e73..5a31a902618d 100644 --- a/Documentation/devicetree/bindings/ata/sata-common.yaml +++ b/Documentation/devicetree/bindings/ata/sata-common.yaml @@ -35,9 +35,15 @@ properties: =20 patternProperties: "^sata-port@[0-9a-e]$": + $ref: '#/$defs/sata-port' description: | DT nodes for ports connected on the SATA host. The SATA port nodes will be named "sata-port". + +additionalProperties: true + +$defs: + sata-port: type: object =20 properties: @@ -49,6 +55,4 @@ patternProperties: multiplier making it possible to connect up to 15 disks to a sin= gle SATA port. =20 -additionalProperties: true - ... --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33197ECAAD3 for ; Fri, 9 Sep 2022 19:36:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231204AbiIITgp (ORCPT ); Fri, 9 Sep 2022 15:36:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230268AbiIITgg (ORCPT ); Fri, 9 Sep 2022 15:36:36 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3EC7710B022; Fri, 9 Sep 2022 12:36:34 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id EA7E6DBC; Fri, 9 Sep 2022 22:40:19 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com EA7E6DBC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752419; bh=atwOSwDRSOTca1rVnY7Q+fsngIpvJLTucuiF7rHU128=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=MLvG8BV9RsPBBTcLnEFxs9GS4aE3iB43LYI+BOStHDlT1eOe83FWkmGoHZdh1uPbM m3C5KRo+keA9FF1bmuyLrC/OqDGP2doxWi7YX4qSfg2psb90QN1ZSpnO4g+ITJpvEi 5hi16HwbXxoLmGLVWYkE1bKgJfF5jbsgJ3dGOfAQ= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:31 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Rob Herring , Krzysztof Kozlowski CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , , Rob Herring Subject: [PATCH v8 03/23] dt-bindings: ata: ahci-platform: Clarify common AHCI props constraints Date: Fri, 9 Sep 2022 22:36:01 +0300 Message-ID: <20220909193621.17380-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Indeed in accordance with what is implemented in the AHCI platform driver and the way the AHCI DT nodes are defined in the DT files we can add the next AHCI DT properties constraints: AHCI CSR ID is fixed to 'ahci', PHY name is fixed to 'sata-phy', AHCI controller can't have more than 32 ports by design, AHCI controller can have up to 32 IRQ lines. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke Reviewed-by: Rob Herring --- Changelog v2: - This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel. Changelog v4: - Fix spelling: 'imeplemtned' and 'paltform' in the patch log. (@Hannes) - Add the interrupts property constraints. (@Rob) - Add forgotten '---' patchlog-changelog separator. (@Sergei) --- .../devicetree/bindings/ata/ahci-common.yaml | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Docum= entation/devicetree/bindings/ata/ahci-common.yaml index e89bda3b62cc..12a97b56226f 100644 --- a/Documentation/devicetree/bindings/ata/ahci-common.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml @@ -31,12 +31,16 @@ properties: =20 reg-names: description: CSR space IDs + contains: + const: ahci =20 interrupts: description: Generic AHCI state change interrupt. Can be implemented either as a single line attached to the controller or as a set of the signals indicating the particular port events. + minItems: 1 + maxItems: 32 =20 ahci-supply: description: Power regulator for AHCI controller @@ -52,14 +56,13 @@ properties: maxItems: 1 =20 phy-names: - maxItems: 1 + const: sata-phy =20 ports-implemented: $ref: '/schemas/types.yaml#/definitions/uint32' description: Mask that indicates which ports the HBA supports. Useful if PI is not programmed by the BIOS, which is true for some embedded SoC's. - maximum: 0x1f =20 patternProperties: "^sata-port@[0-9a-f]+$": @@ -80,8 +83,12 @@ $defs: =20 properties: reg: - description: AHCI SATA port identifier - maxItems: 1 + description: + AHCI SATA port identifier. By design AHCI controller can't have + more than 32 ports due to the CAP.NP fields and PI register size + constraints. + minimum: 0 + maximum: 31 =20 phys: description: Individual AHCI SATA port PHY @@ -89,7 +96,7 @@ $defs: =20 phy-names: description: AHCI SATA port PHY ID - maxItems: 1 + const: sata-phy =20 target-supply: description: Power regulator for SATA port target device --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A143ECAAA1 for ; Fri, 9 Sep 2022 19:37:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231626AbiIIThU (ORCPT ); Fri, 9 Sep 2022 15:37:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231243AbiIITgq (ORCPT ); Fri, 9 Sep 2022 15:36:46 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7C0DA11213D; Fri, 9 Sep 2022 12:36:35 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 9AF04DBD; Fri, 9 Sep 2022 22:40:20 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 9AF04DBD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752420; bh=d2GPchrpvVOgjuEOQF2EanFTi3kLUr78uJWuPrwrf50=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=pW1qm12n8TUUoawpbk1GHwTl7ZL6XeNLE+u6nnBBKX2P+ZZdeet8dv5w/59D7y3Gh do78eRjnqamBaheNS0BIm13HV5q4E9BEMmt02mLfLBGpnGGWL2gqiMAIQUCIN1EZ+v /JVaQOCa7r96dtDm4HpDcVK3rfej96wkBhILC2Dw= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:32 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Rob Herring , Krzysztof Kozlowski , Linus Walleij CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , , Rob Herring Subject: [PATCH v8 04/23] dt-bindings: ata: sata: Extend number of SATA ports Date: Fri, 9 Sep 2022 22:36:02 +0300 Message-ID: <20220909193621.17380-5-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The denoted in the description upper limit only concerns the Port Multipliers, but not the actual SATA ports. It's an external device attached to a SATA port in order to access more than one SATA-drive. So when it's attached to a SATA port it just extends the port capability while the number of actual SATA ports stays the same. For instance on AHCI controllers the number of actual ports is determined by the CAP.NP field and the PI (Ports Implemented) register. AFAICS in general the maximum number of SATA ports depends on the particular controller implementation. Generic AHCI controller can't have more than 32 ports (since CAP.NP is of 5 bits wide and PI register is 32-bits size), while DWC AHCI SATA controller can't be configured with more than 8 ports activated. So let's discard the SATA ports reg-property restrictions and just make sure that it consists of a single reg-item. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke Reviewed-by: Rob Herring --- Changelog v2: - Add comma and replace "channel" with "SATA port" in the reg property description (@Damien). --- Documentation/devicetree/bindings/ata/sata-common.yaml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/sata-common.yaml b/Docum= entation/devicetree/bindings/ata/sata-common.yaml index 5a31a902618d..58c9342b9925 100644 --- a/Documentation/devicetree/bindings/ata/sata-common.yaml +++ b/Documentation/devicetree/bindings/ata/sata-common.yaml @@ -49,10 +49,9 @@ $defs: properties: reg: minimum: 0 - maximum: 14 description: - The ID number of the drive port SATA can potentially use a port - multiplier making it possible to connect up to 15 disks to a sin= gle - SATA port. + The ID number of the SATA port. Aside with being directly used, + each port can have a Port Multiplier attached thus allowing to + access more than one drive by means of a single SATA port. =20 ... --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90F18ECAAD5 for ; Fri, 9 Sep 2022 19:37:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231467AbiIIThD (ORCPT ); Fri, 9 Sep 2022 15:37:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230436AbiIITgj (ORCPT ); Fri, 9 Sep 2022 15:36:39 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1A3B01153BB; Fri, 9 Sep 2022 12:36:37 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 6602ADBE; Fri, 9 Sep 2022 22:40:21 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 6602ADBE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752421; bh=wYx4YZQxrd0X1DNHR+uvu1prpgP1TFhOgzBZNgxVtkg=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=ISH/lFNkRqQ0b2n9GqTdZQoZ0TN34V0kKKFH2GI5krA5iuCV7qhvwbY5i0in2OO0c 5D8yRBgaxdaaqM4oTUvkKvxzRyig7m+A1JzMkSCCe5ZU983wfMWAiZPITJzPllxh3g nIq8uxfqUDODAlPeWIPOi5yRvggpRRAep+bFNNP0= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:32 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Rob Herring , Krzysztof Kozlowski , Florian Fainelli CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , , Rob Herring Subject: [PATCH v8 05/23] dt-bindings: ata: sata-brcm: Apply common AHCI schema Date: Fri, 9 Sep 2022 22:36:03 +0300 Message-ID: <20220909193621.17380-6-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Broadcom SATA controller is obviously based on the AHCI standard. The device driver uses the kernel AHCI library to work with it. Therefore we can be have a more thorough DT-bindings evaluation by referring to the AHCI-common schema instead of using the more relaxed SATA-common one. Signed-off-by: Serge Semin Reviewed-by: Florian Fainelli Reviewed-by: Rob Herring --- Changelog v4: - This is a new patch added on v4 lap of the review procedure. --- Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml b/Do= cumentation/devicetree/bindings/ata/brcm,sata-brcm.yaml index 4ee74df8e58a..fa8ebc8f243f 100644 --- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml +++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml @@ -14,7 +14,7 @@ maintainers: - Florian Fainelli =20 allOf: - - $ref: sata-common.yaml# + - $ref: ahci-common.yaml# =20 properties: compatible: --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B7D9ECAAD3 for ; Fri, 9 Sep 2022 19:37:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231636AbiIIThY (ORCPT ); Fri, 9 Sep 2022 15:37:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230268AbiIITgu (ORCPT ); Fri, 9 Sep 2022 15:36:50 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D789D115CE3; Fri, 9 Sep 2022 12:36:37 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 27E3FDBF; Fri, 9 Sep 2022 22:40:22 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 27E3FDBF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752422; bh=4UEvOJBnrhYbJMOH5dIhZYkkbJ2g80CrYqwa/ZKcSYU=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=PuI+Re6LN1febwr8DWRC0N7Vh/Z6Olj+NKDllbtqHnTPgdUnqdjDaIBA608in6QIS +6lx0LYqvn+sdfBUgmoYj2NSYvq9x0w4g6bTXl6ogVkgNqenHF4WdHU0ftgjvlrxCM p0yOA7DYXbv+cA4gEgl1urShyqqMTVUjK3JcpcK8= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:33 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 06/23] ata: libahci_platform: Convert to using platform devm-ioremap methods Date: Fri, 9 Sep 2022 22:36:04 +0300 Message-ID: <20220909193621.17380-7-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently the IOMEM AHCI registers space is mapped by means of the two functions invocation: platform_get_resource() is used to get the very first memory resource and devm_ioremap_resource() is called to remap that resource. Device-managed kernel API provides a handy wrapper to perform the same in single function call: devm_platform_ioremap_resource(). While at it seeing many AHCI platform drivers rely on having the AHCI CSR space marked with "ahci" name let's first try to find and remap the CSR IO-mem with that name and only if it fails fallback to getting the very first registers space platform resource. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- Changelog v2: - Check whether there is "ahci" reg resource before using the devm_platform_ioremap_resource_byname() method in order to prevent a false error message printed in the log (@Damien) - Slightly update the patch title due to the change above and to be more specific about what the platform device managed methods are utilized for. --- drivers/ata/libahci_platform.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 32495ae96567..1e9e825d6cc5 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -402,8 +402,14 @@ struct ahci_host_priv *ahci_platform_get_resources(str= uct platform_device *pdev, =20 devres_add(dev, hpriv); =20 - hpriv->mmio =3D devm_ioremap_resource(dev, - platform_get_resource(pdev, IORESOURCE_MEM, 0)); + /* + * If the DT provided an "ahci" named resource, use it. Otherwise, + * fallback to using the default first resource for the device node. + */ + if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci")) + hpriv->mmio =3D devm_platform_ioremap_resource_byname(pdev, "ahci"); + else + hpriv->mmio =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hpriv->mmio)) { rc =3D PTR_ERR(hpriv->mmio); goto err_out; --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51E64ECAAA1 for ; Fri, 9 Sep 2022 19:37:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231515AbiIIThK (ORCPT ); Fri, 9 Sep 2022 15:37:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230280AbiIITgk (ORCPT ); Fri, 9 Sep 2022 15:36:40 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CD5A9116B47; Fri, 9 Sep 2022 12:36:38 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 69B28DB9; Fri, 9 Sep 2022 22:40:23 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 69B28DB9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752423; bh=dv1QJRPjCBsNnk5G5B5h+UHLLXCKncnGGtihof8xnGU=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=rKvVP/jcbj9gz0ADtejhJUsBqIdm9vTt8QFE0bXvsMRspEBTxT6n8H8mU+V5m848A Q/kqdUIRmUoQvSQJfRkHZncJaMpvP03VhanGTHsKpLQfzWhYJFOdzvS0AoUK+ajH5s dG64g2tDCkCNwW2GeXDzGe+EWvDDfA/NpAu7Fw+g= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:34 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 07/23] ata: libahci_platform: Convert to using devm bulk clocks API Date: Fri, 9 Sep 2022 22:36:05 +0300 Message-ID: <20220909193621.17380-8-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to simplify the clock-related code there is a way to convert the current fixed clocks array into using the common bulk clocks kernel API with dynamic set of the clock handlers and device-managed clock-resource tracking. It's a bit tricky due to the complication coming from the requirement to support the platforms (da850, spear13xx) with the non-OF-based clock source, but still doable. Before this modification there are two methods have been used to get the clocks connected to an AHCI device: clk_get() - to get the very first clock in the list and of_clk_get() - to get the rest of them. Basically the platforms with non-OF-based clocks definition could specify only a single reference clock source. The platforms with OF-hw clocks have been luckier and could setup up to AHCI_MAX_CLKS clocks. Such semantic can be retained with using devm_clk_bulk_get_all() to retrieve the clocks defined via the DT firmware and devm_clk_get_optional() otherwise. In both cases using the device-managed version of the methods will cause the automatic resources deallocation on the AHCI device removal event. The only complicated part in the suggested approach is the explicit allocation and initialization of the clk_bulk_data structure instance for the non-OF reference clocks. It's required in order to use the Bulk Clocks API for the both denoted cases of the clocks definition. Note aside with the clock-related code reduction and natural simplification, there are several bonuses the suggested modification provides. First of all the limitation of having no greater than AHCI_MAX_CLKS clocks is now removed, since the devm_clk_bulk_get_all() method will allocate as many reference clocks data descriptors as there are clocks specified for the device. Secondly the clock names are auto-detected. So the LLDD (glue) drivers can make sure that the required clocks are specified just by checking the clock IDs in the clk_bulk_data array. Thirdly using the handy Bulk Clocks kernel API improves the clocks-handling code readability. And the last but not least this modification implements a true optional clocks support to the ahci_platform_get_resources() method. Indeed the previous clocks getting procedure just stopped getting the clocks on any errors (aside from non-critical -EPROBE_DEFER) in a way so the callee wasn't even informed about abnormal loop termination. The new implementation lacks of such problem. The ahci_platform_get_resources() will return an error code if the corresponding clocks getting method ends execution abnormally. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- Changelog v2: - Convert to checking the error-case first in the devm_clk_bulk_get_all() method invocation. (@Damien) - Fix some grammar mistakes in the comments. Changelog v7: - Fix Davinci DA850 and Omap2 DM816 AHCI LLDD to be using the new bulk clocks interface. Changelog v8: - Replace __clk_get_name() call with static string "ahci". (@Damien, @tbot) --- drivers/ata/ahci.h | 4 +- drivers/ata/ahci_da850.c | 47 ++++++++----------- drivers/ata/ahci_dm816.c | 4 +- drivers/ata/libahci_platform.c | 83 ++++++++++++++++------------------ 4 files changed, 61 insertions(+), 77 deletions(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index ad11a4c52fbe..c3770a19781b 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -38,7 +38,6 @@ =20 enum { AHCI_MAX_PORTS =3D 32, - AHCI_MAX_CLKS =3D 5, AHCI_MAX_SG =3D 168, /* hardware max is 64K */ AHCI_DMA_BOUNDARY =3D 0xffffffff, AHCI_MAX_CMDS =3D 32, @@ -339,7 +338,8 @@ struct ahci_host_priv { u32 em_msg_type; /* EM message type */ u32 remapped_nvme; /* NVMe remapped device count */ bool got_runtime_pm; /* Did we do pm_runtime_get? */ - struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ + unsigned int n_clks; + struct clk_bulk_data *clks; /* Optional */ struct reset_control *rsts; /* Optional */ struct regulator **target_pwrs; /* Optional */ struct regulator *ahci_regulator;/* Optional */ diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c index 052c28e250aa..dc8a019b8340 100644 --- a/drivers/ata/ahci_da850.c +++ b/drivers/ata/ahci_da850.c @@ -163,7 +163,6 @@ static int ahci_da850_probe(struct platform_device *pde= v) struct ahci_host_priv *hpriv; void __iomem *pwrdn_reg; struct resource *res; - struct clk *clk; u32 mpy; int rc; =20 @@ -172,36 +171,28 @@ static int ahci_da850_probe(struct platform_device *p= dev) return PTR_ERR(hpriv); =20 /* - * Internally ahci_platform_get_resources() calls clk_get(dev, NULL) - * when trying to obtain the functional clock. This SATA controller - * uses two clocks for which we specify two connection ids. If we don't - * have the functional clock at this point - call clk_get() again with - * con_id =3D "fck". + * Internally ahci_platform_get_resources() calls the bulk clocks + * get method or falls back to using a single clk_get_optional(). + * This AHCI SATA controller uses two clocks: functional clock + * with "fck" connection id and external reference clock with + * "refclk" id. If we haven't got all of them re-try the clocks + * getting procedure with the explicitly specified ids. */ - if (!hpriv->clks[0]) { - clk =3D clk_get(dev, "fck"); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - hpriv->clks[0] =3D clk; - } - - /* - * The second clock used by ahci-da850 is the external REFCLK. If we - * didn't get it from ahci_platform_get_resources(), let's try to - * specify the con_id in clk_get(). - */ - if (!hpriv->clks[1]) { - clk =3D clk_get(dev, "refclk"); - if (IS_ERR(clk)) { - dev_err(dev, "unable to obtain the reference clock"); - return -ENODEV; - } - - hpriv->clks[1] =3D clk; + if (hpriv->n_clks < 2) { + hpriv->clks =3D devm_kcalloc(dev, 2, sizeof(*hpriv->clks), GFP_KERNEL); + if (!hpriv->clks) + return -ENOMEM; + + hpriv->clks[0].id =3D "fck"; + hpriv->clks[1].id =3D "refclk"; + hpriv->n_clks =3D 2; + + rc =3D devm_clk_bulk_get(dev, hpriv->n_clks, hpriv->clks); + if (rc) + return rc; } =20 - mpy =3D ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1])); + mpy =3D ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1].clk)); if (mpy =3D=3D 0) { dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy); return -EINVAL; diff --git a/drivers/ata/ahci_dm816.c b/drivers/ata/ahci_dm816.c index 8a92112dcd59..d26efcd20f64 100644 --- a/drivers/ata/ahci_dm816.c +++ b/drivers/ata/ahci_dm816.c @@ -69,12 +69,12 @@ static int ahci_dm816_phy_init(struct ahci_host_priv *h= priv, struct device *dev) * keep-alive clock and the external reference clock. We need the * rate of the latter to calculate the correct value of MPY bits. */ - if (!hpriv->clks[1]) { + if (hpriv->n_clks < 2) { dev_err(dev, "reference clock not supplied\n"); return -EINVAL; } =20 - refclk_rate =3D clk_get_rate(hpriv->clks[1]); + refclk_rate =3D clk_get_rate(hpriv->clks[1].clk); if ((refclk_rate % 100) !=3D 0) { dev_err(dev, "reference clock rate must be divisible by 100\n"); return -EINVAL; diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 1e9e825d6cc5..7366eb0adf41 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -97,28 +97,14 @@ EXPORT_SYMBOL_GPL(ahci_platform_disable_phys); * ahci_platform_enable_clks - Enable platform clocks * @hpriv: host private area to store config values * - * This function enables all the clks found in hpriv->clks, starting at - * index 0. If any clk fails to enable it disables all the clks already - * enabled in reverse order, and then returns an error. + * This function enables all the clks found for the AHCI device. * * RETURNS: * 0 on success otherwise a negative error code */ int ahci_platform_enable_clks(struct ahci_host_priv *hpriv) { - int c, rc; - - for (c =3D 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++) { - rc =3D clk_prepare_enable(hpriv->clks[c]); - if (rc) - goto disable_unprepare_clk; - } - return 0; - -disable_unprepare_clk: - while (--c >=3D 0) - clk_disable_unprepare(hpriv->clks[c]); - return rc; + return clk_bulk_prepare_enable(hpriv->n_clks, hpriv->clks); } EXPORT_SYMBOL_GPL(ahci_platform_enable_clks); =20 @@ -126,16 +112,13 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_clks); * ahci_platform_disable_clks - Disable platform clocks * @hpriv: host private area to store config values * - * This function disables all the clks found in hpriv->clks, in reverse - * order of ahci_platform_enable_clks (starting at the end of the array). + * This function disables all the clocks enabled before + * (bulk-clocks-disable function is supposed to do that in reverse + * from the enabling procedure order). */ void ahci_platform_disable_clks(struct ahci_host_priv *hpriv) { - int c; - - for (c =3D AHCI_MAX_CLKS - 1; c >=3D 0; c--) - if (hpriv->clks[c]) - clk_disable_unprepare(hpriv->clks[c]); + clk_bulk_disable_unprepare(hpriv->n_clks, hpriv->clks); } EXPORT_SYMBOL_GPL(ahci_platform_disable_clks); =20 @@ -292,8 +275,6 @@ static void ahci_platform_put_resources(struct device *= dev, void *res) pm_runtime_disable(dev); } =20 - for (c =3D 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++) - clk_put(hpriv->clks[c]); /* * The regulators are tied to child node device and not to the * SATA device itself. So we can't use devm for automatically @@ -374,8 +355,8 @@ static int ahci_platform_get_regulator(struct ahci_host= _priv *hpriv, u32 port, * 1) mmio registers (IORESOURCE_MEM 0, mandatory) * 2) regulator for controlling the targets power (optional) * regulator for controlling the AHCI controller (optional) - * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node, - * or for non devicetree enabled platforms a single clock + * 3) all clocks specified in the devicetree node, or a single + * clock for non-OF platforms (optional) * 4) resets, if flags has AHCI_PLATFORM_GET_RESETS (optional) * 5) phys (optional) * @@ -385,11 +366,10 @@ static int ahci_platform_get_regulator(struct ahci_ho= st_priv *hpriv, u32 port, struct ahci_host_priv *ahci_platform_get_resources(struct platform_device = *pdev, unsigned int flags) { + int child_nodes, rc =3D -ENOMEM, enabled_ports =3D 0; struct device *dev =3D &pdev->dev; struct ahci_host_priv *hpriv; - struct clk *clk; struct device_node *child; - int i, enabled_ports =3D 0, rc =3D -ENOMEM, child_nodes; u32 mask_port_map =3D 0; =20 if (!devres_open_group(dev, NULL, GFP_KERNEL)) @@ -415,25 +395,38 @@ struct ahci_host_priv *ahci_platform_get_resources(st= ruct platform_device *pdev, goto err_out; } =20 - for (i =3D 0; i < AHCI_MAX_CLKS; i++) { + /* + * Bulk clocks getting procedure can fail to find any clock due to + * running on a non-OF platform or due to the clocks being defined in + * bypass of the DT firmware (like da850, spear13xx). In that case we + * fallback to getting a single clock source right from the dev clocks + * list. + */ + rc =3D devm_clk_bulk_get_all(dev, &hpriv->clks); + if (rc < 0) + goto err_out; + + if (rc > 0) { + /* Got clocks in bulk */ + hpriv->n_clks =3D rc; + } else { /* - * For now we must use clk_get(dev, NULL) for the first clock, - * because some platforms (da850, spear13xx) are not yet - * converted to use devicetree for clocks. For new platforms - * this is equivalent to of_clk_get(dev->of_node, 0). + * No clock bulk found: fallback to manually getting + * the optional clock. */ - if (i =3D=3D 0) - clk =3D clk_get(dev, NULL); - else - clk =3D of_clk_get(dev->of_node, i); - - if (IS_ERR(clk)) { - rc =3D PTR_ERR(clk); - if (rc =3D=3D -EPROBE_DEFER) - goto err_out; - break; + hpriv->clks =3D devm_kzalloc(dev, sizeof(*hpriv->clks), GFP_KERNEL); + if (!hpriv->clks) { + rc =3D -ENOMEM; + goto err_out; + } + hpriv->clks->clk =3D devm_clk_get_optional(dev, NULL); + if (IS_ERR(hpriv->clks->clk)) { + rc =3D PTR_ERR(hpriv->clks->clk); + goto err_out; + } else if (hpriv->clks->clk) { + hpriv->clks->id =3D "ahci"; + hpriv->n_clks =3D 1; } - hpriv->clks[i] =3D clk; } =20 hpriv->ahci_regulator =3D devm_regulator_get(dev, "ahci"); --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09D4BC6FA8B for ; Fri, 9 Sep 2022 19:37:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231787AbiIIThz (ORCPT ); Fri, 9 Sep 2022 15:37:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231484AbiIIThF (ORCPT ); Fri, 9 Sep 2022 15:37:05 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E4BC8112130; Fri, 9 Sep 2022 12:36:39 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 0FC8ADBA; Fri, 9 Sep 2022 22:40:24 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 0FC8ADBA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752424; bh=MxJlAieoI0TgAMq3MnhprrteEcvbjMxPRTOKIFXhakY=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=YhISV66IKakezX9NkxCY8cApL5mYwmnlSg+h2QstlTvJow+OlTfgQrOeIQycNK5h0 5ZLJQZVqTLRy73Gef4BsZa2f7kXpYs5D7/IvGjhD6f5gyWjQgRK6DGaliJvLjWzyZo YJPfU6X3uWiA3s+0Hot5D6C3Jdng3GPOPhWcejos= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:35 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 08/23] ata: libahci_platform: Sanity check the DT child nodes number Date: Fri, 9 Sep 2022 22:36:06 +0300 Message-ID: <20220909193621.17380-9-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Having greater than AHCI_MAX_PORTS (32) ports detected isn't that critical from the further AHCI-platform initialization point of view since exceeding the ports upper limit will cause allocating more resources than will be used afterwards. But detecting too many child DT-nodes doesn't seem right since it's very unlikely to have it on an ordinary platform. In accordance with the AHCI specification there can't be more than 32 ports implemented at least due to having the CAP.NP field of 5 bits wide and the PI register of dword size. Thus if such situation is found the DTB must have been corrupted and the data read from it shouldn't be reliable. Let's consider that as an erroneous situation and halt further resources allocation. Note it's logically more correct to have the nports set only after the initialization value is checked for being sane. So while at it let's make sure nports is assigned with a correct value. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- Changelog v2: - Drop the else word from the child_nodes value checking if-else-if statement (@Damien) and convert the after-else part into the ternary operator-based statement. Changelog v4: - Fix some logical mistakes in the patch log. (@Sergei Shtylyov) - Replace "?:" operator with if-else statement. (@Damien) --- drivers/ata/libahci_platform.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 7366eb0adf41..bacb974c1b16 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -450,14 +450,24 @@ struct ahci_host_priv *ahci_platform_get_resources(st= ruct platform_device *pdev, } } =20 - hpriv->nports =3D child_nodes =3D of_get_child_count(dev->of_node); + /* + * Too many sub-nodes most likely means having something wrong with + * the firmware. + */ + child_nodes =3D of_get_child_count(dev->of_node); + if (child_nodes > AHCI_MAX_PORTS) { + rc =3D -EINVAL; + goto err_out; + } =20 /* * If no sub-node was found, we still need to set nports to * one in order to be able to use the * ahci_platform_[en|dis]able_[phys|regulators] functions. */ - if (!child_nodes) + if (child_nodes) + hpriv->nports =3D child_nodes; + else hpriv->nports =3D 1; =20 hpriv->phys =3D devm_kcalloc(dev, hpriv->nports, sizeof(*hpriv->phys), GF= P_KERNEL); --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E42AECAAD3 for ; Fri, 9 Sep 2022 19:37:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231659AbiIITh3 (ORCPT ); Fri, 9 Sep 2022 15:37:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231269AbiIITg7 (ORCPT ); Fri, 9 Sep 2022 15:36:59 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 777A5114A65; Fri, 9 Sep 2022 12:36:41 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 0E152DC0; Fri, 9 Sep 2022 22:40:25 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 0E152DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752425; bh=rhrnZSbWpC1+1M+RgTKZFn+aypUJXi4N7nzDSxZUsFI=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=X1RgDR7uBneTQoIDep2jJUEo9CCjeOOta0eN3C0t+s9oksDoa/hc5XjEHFo986btS GQ8+NfzEKF/dc4GRQG8N6zUeDvO385oY84GPutS5oXYG65TvoeDDGnTPheVogbuwGv Z26tuO6krIsRSLJsuZUgBNBMftqtOGYtSFJ3fJ2A= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:36 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Matthias Brugger , Patrice Chotard CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , , , Subject: [PATCH v8 09/23] ata: libahci_platform: Parse ports-implemented property in resources getter Date: Fri, 9 Sep 2022 22:36:07 +0300 Message-ID: <20220909193621.17380-10-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ports-implemented property is mainly used on the OF-based platforms with no ports mapping initialized by a bootloader/BIOS firmware. Seeing the same of_property_read_u32()-based pattern has already been implemented in the generic AHCI LLDD (glue) driver and in the Mediatek, St AHCI drivers let's move the property read procedure to the generic ahci_platform_get_resources() method. Thus we'll have the forced ports mapping feature supported for each OF-based platform which requires that, and stop re-implementing the same pattern in there a bit simplifying the code. Signed-off-by: Serge Semin --- drivers/ata/ahci_mtk.c | 2 -- drivers/ata/ahci_platform.c | 3 --- drivers/ata/ahci_st.c | 3 --- drivers/ata/libahci_platform.c | 3 +++ 4 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c index 1f6c85fde983..c056378e3e72 100644 --- a/drivers/ata/ahci_mtk.c +++ b/drivers/ata/ahci_mtk.c @@ -118,8 +118,6 @@ static int mtk_ahci_parse_property(struct ahci_host_pri= v *hpriv, SYS_CFG_SATA_EN); } =20 - of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map); - return 0; } =20 diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c index 28a8de5b48b9..9b56490ecbc3 100644 --- a/drivers/ata/ahci_platform.c +++ b/drivers/ata/ahci_platform.c @@ -56,9 +56,6 @@ static int ahci_probe(struct platform_device *pdev) if (rc) return rc; =20 - of_property_read_u32(dev->of_node, - "ports-implemented", &hpriv->force_port_map); - if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci")) hpriv->flags |=3D AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; =20 diff --git a/drivers/ata/ahci_st.c b/drivers/ata/ahci_st.c index 7526653c843b..068621099c00 100644 --- a/drivers/ata/ahci_st.c +++ b/drivers/ata/ahci_st.c @@ -168,9 +168,6 @@ static int st_ahci_probe(struct platform_device *pdev) =20 st_ahci_configure_oob(hpriv->mmio); =20 - of_property_read_u32(dev->of_node, - "ports-implemented", &hpriv->force_port_map); - err =3D ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info, &ahci_platform_sht); if (err) { diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index bacb974c1b16..085f99b2eb5a 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -485,6 +485,9 @@ struct ahci_host_priv *ahci_platform_get_resources(stru= ct platform_device *pdev, goto err_out; } =20 + of_property_read_u32(dev->of_node, + "ports-implemented", &hpriv->force_port_map); + if (child_nodes) { for_each_child_of_node(dev->of_node, child) { u32 port; --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72FF6ECAAD3 for ; Fri, 9 Sep 2022 19:38:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231799AbiIITh7 (ORCPT ); Fri, 9 Sep 2022 15:37:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231490AbiIIThF (ORCPT ); Fri, 9 Sep 2022 15:37:05 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5485D117791; Fri, 9 Sep 2022 12:36:43 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id EE922DBD; Fri, 9 Sep 2022 22:40:25 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com EE922DBD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752425; bh=eX59xZ6l42ON030TF9xeyHb/pqfH9g8/ygT2gyZcpvg=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=F/lUTUrMkD63Nrd/mzpajNi/6nmMFWYh2v+U1yigNfy0ZLeoVaaAX63tVynSfuB/0 8VWeSPB1swDXHYz5hdRM8j+LjzBq0h+Kz+e032/tuGOCy0twUoBFWgdkjS4zf8eNL0 keMIGOGuyW935qCA80W6HX1Tq2nfKLyHikcMgGWY= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:37 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 10/23] ata: libahci_platform: Introduce reset assertion/deassertion methods Date: Fri, 9 Sep 2022 22:36:08 +0300 Message-ID: <20220909193621.17380-11-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently the ACHI-platform library supports only the assert and deassert reset signals and ignores the platforms with self-deasserting reset lines. That prone to having the platforms with self-deasserting reset method misbehaviour when it comes to resuming from sleep state after the clocks have been fully disabled. For such cases the controller needs to be fully reset all over after the reference clocks are enabled and stable, otherwise the controller state machine might be in an undetermined state. The best solution would be to auto-detect which reset method is supported by the particular platform and use it implicitly in the framework of the ahci_platform_enable_resources()/ahci_platform_disable_resources() methods. Alas it can't be implemented due to the AHCI-platform library already supporting the shared reset control lines. As [1] says in such case we have to use only one of the next methods: + reset_control_assert()/reset_control_deassert(); + reset_control_reset()/reset_control_rearm(). If the driver had an exclusive control over the reset lines we could have been able to manipulate the lines with no much limitation and just used the combination of the methods above to cover all the possible reset-control cases. Since the shared reset control has already been advertised and couldn't be changed with no risk to breaking the platforms relying on it, we have no choice but to make the platform drivers to determine which reset methods the platform reset system supports. In order to implement both types of reset control support we suggest to introduce the new AHCI-platform flag: AHCI_PLATFORM_RST_TRIGGER, which when passed to the ahci_platform_get_resources() method together with the AHCI_PLATFORM_GET_RESETS flag will indicate that the reset lines are self-deasserting thus the reset_control_reset()/reset_control_rearm() will be used to control the reset state. Otherwise the reset_control_deassert()/reset_control_assert() methods will be utilized. [1] Documentation/driver-api/reset.rst Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- Changelog v2: - Convert the ahci_platform_assert_rsts() method to returning int status (@Damien). - Fix some grammar mistakes in the ahci_platform_deassert_rsts() doc (@Damien). --- drivers/ata/ahci.h | 1 + drivers/ata/libahci_platform.c | 50 ++++++++++++++++++++++++++++++---- include/linux/ahci_platform.h | 5 +++- 3 files changed, 50 insertions(+), 6 deletions(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index c3770a19781b..7d834deefeb9 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -340,6 +340,7 @@ struct ahci_host_priv { bool got_runtime_pm; /* Did we do pm_runtime_get? */ unsigned int n_clks; struct clk_bulk_data *clks; /* Optional */ + unsigned int f_rsts; struct reset_control *rsts; /* Optional */ struct regulator **target_pwrs; /* Optional */ struct regulator *ahci_regulator;/* Optional */ diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 085f99b2eb5a..31be8a10facd 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -122,6 +122,44 @@ void ahci_platform_disable_clks(struct ahci_host_priv = *hpriv) } EXPORT_SYMBOL_GPL(ahci_platform_disable_clks); =20 +/** + * ahci_platform_deassert_rsts - Deassert/trigger platform resets + * @hpriv: host private area to store config values + * + * This function deasserts or triggers all the reset lines found for + * the AHCI device. + * + * RETURNS: + * 0 on success otherwise a negative error code + */ +int ahci_platform_deassert_rsts(struct ahci_host_priv *hpriv) +{ + if (hpriv->f_rsts & AHCI_PLATFORM_RST_TRIGGER) + return reset_control_reset(hpriv->rsts); + + return reset_control_deassert(hpriv->rsts); +} +EXPORT_SYMBOL_GPL(ahci_platform_deassert_rsts); + +/** + * ahci_platform_assert_rsts - Assert/rearm platform resets + * @hpriv: host private area to store config values + * + * This function asserts or rearms (for self-deasserting resets) all + * the reset controls found for the AHCI device. + * + * RETURNS: + * 0 on success otherwise a negative error code + */ +int ahci_platform_assert_rsts(struct ahci_host_priv *hpriv) +{ + if (hpriv->f_rsts & AHCI_PLATFORM_RST_TRIGGER) + return reset_control_rearm(hpriv->rsts); + + return reset_control_assert(hpriv->rsts); +} +EXPORT_SYMBOL_GPL(ahci_platform_assert_rsts); + /** * ahci_platform_enable_regulators - Enable regulators * @hpriv: host private area to store config values @@ -219,18 +257,18 @@ int ahci_platform_enable_resources(struct ahci_host_p= riv *hpriv) if (rc) goto disable_regulator; =20 - rc =3D reset_control_deassert(hpriv->rsts); + rc =3D ahci_platform_deassert_rsts(hpriv); if (rc) goto disable_clks; =20 rc =3D ahci_platform_enable_phys(hpriv); if (rc) - goto disable_resets; + goto disable_rsts; =20 return 0; =20 -disable_resets: - reset_control_assert(hpriv->rsts); +disable_rsts: + ahci_platform_assert_rsts(hpriv); =20 disable_clks: ahci_platform_disable_clks(hpriv); @@ -257,7 +295,7 @@ void ahci_platform_disable_resources(struct ahci_host_p= riv *hpriv) { ahci_platform_disable_phys(hpriv); =20 - reset_control_assert(hpriv->rsts); + ahci_platform_assert_rsts(hpriv); =20 ahci_platform_disable_clks(hpriv); =20 @@ -448,6 +486,8 @@ struct ahci_host_priv *ahci_platform_get_resources(stru= ct platform_device *pdev, rc =3D PTR_ERR(hpriv->rsts); goto err_out; } + + hpriv->f_rsts =3D flags & AHCI_PLATFORM_RST_TRIGGER; } =20 /* diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h index 49e5383d4222..6d7dd472d370 100644 --- a/include/linux/ahci_platform.h +++ b/include/linux/ahci_platform.h @@ -23,6 +23,8 @@ int ahci_platform_enable_phys(struct ahci_host_priv *hpri= v); void ahci_platform_disable_phys(struct ahci_host_priv *hpriv); int ahci_platform_enable_clks(struct ahci_host_priv *hpriv); void ahci_platform_disable_clks(struct ahci_host_priv *hpriv); +int ahci_platform_deassert_rsts(struct ahci_host_priv *hpriv); +int ahci_platform_assert_rsts(struct ahci_host_priv *hpriv); int ahci_platform_enable_regulators(struct ahci_host_priv *hpriv); void ahci_platform_disable_regulators(struct ahci_host_priv *hpriv); int ahci_platform_enable_resources(struct ahci_host_priv *hpriv); @@ -41,6 +43,7 @@ int ahci_platform_resume_host(struct device *dev); int ahci_platform_suspend(struct device *dev); int ahci_platform_resume(struct device *dev); =20 -#define AHCI_PLATFORM_GET_RESETS 0x01 +#define AHCI_PLATFORM_GET_RESETS BIT(0) +#define AHCI_PLATFORM_RST_TRIGGER BIT(1) =20 #endif /* _AHCI_PLATFORM_H */ --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC97DECAAA1 for ; Fri, 9 Sep 2022 19:38:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231816AbiIITiE (ORCPT ); Fri, 9 Sep 2022 15:38:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231244AbiIIThL (ORCPT ); Fri, 9 Sep 2022 15:37:11 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EC6FA116B6A; Fri, 9 Sep 2022 12:36:45 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 0C05FDC1; Fri, 9 Sep 2022 22:40:27 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 0C05FDC1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752427; bh=UQ0nLdDhSzWtNcB1iar518w4MATzJhPIimxsv/c0UjM=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=CL2Dv+vjBwE9UIQ2KIJlrxBZMxuyvJUp2RindUWWCN5kQg91TgrDmdxrRt3Kv0lIE NLzhoVUdJxkE034Ht2rQrHugRsxjJRwQnYccUrmYUp8RILHkwN83C/4xqcPruImhG9 8eS0iaZIv148OrI0zPzXJYR9qzyP3tNJTI1IEGeQ= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:38 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Rob Herring , Krzysztof Kozlowski CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , , Rob Herring Subject: [PATCH v8 11/23] dt-bindings: ata: ahci: Add platform capability properties Date: Fri, 9 Sep 2022 22:36:09 +0300 Message-ID: <20220909193621.17380-12-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In case if the platform doesn't have BIOS or a comprehensive firmware installed then the HBA capability flags will be left uninitialized. As a good alternative we suggest to define the DT-properties with the AHCI platform capabilities describing all the HW-init flags of the corresponding capability register. Luckily there aren't too many of them. SSS - Staggered Spin-up support and MPS - Mechanical Presence Switch support determine the corresponding feature availability for the whole HBA by means of the "hba-cap" property. Each port can have the "hba-port-cap" property initialized indicating that the port supports some of the next functionalities: HPCP - HotPlug capable port, MPSP - Mechanical Presence Switch attached to a port, CPD - Cold Plug detection, ESP - External SATA Port (eSATA), FBSCP - FIS-based switching capable port. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog v4: - Fix some misspelling in the patch log. - Convert the boolean properties to the bitfield properties. (@Rob) - Remove Hannes' rb tag due to the patch content change. Changelog v5: - Dual-licese the include/dt-bindings/ata/ahci.h file. (@Rob) --- .../devicetree/bindings/ata/ahci-common.yaml | 16 +++++++++++++++ .../bindings/ata/ahci-platform.yaml | 10 ++++++++++ include/dt-bindings/ata/ahci.h | 20 +++++++++++++++++++ 3 files changed, 46 insertions(+) create mode 100644 include/dt-bindings/ata/ahci.h diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Docum= entation/devicetree/bindings/ata/ahci-common.yaml index 12a97b56226f..94d72aeaad0f 100644 --- a/Documentation/devicetree/bindings/ata/ahci-common.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml @@ -58,6 +58,14 @@ properties: phy-names: const: sata-phy =20 + hba-cap: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + Bitfield of the HBA generic platform capabilities like Staggered + Spin-up or Mechanical Presence Switch support. It can be used to + appropriately initialize the HWinit fields of the HBA CAP register + in case if the system firmware hasn't done it. + ports-implemented: $ref: '/schemas/types.yaml#/definitions/uint32' description: @@ -101,6 +109,14 @@ $defs: target-supply: description: Power regulator for SATA port target device =20 + hba-port-cap: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + Bitfield of the HBA port-specific platform capabilities like Hot + plugging, eSATA, FIS-based Switching, etc (see AHCI specification + for details). It can be used to initialize the HWinit fields of + the PxCMD register in case if the system firmware hasn't done it. + required: - reg =20 diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Doc= umentation/devicetree/bindings/ata/ahci-platform.yaml index 15be98e0385b..e19cf9828e68 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml @@ -111,6 +111,8 @@ examples: - | #include #include + #include + sata@f7e90000 { compatible =3D "marvell,berlin2q-ahci", "generic-ahci"; reg =3D <0xf7e90000 0x1000>; @@ -119,15 +121,23 @@ examples: #address-cells =3D <1>; #size-cells =3D <0>; =20 + hba-cap =3D ; + sata0: sata-port@0 { reg =3D <0>; + phys =3D <&sata_phy 0>; target-supply =3D <®_sata0>; + + hba-port-cap =3D <(HBA_PORT_FBSCP | HBA_PORT_ESP)>; }; =20 sata1: sata-port@1 { reg =3D <1>; + phys =3D <&sata_phy 1>; target-supply =3D <®_sata1>; + + hba-port-cap =3D <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FB= SCP)>; }; }; diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h new file mode 100644 index 000000000000..77997b35612c --- /dev/null +++ b/include/dt-bindings/ata/ahci.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause */ +/* + * This header provides constants for most AHCI bindings. + */ + +#ifndef _DT_BINDINGS_ATA_AHCI_H +#define _DT_BINDINGS_ATA_AHCI_H + +/* Host Bus Adapter generic platform capabilities */ +#define HBA_SSS (1 << 27) +#define HBA_SMPS (1 << 28) + +/* Host Bus Adapter port-specific platform capabilities */ +#define HBA_PORT_HPCP (1 << 18) +#define HBA_PORT_MPSP (1 << 19) +#define HBA_PORT_CPD (1 << 20) +#define HBA_PORT_ESP (1 << 21) +#define HBA_PORT_FBSCP (1 << 22) + +#endif --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EBEEECAAA1 for ; Fri, 9 Sep 2022 19:38:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231886AbiIITiR (ORCPT ); Fri, 9 Sep 2022 15:38:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231538AbiIIThM (ORCPT ); Fri, 9 Sep 2022 15:37:12 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3660C11B037; Fri, 9 Sep 2022 12:36:46 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id BD46DDBE; Fri, 9 Sep 2022 22:40:27 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com BD46DDBE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752427; bh=lR+XuoZ5OpBeN2gxrD/crsk4SZmx3KT/fJ296KmTZDU=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=dkQ7x92rwf4ZFGPkITL4+WyM0/2sdRRqBOD8LTdLfDPJFUUgk3LyPApiRqFDlQSoF RyHGPCSvDKXnSxJmZdwaQQQnCcCP/hNo87eg2bFrQZa+AkcwQbgBO37yQyPcU10op4 fRYZi0qr6UvIg/HtJARYcugtNHtU/B6wE+38R5fM= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:39 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 12/23] ata: libahci: Extend port-cmd flags set with port capabilities Date: Fri, 9 Sep 2022 22:36:10 +0300 Message-ID: <20220909193621.17380-13-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently not all of the Port-specific capabilities listed in the PORT_CMD-enumeration. Let's extend that set with the Cold Presence Detection and Mechanical Presence Switch attached to the Port flags [1] so to closeup the set of the platform-specific port-capabilities flags. Note these flags are supposed to be set by the platform firmware if there is one. Alternatively as we are about to do they can be set by means of the OF properties. While at it replace PORT_IRQ_DEV_ILCK with PORT_IRQ_DMPS and fix the comment there. In accordance with [2] that IRQ flag is supposed to indicate the state of the signal coming from the Mechanical Presence Switch. [1] Serial ATA AHCI 1.3.1 Specification, p.27 [2] Serial ATA AHCI 1.3.1 Specification, p.24, p.88 Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- Changelog v4: - Fix the DMPS macros name in the patch log. (@Sergei Shtylyov) Changelog v5: - Add a comment regarding the PORT_CMD_CAP enum entity purpose. (@Damien) --- drivers/ata/ahci.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index 7d834deefeb9..27cab4e909a5 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -138,7 +138,7 @@ enum { PORT_IRQ_BAD_PMP =3D (1 << 23), /* incorrect port multiplier */ =20 PORT_IRQ_PHYRDY =3D (1 << 22), /* PhyRdy changed */ - PORT_IRQ_DEV_ILCK =3D (1 << 7), /* device interlock */ + PORT_IRQ_DMPS =3D (1 << 7), /* mechanical presence status */ PORT_IRQ_CONNECT =3D (1 << 6), /* port connect change status */ PORT_IRQ_SG_DONE =3D (1 << 5), /* descriptor processed */ PORT_IRQ_UNK_FIS =3D (1 << 4), /* unknown FIS rx'd */ @@ -166,6 +166,8 @@ enum { PORT_CMD_ATAPI =3D (1 << 24), /* Device is ATAPI */ PORT_CMD_FBSCP =3D (1 << 22), /* FBS Capable Port */ PORT_CMD_ESP =3D (1 << 21), /* External Sata Port */ + PORT_CMD_CPD =3D (1 << 20), /* Cold Presence Detection */ + PORT_CMD_MPSP =3D (1 << 19), /* Mechanical Presence Switch */ PORT_CMD_HPCP =3D (1 << 18), /* HotPlug Capable Port */ PORT_CMD_PMP =3D (1 << 17), /* PMP attached */ PORT_CMD_LIST_ON =3D (1 << 15), /* cmd list DMA engine running */ @@ -181,6 +183,10 @@ enum { PORT_CMD_ICC_PARTIAL =3D (0x2 << 28), /* Put i/f in partial state */ PORT_CMD_ICC_SLUMBER =3D (0x6 << 28), /* Put i/f in slumber state */ =20 + /* PORT_CMD capabilities mask */ + PORT_CMD_CAP =3D PORT_CMD_HPCP | PORT_CMD_MPSP | + PORT_CMD_CPD | PORT_CMD_ESP | PORT_CMD_FBSCP, + /* PORT_FBS bits */ PORT_FBS_DWE_OFFSET =3D 16, /* FBS device with error offset */ PORT_FBS_ADO_OFFSET =3D 12, /* FBS active dev optimization offset */ --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11905ECAAD5 for ; Fri, 9 Sep 2022 19:38:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231678AbiIITiV (ORCPT ); Fri, 9 Sep 2022 15:38:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230423AbiIIThM (ORCPT ); Fri, 9 Sep 2022 15:37:12 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 08E3711C7E7; Fri, 9 Sep 2022 12:36:47 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id C14E5DBF; Fri, 9 Sep 2022 22:40:28 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com C14E5DBF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752428; bh=xg2OaeZnmPtszpVQN/SChJWw4hReYgrzAYpanoiG0kE=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=dTvDS2QHHDP3hTcT/QCoG82jygqtpvQXIhvFTn1nl8LSxpLwM12d2POhk4ddr11tL OBgkbVME6MFzpWSvBnMVOcL8bMzKPAxWkXHIrAEb+cPPKfFNZru7iANE0pYFWKl3Q0 khA5Raa8nph+KqeHd4HGZleKlPxE4Q+ZmRuYf6Dc= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:40 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 13/23] ata: libahci: Discard redundant force_port_map parameter Date: Fri, 9 Sep 2022 22:36:11 +0300 Message-ID: <20220909193621.17380-14-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently there are four port-map-related fields declared in the ahci_host_priv structure and used to setup the HBA ports mapping. First the ports-mapping is read from the PI register and immediately stored in the saved_port_map field. If forced_port_map is initialized with non-zero value then its value will have greater priority over the value read from PI, thus it will override the saved_port_map field. That value will be then masked by a non-zero mask_port_map field and after some sanity checks it will be stored in the ahci_host_priv.port_map field as a final port mapping. As you can see the logic is a bit too complicated for such a simple task. We can freely get rid from at least one of the fields with no change to the implemented semantic. The force_port_map field can be replaced with taking non-zero saved_port_map value into account. So if saved_port_map is pre-initialized by the low level drivers (platform drivers) then it will have greater priority over the value read from PI register and will be used as actual HBA ports mapping later on. Thus the ports map forcing task will be just transferred from force_port_map to the saved_port_map field. This modification will perfectly fit into the feature of having OF-based initialization of the HW-init HBA CSR fields we are about to introduce in the next commit. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- drivers/ata/ahci.c | 2 +- drivers/ata/ahci.h | 1 - drivers/ata/libahci.c | 10 ++++++---- drivers/ata/libahci_platform.c | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index c1eca72b4575..bacb597a0d32 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -657,7 +657,7 @@ static void ahci_pci_save_initial_config(struct pci_dev= *pdev, { if (pdev->vendor =3D=3D PCI_VENDOR_ID_JMICRON && pdev->device =3D=3D 0x23= 61) { dev_info(&pdev->dev, "JMB361 has only one port\n"); - hpriv->force_port_map =3D 1; + hpriv->saved_port_map =3D 1; } =20 /* diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index 27cab4e909a5..cc4f40e6c924 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -328,7 +328,6 @@ struct ahci_port_priv { struct ahci_host_priv { /* Input fields */ unsigned int flags; /* AHCI_HFLAG_* */ - u32 force_port_map; /* force port map */ u32 mask_port_map; /* mask out particular bits */ =20 void __iomem * mmio; /* bus-independent mem map */ diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index cf8c7fd59ada..000a7072614f 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -453,7 +453,6 @@ void ahci_save_initial_config(struct device *dev, struc= t ahci_host_priv *hpriv) * reset. Values without are used for driver operation. */ hpriv->saved_cap =3D cap =3D readl(mmio + HOST_CAP); - hpriv->saved_port_map =3D port_map =3D readl(mmio + HOST_PORTS_IMPL); =20 /* CAP2 register is only defined for AHCI 1.2 and later */ vers =3D readl(mmio + HOST_VERSION); @@ -517,10 +516,13 @@ void ahci_save_initial_config(struct device *dev, str= uct ahci_host_priv *hpriv) cap &=3D ~HOST_CAP_SXS; } =20 - if (hpriv->force_port_map && port_map !=3D hpriv->force_port_map) { + /* Override the HBA ports mapping if the platform needs it */ + port_map =3D readl(mmio + HOST_PORTS_IMPL); + if (hpriv->saved_port_map && port_map !=3D hpriv->saved_port_map) { dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", - port_map, hpriv->force_port_map); - port_map =3D hpriv->force_port_map; + port_map, hpriv->saved_port_map); + port_map =3D hpriv->saved_port_map; + } else { hpriv->saved_port_map =3D port_map; } =20 diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 31be8a10facd..01c195b6d9e6 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -526,7 +526,7 @@ struct ahci_host_priv *ahci_platform_get_resources(stru= ct platform_device *pdev, } =20 of_property_read_u32(dev->of_node, - "ports-implemented", &hpriv->force_port_map); + "ports-implemented", &hpriv->saved_port_map); =20 if (child_nodes) { for_each_child_of_node(dev->of_node, child) { --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0F16ECAAA1 for ; Fri, 9 Sep 2022 19:38:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231995AbiIITi0 (ORCPT ); Fri, 9 Sep 2022 15:38:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231611AbiIIThS (ORCPT ); Fri, 9 Sep 2022 15:37:18 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0A5A211E6F5; Fri, 9 Sep 2022 12:36:49 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 67B04DC2; Fri, 9 Sep 2022 22:40:29 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 67B04DC2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752429; bh=2uGMZvqONo/mGb1/ywfB2p6vdAzh6/ySAHV5YXJ66sg=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=ckiSdyXX6/kEg4mGPqIUSRtmPdMugy2tKqRLF0S3DLItruLeTqoYOxUuN3vcIMcGz P7bbBFZHB/VMQqBF+KXcCiT9nK2HTrmFhYV5IrdTOl7pa4AErDZanrkM5CfsHXUSUg U5SHAQjRdoJWaj+7thO7N08ZAfaxbadrSJ+9Hzbg= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:40 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 14/23] ata: libahci: Don't read AHCI version twice in the save-config method Date: Fri, 9 Sep 2022 22:36:12 +0300 Message-ID: <20220909193621.17380-15-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is no point in reading the AHCI version all over in the tail of the ahci_save_initial_config() method. That register is RO and doesn't change its value even after reset. So just reuse the data, which has already been read from there earlier in the head of the function. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- drivers/ata/libahci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index 000a7072614f..1ffaa5f5f21a 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -564,7 +564,7 @@ void ahci_save_initial_config(struct device *dev, struc= t ahci_host_priv *hpriv) /* record values to use during operation */ hpriv->cap =3D cap; hpriv->cap2 =3D cap2; - hpriv->version =3D readl(mmio + HOST_VERSION); + hpriv->version =3D vers; hpriv->port_map =3D port_map; =20 if (!hpriv->start_engine) --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48EB7ECAAD3 for ; Fri, 9 Sep 2022 19:38:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232018AbiIITib (ORCPT ); Fri, 9 Sep 2022 15:38:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231699AbiIIThg (ORCPT ); Fri, 9 Sep 2022 15:37:36 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6DF021203FA; Fri, 9 Sep 2022 12:36:50 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 32686DC3; Fri, 9 Sep 2022 22:40:30 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 32686DC3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752430; bh=/e1wD+4/ocZIxrPY/TeSDUfGQdbEoA1sGbcbkJoPplY=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Q/u66tyHdsZyN0m7W+ErHsetSTd+wajoWdEnfKBO9/DxA8uEuFVvc/lstDcIp7WdA F8cB5vcD1fnZDUEoiNYJs97NVdyE3UG0Ner+OTy6CAsVWvICOHORQcGb3HYfEQLK04 Nya9VcRzmJsiNoc0sAHQQYJgp1XMdZAQI6o28Xbk= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:41 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 15/23] ata: ahci: Convert __ahci_port_base to accepting hpriv as arguments Date: Fri, 9 Sep 2022 22:36:13 +0300 Message-ID: <20220909193621.17380-16-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The port base address may be required even before the ata_host instance is initialized and activated, for instance in the ahci_save_initial_config() method which we are about to update (consider this modification as a preparation for that one). Seeing the __ahci_port_base() function isn't used much it's the best candidate to provide the required functionality. So let's convert it to accepting the ahci_host_priv structure pointer. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- Changelog v5: - Fix some grammar notes in the patchlog. (@Damien) --- drivers/ata/ahci.c | 2 +- drivers/ata/ahci.h | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index bacb597a0d32..51c0c1dd91ea 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -690,7 +690,7 @@ static void ahci_pci_init_controller(struct ata_host *h= ost) mv =3D 2; else mv =3D 4; - port_mmio =3D __ahci_port_base(host, mv); + port_mmio =3D __ahci_port_base(hpriv, mv); =20 writel(0, port_mmio + PORT_IRQ_MASK); =20 diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index cc4f40e6c924..5d9db5e7476c 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -432,10 +432,9 @@ int ahci_host_activate(struct ata_host *host, struct s= csi_host_template *sht); void ahci_error_handler(struct ata_port *ap); u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked); =20 -static inline void __iomem *__ahci_port_base(struct ata_host *host, +static inline void __iomem *__ahci_port_base(struct ahci_host_priv *hpriv, unsigned int port_no) { - struct ahci_host_priv *hpriv =3D host->private_data; void __iomem *mmio =3D hpriv->mmio; =20 return mmio + 0x100 + (port_no * 0x80); @@ -443,7 +442,9 @@ static inline void __iomem *__ahci_port_base(struct ata= _host *host, =20 static inline void __iomem *ahci_port_base(struct ata_port *ap) { - return __ahci_port_base(ap->host, ap->port_no); + struct ahci_host_priv *hpriv =3D ap->host->private_data; + + return __ahci_port_base(hpriv, ap->port_no); } =20 static inline int ahci_nr_ports(u32 cap) --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 696B9ECAAD5 for ; Fri, 9 Sep 2022 19:38:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232058AbiIITif (ORCPT ); Fri, 9 Sep 2022 15:38:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230114AbiIIThs (ORCPT ); Fri, 9 Sep 2022 15:37:48 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6E6CC12111C; Fri, 9 Sep 2022 12:36:50 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 3275EDC4; Fri, 9 Sep 2022 22:40:31 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 3275EDC4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752431; bh=LjEVU17xhUc7qGeB4gV9o+RnzXDn6ct6Ytun4AKLoos=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=fitiu+uuBH3ViaeAyjRm9vSVfec0yoEt9AgYZy7BwvdI7wpanC2xlFR7IbORnXXyr 2z0BIIRUQLnotuPbUZJkStaXvXGVZjYnMSnRTd2N511BHpvYTYquUlSyrCrWkCGZWJ 7EEV3Gfs5buuivm65F7GvOUM3XdikPvhLzw5dp/U= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:42 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 16/23] ata: ahci: Introduce firmware-specific caps initialization Date: Fri, 9 Sep 2022 22:36:14 +0300 Message-ID: <20220909193621.17380-17-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are systems with no BIOS or comprehensive embedded firmware which could be able to properly initialize the SATA AHCI controller platform-specific capabilities. In that case a good alternative to having a clever bootloader is to create a device tree node with the properties well describing all the AHCI-related platform specifics. All the settings which are normally detected and marked as available in the HBA and its ports capabilities fields [1] could be defined in the platform DTB by means of a set of the dedicated properties. Such approach perfectly fits to the DTB-philosophy - to provide hardware/platform description. So here we suggest to extend the SATA AHCI device tree bindings with two additional DT-properties: 1) "hba-cap" - HBA platform generic capabilities like: - SSS - Staggered Spin-up support. - SMPS - Mechanical Presence Switch support. 2) "hba-port-cap" - HBA platform port capabilities like: - HPCP - Hot Plug Capable Port. - MPSP - Mechanical Presence Switch Attached to Port. - CPD - Cold Presence Detection. - ESP - External SATA Port. - FBSCP - FIS-based Switching Capable Port. All of these capabilities require to have a corresponding hardware configuration. Thus it's ok to have them defined in DTB. Even though the driver currently takes into account the state of the ESP and FBSCP flags state only, there is nothing wrong with having all of them supported by the generic AHCI library in order to have a complete OF-based platform-capabilities initialization procedure. These properties will be parsed in the ahci_platform_get_resources() method and their values will be stored in the saved_* fields of the ahci_host_priv structure, which in its turn then will be used to restore the H.CAP, H.PI and P#.CMD capability fields on device init and after HBA reset. Please note this modification concerns the HW-init HBA and its ports flags only, which are by specification [1] are supposed to be initialized by the BIOS/platform firmware/expansion ROM and which are normally declared in the one-time-writable-after-reset register fields. Even though these flags aren't supposed to be cleared after HBA reset some AHCI instances may violate that rule so we still need to perform the fields resetting after each reset. Luckily the corresponding functionality has already been partly implemented in the framework of the ahci_save_initial_config() and ahci_restore_initial_config() methods. [1] Serial ATA AHCI 1.3.1 Specification, p. 103 Signed-off-by: Serge Semin --- Changelog v4: - Convert the boolean properties to the bitfield DT-properties. (@Rob) Changelog v5: - Drop white line modification. (@Damien) --- drivers/ata/ahci.h | 1 + drivers/ata/libahci.c | 51 ++++++++++++++++++++++++++++------ drivers/ata/libahci_platform.c | 40 ++++++++++++++++++++++++-- 3 files changed, 81 insertions(+), 11 deletions(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index 5d9db5e7476c..da7ee8bec165 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -338,6 +338,7 @@ struct ahci_host_priv { u32 saved_cap; /* saved initial cap */ u32 saved_cap2; /* saved initial cap2 */ u32 saved_port_map; /* saved initial port_map */ + u32 saved_port_cap[AHCI_MAX_PORTS]; /* saved port_cap */ u32 em_loc; /* enclosure management location */ u32 em_buf_sz; /* EM buffer size in byte */ u32 em_msg_type; /* EM message type */ diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index 1ffaa5f5f21a..954386a2b500 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -16,6 +16,7 @@ * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf */ =20 +#include #include #include #include @@ -443,16 +444,28 @@ static ssize_t ahci_show_em_supported(struct device *= dev, void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *h= priv) { void __iomem *mmio =3D hpriv->mmio; - u32 cap, cap2, vers, port_map; + void __iomem *port_mmio; + unsigned long port_map; + u32 cap, cap2, vers; int i; =20 /* make sure AHCI mode is enabled before accessing CAP */ ahci_enable_ahci(mmio); =20 - /* Values prefixed with saved_ are written back to host after - * reset. Values without are used for driver operation. + /* + * Values prefixed with saved_ are written back to the HBA and ports + * registers after reset. Values without are used for driver operation. + */ + + /* + * Override HW-init HBA capability fields with the platform-specific + * values. The rest of the HBA capabilities are defined as Read-only + * and can't be modified in CSR anyway. */ - hpriv->saved_cap =3D cap =3D readl(mmio + HOST_CAP); + cap =3D readl(mmio + HOST_CAP); + if (hpriv->saved_cap) + cap =3D (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap; + hpriv->saved_cap =3D cap; =20 /* CAP2 register is only defined for AHCI 1.2 and later */ vers =3D readl(mmio + HOST_VERSION); @@ -519,7 +532,7 @@ void ahci_save_initial_config(struct device *dev, struc= t ahci_host_priv *hpriv) /* Override the HBA ports mapping if the platform needs it */ port_map =3D readl(mmio + HOST_PORTS_IMPL); if (hpriv->saved_port_map && port_map !=3D hpriv->saved_port_map) { - dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", + dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n", port_map, hpriv->saved_port_map); port_map =3D hpriv->saved_port_map; } else { @@ -527,7 +540,7 @@ void ahci_save_initial_config(struct device *dev, struc= t ahci_host_priv *hpriv) } =20 if (hpriv->mask_port_map) { - dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", + dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n", port_map, port_map & hpriv->mask_port_map); port_map &=3D hpriv->mask_port_map; @@ -546,7 +559,7 @@ void ahci_save_initial_config(struct device *dev, struc= t ahci_host_priv *hpriv) */ if (map_ports > ahci_nr_ports(cap)) { dev_warn(dev, - "implemented port map (0x%x) contains more ports than nr_ports (%u), = using nr_ports\n", + "implemented port map (0x%lx) contains more ports than nr_ports (%u),= using nr_ports\n", port_map, ahci_nr_ports(cap)); port_map =3D 0; } @@ -555,12 +568,26 @@ void ahci_save_initial_config(struct device *dev, str= uct ahci_host_priv *hpriv) /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ if (!port_map && vers < 0x10300) { port_map =3D (1 << ahci_nr_ports(cap)) - 1; - dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); + dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map); =20 /* write the fixed up value to the PI register */ hpriv->saved_port_map =3D port_map; } =20 + /* + * Preserve the ports capabilities defined by the platform. Note there + * is no need in storing the rest of the P#.CMD fields since they are + * volatile. + */ + for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { + if (hpriv->saved_port_cap[i]) + continue; + + port_mmio =3D __ahci_port_base(hpriv, i); + hpriv->saved_port_cap[i] =3D + readl(port_mmio + PORT_CMD) & PORT_CMD_CAP; + } + /* record values to use during operation */ hpriv->cap =3D cap; hpriv->cap2 =3D cap2; @@ -590,13 +617,21 @@ EXPORT_SYMBOL_GPL(ahci_save_initial_config); static void ahci_restore_initial_config(struct ata_host *host) { struct ahci_host_priv *hpriv =3D host->private_data; + unsigned long port_map =3D hpriv->port_map; void __iomem *mmio =3D hpriv->mmio; + void __iomem *port_mmio; + int i; =20 writel(hpriv->saved_cap, mmio + HOST_CAP); if (hpriv->saved_cap2) writel(hpriv->saved_cap2, mmio + HOST_CAP2); writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ + + for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { + port_mmio =3D __ahci_port_base(hpriv, i); + writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD); + } } =20 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 01c195b6d9e6..86d156075336 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -382,6 +382,34 @@ static int ahci_platform_get_regulator(struct ahci_hos= t_priv *hpriv, u32 port, return rc; } =20 +static int ahci_platform_get_firmware(struct ahci_host_priv *hpriv, + struct device *dev) +{ + struct device_node *child; + u32 port; + + if (!of_property_read_u32(dev->of_node, "hba-cap", &hpriv->saved_cap)) + hpriv->saved_cap &=3D (HOST_CAP_SSS | HOST_CAP_MPS); + + of_property_read_u32(dev->of_node, + "ports-implemented", &hpriv->saved_port_map); + + for_each_child_of_node(dev->of_node, child) { + if (!of_device_is_available(child)) + continue; + + if (of_property_read_u32(child, "reg", &port)) { + of_node_put(child); + return -EINVAL; + } + + if (!of_property_read_u32(child, "hba-port-cap", &hpriv->saved_port_cap[= port])) + hpriv->saved_port_cap[port] &=3D PORT_CMD_CAP; + } + + return 0; +} + /** * ahci_platform_get_resources - Get platform resources * @pdev: platform device to get resources for @@ -525,9 +553,6 @@ struct ahci_host_priv *ahci_platform_get_resources(stru= ct platform_device *pdev, goto err_out; } =20 - of_property_read_u32(dev->of_node, - "ports-implemented", &hpriv->saved_port_map); - if (child_nodes) { for_each_child_of_node(dev->of_node, child) { u32 port; @@ -592,6 +617,15 @@ struct ahci_host_priv *ahci_platform_get_resources(str= uct platform_device *pdev, if (rc =3D=3D -EPROBE_DEFER) goto err_out; } + + /* + * Retrieve firmware-specific flags which then will be used to set + * the HW-init fields of HBA and its ports + */ + rc =3D ahci_platform_get_firmware(hpriv, dev); + if (rc) + goto err_out; + pm_runtime_enable(dev); pm_runtime_get_sync(dev); hpriv->got_runtime_pm =3D true; --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E97D4C6FA8A for ; Fri, 9 Sep 2022 19:38:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231722AbiIITik (ORCPT ); Fri, 9 Sep 2022 15:38:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231168AbiIIThs (ORCPT ); Fri, 9 Sep 2022 15:37:48 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5E6C712168E; Fri, 9 Sep 2022 12:36:51 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 42CACDBA; Fri, 9 Sep 2022 22:40:32 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 42CACDBA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752432; bh=0lqXmojW/LDkIzOealxVEvtRoqQ2blxWMO51Pelx9dY=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=auouoW8XoPVPhJVKeD/c+ssknofdm5vkupK38aakI1ksw1atc+GHIbgnwgyPg2sqy Ihb4HGXXT3SI7mnQlmWYzr4bVem8XazkH+m7I4gYaSJ/gEaBueZD4hZHrdppKym3yU zkvFZQoBbmjj0meUa+nQY/Kk+1KpjMGT3WKm3g/c= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:43 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Rob Herring , Krzysztof Kozlowski , Serge Semin CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , , Rob Herring Subject: [PATCH v8 17/23] dt-bindings: ata: ahci: Add DWC AHCI SATA controller DT schema Date: Fri, 9 Sep 2022 22:36:15 +0300 Message-ID: <20220909193621.17380-18-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Synopsys AHCI SATA controller is mainly compatible with the generic AHCI SATA controller except a few peculiarities and the platform environment requirements. In particular it can have at least two reference clocks to feed up its AHB/AXI interface and SATA PHYs domain and at least one reset control for the application clock domain. In addition to that the DMA interface of each port can be tuned up to work with the predefined maximum data chunk size. Note unlike generic AHCI controller DWC AHCI can't have more than 8 ports. All of that is reflected in the new DWC AHCI SATA device DT binding. Note the DWC AHCI SATA controller DT-schema has been created in a way so to be reused for the vendor-specific DT-schemas (see for example the "snps,dwc-ahci" compatible string binding). One of which we are about to introduce. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog v2: - Replace min/max constraints of the snps,{tx,rx}-ts-max property with enum [ 1, 2, 4, ..., 1024 ]. (@Rob) Changelog v4: - Decrease the "additionalProperties" property identation otherwise it's percieved as the node property instead of the key one. (@Rob) - Use the ahci-port properties definition from the AHCI common schema in order to extend it with DWC AHCI SATA port properties. (@Rob) - Remove the Hannes' rb tag since the patch content has changed. Changelog v5: - Fix "resets" property description: replace "clocks" with "resets". (@Rob) - Extend "resets/clocks{-names}" property definitions. (@Rob) - Add "resets" property min/maxItems constraints. (@Rob) - Add names for the basic resets like RxOOB and PM-alive. (@Rob) - Add generic DWC AHCI SATA fallback for "rockchip,rk3568-dwc-ahci" bindings. (@Rob) - Due to the change above the schema has been split up into two parts: common DWC AHCI SATA properties and generic DW AHCI SATA controller DT-schema. (@Rob) --- .../bindings/ata/ahci-platform.yaml | 8 -- .../bindings/ata/snps,dwc-ahci-common.yaml | 102 ++++++++++++++++++ .../bindings/ata/snps,dwc-ahci.yaml | 75 +++++++++++++ 3 files changed, 177 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/snps,dwc-ahci-com= mon.yaml create mode 100644 Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Doc= umentation/devicetree/bindings/ata/ahci-platform.yaml index e19cf9828e68..7dc2a2e8f598 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml +++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml @@ -30,8 +30,6 @@ select: - marvell,armada-3700-ahci - marvell,armada-8k-ahci - marvell,berlin2q-ahci - - snps,dwc-ahci - - snps,spear-ahci required: - compatible =20 @@ -48,17 +46,11 @@ properties: - marvell,berlin2-ahci - marvell,berlin2q-ahci - const: generic-ahci - - items: - - enum: - - rockchip,rk3568-dwc-ahci - - const: snps,dwc-ahci - enum: - cavium,octeon-7130-ahci - hisilicon,hisi-ahci - ibm,476gtr-ahci - marvell,armada-3700-ahci - - snps,dwc-ahci - - snps,spear-ahci =20 reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yam= l b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml new file mode 100644 index 000000000000..c1457910520b --- /dev/null +++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DWC AHCI SATA controller properties + +maintainers: + - Serge Semin + +description: + This document defines device tree schema for the generic Synopsys DWC + AHCI controller properties. + +select: false + +allOf: + - $ref: ahci-common.yaml# + +properties: + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: + Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock, + PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/T= x) + clock, etc. + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + oneOf: + - description: Application APB/AHB/AXI BIU clock + enum: + - pclk + - aclk + - hclk + - sata + - description: Power Module keep-alive clock + const: pmalive + - description: RxOOB detection clock + const: rxoob + - description: SATA Ports reference clock + const: ref + + resets: + description: + At least basic application and reference clock domains resets are + normally supported by the DWC AHCI SATA controller. + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + items: + oneOf: + - description: Application AHB/AXI BIU clock domain reset control + enum: + - arst + - hrst + - description: Power Module keep-alive clock domain reset control + const: pmalive + - description: RxOOB detection clock domain reset control + const: rxoob + - description: Reference clock domain reset control + const: ref + +patternProperties: + "^sata-port@[0-9a-e]$": + $ref: '#/$defs/dwc-ahci-port' + +additionalProperties: true + +$defs: + dwc-ahci-port: + $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port + + properties: + reg: + minimum: 0 + maximum: 7 + + snps,tx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Maximal size of Tx DMA transactions in FIFO words + enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ] + + snps,rx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Maximal size of Rx DMA transactions in FIFO words + enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ] + +... diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Doc= umentation/devicetree/bindings/ata/snps,dwc-ahci.yaml new file mode 100644 index 000000000000..5afa4b57ce20 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DWC AHCI SATA controller + +maintainers: + - Serge Semin + +description: + This document defines device tree bindings for the generic Synopsys DWC + implementation of the AHCI SATA controller. + +allOf: + - $ref: snps,dwc-ahci-common.yaml# + +properties: + compatible: + oneOf: + - description: Synopsys AHCI SATA-compatible devices + const: snps,dwc-ahci + - description: SPEAr1340 AHCI SATA device + const: snps,spear-ahci + - description: Rockhip RK3568 AHCI controller + items: + - const: rockchip,rk3568-dwc-ahci + - const: snps,dwc-ahci + +patternProperties: + "^sata-port@[0-9a-e]$": + $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + sata@122f0000 { + compatible =3D "snps,dwc-ahci"; + reg =3D <0x122F0000 0x1ff>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + interrupts =3D ; + + clocks =3D <&clock1>, <&clock2>; + clock-names =3D "aclk", "ref"; + + phys =3D <&sata_phy>; + phy-names =3D "sata-phy"; + + ports-implemented =3D <0x1>; + + sata-port@0 { + reg =3D <0>; + + hba-port-cap =3D ; + + snps,tx-ts-max =3D <512>; + snps,rx-ts-max =3D <512>; + }; + }; + +... --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECD09ECAAD3 for ; Fri, 9 Sep 2022 19:38:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232079AbiIITio (ORCPT ); Fri, 9 Sep 2022 15:38:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231755AbiIIThx (ORCPT ); Fri, 9 Sep 2022 15:37:53 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B56EA131EE4; Fri, 9 Sep 2022 12:36:53 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id F2856DC5; Fri, 9 Sep 2022 22:40:32 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com F2856DC5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752432; bh=tSsMfF1s5Ux6xk0N3ZRzC7OTKA8znIR4lsF8Oe1CY5A=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Ov8Kkd5Cjpw5NKlAx+XL4mx/jUkM8JMigsPJOyvLm3T4sw57hLag3CgCWRqLFqbGQ x+WuTPVjHcsgR3XU9AEk1FFho2m9Jx5UEMwQuPbOpPc1PoCxbZTfma4OvsvhQKa0Ej FoIxGm71HPLWc0xzynH8VKDMtTsJ9I9yD+7L3tks= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:44 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 18/23] ata: libahci_platform: Add function returning a clock-handle by id Date: Fri, 9 Sep 2022 22:36:16 +0300 Message-ID: <20220909193621.17380-19-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since all the clocks are retrieved by the method ahci_platform_get_resources() there is no need for the LLD (glue) drivers to be looking for some particular of them in the kernel clocks table again. Instead we suggest to add a simple method returning a device-specific clock with passed connection ID if it is managed to be found. Otherwise the function will return NULL. Thus the glue-drivers won't need to either manually touching the hpriv->clks array or calling clk_get()-friends. The AHCI platform drivers will be able to use the new function right after the ahci_platform_get_resources() method invocation and up to the device removal. Note the method is left unused here, but will be utilized in the framework of the DWC AHCI SATA driver being added in the next commit. Signed-off-by: Serge Semin --- Changelog v2: - Fix some grammar mistakes in the method description. Changelog v4: - Add a note regarding the new method usage. Changelog v5: - Fix the ahci_platform_find_clk() declaration identations. (@Damien) - Simplify the ahci_platform_find_clk() method body by dropping the local poiter to clk structure. (@Damien) --- drivers/ata/libahci_platform.c | 24 ++++++++++++++++++++++++ include/linux/ahci_platform.h | 3 +++ 2 files changed, 27 insertions(+) diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 86d156075336..ddf17e2d266c 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -93,6 +93,30 @@ void ahci_platform_disable_phys(struct ahci_host_priv *h= priv) } EXPORT_SYMBOL_GPL(ahci_platform_disable_phys); =20 +/** + * ahci_platform_find_clk - Find platform clock + * @hpriv: host private area to store config values + * @con_id: clock connection ID + * + * This function returns a pointer to the clock descriptor of the clock wi= th + * the passed ID. + * + * RETURNS: + * Pointer to the clock descriptor on success otherwise NULL + */ +struct clk *ahci_platform_find_clk(struct ahci_host_priv *hpriv, const cha= r *con_id) +{ + int i; + + for (i =3D 0; i < hpriv->n_clks; i++) { + if (!strcmp(hpriv->clks[i].id, con_id)) + return hpriv->clks[i].clk; + } + + return NULL; +} +EXPORT_SYMBOL_GPL(ahci_platform_find_clk); + /** * ahci_platform_enable_clks - Enable platform clocks * @hpriv: host private area to store config values diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h index 6d7dd472d370..17fa26215292 100644 --- a/include/linux/ahci_platform.h +++ b/include/linux/ahci_platform.h @@ -13,6 +13,7 @@ =20 #include =20 +struct clk; struct device; struct ata_port_info; struct ahci_host_priv; @@ -21,6 +22,8 @@ struct scsi_host_template; =20 int ahci_platform_enable_phys(struct ahci_host_priv *hpriv); void ahci_platform_disable_phys(struct ahci_host_priv *hpriv); +struct clk *ahci_platform_find_clk(struct ahci_host_priv *hpriv, + const char *con_id); int ahci_platform_enable_clks(struct ahci_host_priv *hpriv); void ahci_platform_disable_clks(struct ahci_host_priv *hpriv); int ahci_platform_deassert_rsts(struct ahci_host_priv *hpriv); --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FABDECAAD3 for ; Fri, 9 Sep 2022 19:38:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231508AbiIITis (ORCPT ); Fri, 9 Sep 2022 15:38:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231748AbiIIThx (ORCPT ); Fri, 9 Sep 2022 15:37:53 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B429811CD77; Fri, 9 Sep 2022 12:36:53 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 197C7DC0; Fri, 9 Sep 2022 22:40:34 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 197C7DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752434; bh=PC+poOD2/oRdeGMaahjbFoEzOps9Kix3C1IyInviCw8=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Evipw6FFWsPEAYTUzk3iGJiKKRz8flOsifu5d/O9NNJbnPq/ujvqjynzYy6vdH5vU 27AZGsWpS3Cely/iWQWjY7Y1SJjbvfCYbI6wMNUQpK5PiQ8mQ+KDeuRRbRyp1t9pmR PJ+RwcY3wXmYt7VwHt2WN+X+k1SMbFBSl+Q3RqIw= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:45 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Serge Semin CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 19/23] ata: ahci: Add DWC AHCI SATA controller support Date: Fri, 9 Sep 2022 22:36:17 +0300 Message-ID: <20220909193621.17380-20-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Synopsys AHCI SATA controller can work pretty under with the generic AHCI-platform driver control. But there are vendor-specific peculiarities which can tune the device performance up and which may need to be fixed up for proper device functioning. In addition some DWC AHCI-based controllers may require small platform-specific fixups, so adding them in the generic AHCI driver would have ruined the code simplicity. Shortly speaking in order to keep the generic AHCI-platform code clean and have DWC AHCI SATA-specific features supported we suggest to add a dedicated DWC AHCI SATA device driver. Aside with the standard AHCI-platform resources getting, enabling/disabling and the controller registration the new driver performs the next actions. First of all there is a way to verify whether the HBA/ports capabilities activated in OF are correct. Almost all features availability is reflected in the vendor-specific parameters registers. So the DWC AHCI driver does the capabilities sanity check based on the corresponding fields state. Secondly if either the Command Completion Coalescing or the Device Sleep feature is enabled the DWC AHCI-specific internal 1ms timer must be fixed in accordance with the application clock signal frequency. In particular the timer value must be set to be Fapp * 1000. Normally the SoC designers pre-configure the TIMER1MS register to contain a correct value by default. But the platforms can support the application clock rate change. If that happens the 1ms timer value must be accordingly updated otherwise the dependent features won't work as expected. In the DWC AHCI driver we suggest to rely on the "aclk" reference clock rate to set the timer interval up. That clock source is supposed to be the AHCI SATA application clock in accordance with the DT bindings. Finally DWC AHCI SATA controller AXI/AHB bus DMA-engine can be tuned up to transfer up to 1024 * FIFO words at a time by setting the Tx/Rx transaction size in the DMA control register. The maximum value depends on the DMA data bus and AXI/AHB bus maximum burst length. In most of the cases it's better to set the maximum possible value to reach the best AHCI SATA controller performance. But sometimes in order to improve the system interconnect responsiveness, transferring in smaller data chunks may be more preferable. For such cases and for the case when the default value doesn't provide the best DMA bus performance we suggest to use the new HBA-port specific DT-properties "snps,{tx,rx}-ts-max" to tune the DMA transactions size up. After all the settings denoted above are handled the DWC AHCI SATA driver proceeds further with the standard AHCI-platform host initializations. Note since DWC AHCI controller is now have a dedicated driver we can discard the corresponding compatible string from the ahci-platform.c module. The same concerns "snps,spear-ahci" compatible string, which is also based on the DWC AHCI IP-core. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- Note there are three more AHCI SATA drivers which have been created for the devices based on the DWC AHCI SATA IP-core. It's AHCI SunXi, St and iMX drivers. Mostly they don't support the features implemented in this driver. So hopefully sometime in future they can be converted to be based on the generic DWC AHCI SATA driver and just perform some subvendor-specific setups in their own LLDD (glue) driver code. But for now let's leave the generic DWC AHCI SATA code as is. Hopefully the new DWC AHCI-based device drivers will try at least to re-use a part of the DWC AHCI driver methods if not being able to be integrated in the generic DWC driver code. Changelog v2: - Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_'. (@Damien) Changelog v4: - Replace GPLv2 with just GPL license which are the same in the framework of the MODULE_LICENSE() macro. Changelog v5: - Drop the "default SATA_AHCI_PLATFORM" setting from the AHCI_DWC config. (@Randy) - Replace deprecated SIMPLE_DEV_PM_OPS() with the DEFINE_SIMPLE_DEV_PM_OPS() macro usage. (@Damien) Changelog v8: - Drop ifdef CONFIG_PM_SLEEP since the DEFINE_SIMPLE_DEV_PM_OPS macro uses the PTR_IF() pattern which implies no if-defs. (@tbot) --- drivers/ata/Kconfig | 9 + drivers/ata/Makefile | 1 + drivers/ata/ahci_dwc.c | 394 ++++++++++++++++++++++++++++++++++++ drivers/ata/ahci_platform.c | 2 - 4 files changed, 404 insertions(+), 2 deletions(-) create mode 100644 drivers/ata/ahci_dwc.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 1c9f4fb2595d..2bd743995ab5 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -176,6 +176,15 @@ config AHCI_DM816 =20 If unsure, say N. =20 +config AHCI_DWC + tristate "Synopsys DWC AHCI SATA support" + select SATA_HOST + help + This option enables support for the Synopsys DWC AHCI SATA + controller implementation. + + If unsure, say N. + config AHCI_ST tristate "ST AHCI SATA support" depends on ARCH_STI diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index b8aebfb14e82..34623365d9a6 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_BRCM) +=3D ahci_brcm.o libahci.o libah= ci_platform.o obj-$(CONFIG_AHCI_CEVA) +=3D ahci_ceva.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DA850) +=3D ahci_da850.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DM816) +=3D ahci_dm816.o libahci.o libahci_platform.o +obj-$(CONFIG_AHCI_DWC) +=3D ahci_dwc.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_IMX) +=3D ahci_imx.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_MTK) +=3D ahci_mtk.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_MVEBU) +=3D ahci_mvebu.o libahci.o libahci_platform.o diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c new file mode 100644 index 000000000000..40c389078ccc --- /dev/null +++ b/drivers/ata/ahci_dwc.c @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DWC AHCI SATA Platform driver + * + * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ahci.h" + +#define DRV_NAME "ahci-dwc" + +#define AHCI_DWC_FBS_PMPN_MAX 15 + +/* DWC AHCI SATA controller specific registers */ +#define AHCI_DWC_HOST_OOBR 0xbc +#define AHCI_DWC_HOST_OOB_WE BIT(31) +#define AHCI_DWC_HOST_CWMIN_MASK GENMASK(30, 24) +#define AHCI_DWC_HOST_CWMAX_MASK GENMASK(23, 16) +#define AHCI_DWC_HOST_CIMIN_MASK GENMASK(15, 8) +#define AHCI_DWC_HOST_CIMAX_MASK GENMASK(7, 0) + +#define AHCI_DWC_HOST_GPCR 0xd0 +#define AHCI_DWC_HOST_GPSR 0xd4 + +#define AHCI_DWC_HOST_TIMER1MS 0xe0 +#define AHCI_DWC_HOST_TIMV_MASK GENMASK(19, 0) + +#define AHCI_DWC_HOST_GPARAM1R 0xe8 +#define AHCI_DWC_HOST_ALIGN_M BIT(31) +#define AHCI_DWC_HOST_RX_BUFFER BIT(30) +#define AHCI_DWC_HOST_PHY_DATA_MASK GENMASK(29, 28) +#define AHCI_DWC_HOST_PHY_RST BIT(27) +#define AHCI_DWC_HOST_PHY_CTRL_MASK GENMASK(26, 21) +#define AHCI_DWC_HOST_PHY_STAT_MASK GENMASK(20, 15) +#define AHCI_DWC_HOST_LATCH_M BIT(14) +#define AHCI_DWC_HOST_PHY_TYPE_MASK GENMASK(13, 11) +#define AHCI_DWC_HOST_RET_ERR BIT(10) +#define AHCI_DWC_HOST_AHB_ENDIAN_MASK GENMASK(9, 8) +#define AHCI_DWC_HOST_S_HADDR BIT(7) +#define AHCI_DWC_HOST_M_HADDR BIT(6) +#define AHCI_DWC_HOST_S_HDATA_MASK GENMASK(5, 3) +#define AHCI_DWC_HOST_M_HDATA_MASK GENMASK(2, 0) + +#define AHCI_DWC_HOST_GPARAM2R 0xec +#define AHCI_DWC_HOST_FBS_MEM_S BIT(19) +#define AHCI_DWC_HOST_FBS_PMPN_MASK GENMASK(17, 16) +#define AHCI_DWC_HOST_FBS_SUP BIT(15) +#define AHCI_DWC_HOST_DEV_CP BIT(14) +#define AHCI_DWC_HOST_DEV_MP BIT(13) +#define AHCI_DWC_HOST_ENCODE_M BIT(12) +#define AHCI_DWC_HOST_RXOOB_CLK_M BIT(11) +#define AHCI_DWC_HOST_RXOOB_M BIT(10) +#define AHCI_DWC_HOST_TXOOB_M BIT(9) +#define AHCI_DWC_HOST_RXOOB_M BIT(10) +#define AHCI_DWC_HOST_RXOOB_CLK_MASK GENMASK(8, 0) + +#define AHCI_DWC_HOST_PPARAMR 0xf0 +#define AHCI_DWC_HOST_TX_MEM_M BIT(11) +#define AHCI_DWC_HOST_TX_MEM_S BIT(10) +#define AHCI_DWC_HOST_RX_MEM_M BIT(9) +#define AHCI_DWC_HOST_RX_MEM_S BIT(8) +#define AHCI_DWC_HOST_TXFIFO_DEPTH GENMASK(7, 4) +#define AHCI_DWC_HOST_RXFIFO_DEPTH GENMASK(3, 0) + +#define AHCI_DWC_HOST_TESTR 0xf4 +#define AHCI_DWC_HOST_PSEL_MASK GENMASK(18, 16) +#define AHCI_DWC_HOST_TEST_IF BIT(0) + +#define AHCI_DWC_HOST_VERSIONR 0xf8 +#define AHCI_DWC_HOST_IDR 0xfc + +#define AHCI_DWC_PORT_DMACR 0x70 +#define AHCI_DWC_PORT_RXABL_MASK GENMASK(15, 12) +#define AHCI_DWC_PORT_TXABL_MASK GENMASK(11, 8) +#define AHCI_DWC_PORT_RXTS_MASK GENMASK(7, 4) +#define AHCI_DWC_PORT_TXTS_MASK GENMASK(3, 0) +#define AHCI_DWC_PORT_PHYCR 0x74 +#define AHCI_DWC_PORT_PHYSR 0x78 + +struct ahci_dwc_host_priv { + struct platform_device *pdev; + + u32 timv; + u32 dmacr[AHCI_MAX_PORTS]; +}; + +static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_devic= e *pdev) +{ + struct ahci_dwc_host_priv *dpriv; + struct ahci_host_priv *hpriv; + + dpriv =3D devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL); + if (!dpriv) + return ERR_PTR(-ENOMEM); + + dpriv->pdev =3D pdev; + + hpriv =3D ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS); + if (IS_ERR(hpriv)) + return hpriv; + + hpriv->plat_data =3D (void *)dpriv; + + return hpriv; +} + +static void ahci_dwc_check_cap(struct ahci_host_priv *hpriv) +{ + unsigned long port_map =3D hpriv->saved_port_map | hpriv->mask_port_map; + struct ahci_dwc_host_priv *dpriv =3D hpriv->plat_data; + bool dev_mp, dev_cp, fbs_sup; + unsigned int fbs_pmp; + u32 param; + int i; + + param =3D readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R); + dev_mp =3D !!(param & AHCI_DWC_HOST_DEV_MP); + dev_cp =3D !!(param & AHCI_DWC_HOST_DEV_CP); + fbs_sup =3D !!(param & AHCI_DWC_HOST_FBS_SUP); + fbs_pmp =3D 5 * FIELD_GET(AHCI_DWC_HOST_FBS_PMPN_MASK, param); + + if (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) { + dev_warn(&dpriv->pdev->dev, "MPS is unsupported\n"); + hpriv->saved_cap &=3D ~HOST_CAP_MPS; + } + + + if (fbs_sup && fbs_pmp < AHCI_DWC_FBS_PMPN_MAX) { + dev_warn(&dpriv->pdev->dev, "PMPn is limited up to %u ports\n", + fbs_pmp); + } + + for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { + if (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) { + dev_warn(&dpriv->pdev->dev, "MPS incapable port %d\n", i); + hpriv->saved_port_cap[i] &=3D ~PORT_CMD_MPSP; + } + + if (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) { + dev_warn(&dpriv->pdev->dev, "CPD incapable port %d\n", i); + hpriv->saved_port_cap[i] &=3D ~PORT_CMD_CPD; + } + + if (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) { + dev_warn(&dpriv->pdev->dev, "FBS incapable port %d\n", i); + hpriv->saved_port_cap[i] &=3D ~PORT_CMD_FBSCP; + } + } +} + +static void ahci_dwc_init_timer(struct ahci_host_priv *hpriv) +{ + struct ahci_dwc_host_priv *dpriv =3D hpriv->plat_data; + unsigned long rate; + struct clk *aclk; + u32 cap, cap2; + + /* 1ms tick is generated only for the CCC or DevSleep features */ + cap =3D readl(hpriv->mmio + HOST_CAP); + cap2 =3D readl(hpriv->mmio + HOST_CAP2); + if (!(cap & HOST_CAP_CCC) && !(cap2 & HOST_CAP2_SDS)) + return; + + /* + * Tick is generated based on the AXI/AHB application clocks signal + * so we need to be sure in the clock we are going to use. + */ + aclk =3D ahci_platform_find_clk(hpriv, "aclk"); + if (!aclk) + return; + + /* 1ms timer interval is set as TIMV =3D AMBA_FREQ[MHZ] * 1000 */ + dpriv->timv =3D readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS); + dpriv->timv =3D FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv); + rate =3D clk_get_rate(aclk) / 1000UL; + if (rate =3D=3D dpriv->timv) + return; + + dev_info(&dpriv->pdev->dev, "Update CCC/DevSlp timer for Fapp %lu MHz\n", + rate / 1000UL); + dpriv->timv =3D FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate); + writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS); +} + +static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv) +{ + struct ahci_dwc_host_priv *dpriv =3D hpriv->plat_data; + struct device_node *child; + void __iomem *port_mmio; + u32 port, dmacr, ts; + + /* + * Update the DMA Tx/Rx transaction sizes in accordance with the + * platform setup. Note values exceeding maximal or minimal limits will + * be automatically clamped. Also note the register isn't affected by + * the HBA global reset so we can freely initialize it once until the + * next system reset. + */ + for_each_child_of_node(dpriv->pdev->dev.of_node, child) { + if (!of_device_is_available(child)) + continue; + + if (of_property_read_u32(child, "reg", &port)) { + of_node_put(child); + return -EINVAL; + } + + port_mmio =3D __ahci_port_base(hpriv, port); + dmacr =3D readl(port_mmio + AHCI_DWC_PORT_DMACR); + + if (!of_property_read_u32(child, "snps,tx-ts-max", &ts)) { + ts =3D ilog2(ts); + dmacr &=3D ~AHCI_DWC_PORT_TXTS_MASK; + dmacr |=3D FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts); + } + + if (!of_property_read_u32(child, "snps,rx-ts-max", &ts)) { + ts =3D ilog2(ts); + dmacr &=3D ~AHCI_DWC_PORT_RXTS_MASK; + dmacr |=3D FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts); + } + + writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR); + dpriv->dmacr[port] =3D dmacr; + } + + return 0; +} + +static int ahci_dwc_init_host(struct ahci_host_priv *hpriv) +{ + int rc; + + rc =3D ahci_platform_enable_resources(hpriv); + if (rc) + return rc; + + ahci_dwc_check_cap(hpriv); + + ahci_dwc_init_timer(hpriv); + + rc =3D ahci_dwc_init_dmacr(hpriv); + if (rc) + goto err_disable_resources; + + return 0; + +err_disable_resources: + ahci_platform_disable_resources(hpriv); + + return rc; +} + +static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv) +{ + struct ahci_dwc_host_priv *dpriv =3D hpriv->plat_data; + unsigned long port_map =3D hpriv->port_map; + void __iomem *port_mmio; + int i, rc; + + rc =3D ahci_platform_enable_resources(hpriv); + if (rc) + return rc; + + writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS); + + for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { + port_mmio =3D __ahci_port_base(hpriv, i); + writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR); + } + + return 0; +} + +static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv) +{ + ahci_platform_disable_resources(hpriv); +} + +static void ahci_dwc_stop_host(struct ata_host *host) +{ + struct ahci_host_priv *hpriv =3D host->private_data; + + ahci_dwc_clear_host(hpriv); +} + +static struct ata_port_operations ahci_dwc_port_ops =3D { + .inherits =3D &ahci_platform_ops, + .host_stop =3D ahci_dwc_stop_host, +}; + +static const struct ata_port_info ahci_dwc_port_info =3D { + .flags =3D AHCI_FLAG_COMMON, + .pio_mask =3D ATA_PIO4, + .udma_mask =3D ATA_UDMA6, + .port_ops =3D &ahci_dwc_port_ops, +}; + +static struct scsi_host_template ahci_dwc_scsi_info =3D { + AHCI_SHT(DRV_NAME), +}; + +static int ahci_dwc_probe(struct platform_device *pdev) +{ + struct ahci_host_priv *hpriv; + int rc; + + hpriv =3D ahci_dwc_get_resources(pdev); + if (IS_ERR(hpriv)) + return PTR_ERR(hpriv); + + rc =3D ahci_dwc_init_host(hpriv); + if (rc) + return rc; + + rc =3D ahci_platform_init_host(pdev, hpriv, &ahci_dwc_port_info, + &ahci_dwc_scsi_info); + if (rc) + goto err_clear_host; + + return 0; + +err_clear_host: + ahci_dwc_clear_host(hpriv); + + return rc; +} + +static int ahci_dwc_suspend(struct device *dev) +{ + struct ata_host *host =3D dev_get_drvdata(dev); + struct ahci_host_priv *hpriv =3D host->private_data; + int rc; + + rc =3D ahci_platform_suspend_host(dev); + if (rc) + return rc; + + ahci_dwc_clear_host(hpriv); + + return 0; +} + +static int ahci_dwc_resume(struct device *dev) +{ + struct ata_host *host =3D dev_get_drvdata(dev); + struct ahci_host_priv *hpriv =3D host->private_data; + int rc; + + rc =3D ahci_dwc_reinit_host(hpriv); + if (rc) + return rc; + + return ahci_platform_resume_host(dev); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend, + ahci_dwc_resume); + +static const struct of_device_id ahci_dwc_of_match[] =3D { + { .compatible =3D "snps,dwc-ahci", }, + { .compatible =3D "snps,spear-ahci", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ahci_dwc_of_match); + +static struct platform_driver ahci_dwc_driver =3D { + .probe =3D ahci_dwc_probe, + .remove =3D ata_platform_remove_one, + .shutdown =3D ahci_platform_shutdown, + .driver =3D { + .name =3D DRV_NAME, + .of_match_table =3D ahci_dwc_of_match, + .pm =3D &ahci_dwc_pm_ops, + }, +}; +module_platform_driver(ahci_dwc_driver); + +MODULE_DESCRIPTION("DWC AHCI SATA platform driver"); +MODULE_AUTHOR("Serge Semin "); +MODULE_LICENSE("GPL"); diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c index 9b56490ecbc3..8f5572a9f8f1 100644 --- a/drivers/ata/ahci_platform.c +++ b/drivers/ata/ahci_platform.c @@ -80,9 +80,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspe= nd, static const struct of_device_id ahci_of_match[] =3D { { .compatible =3D "generic-ahci", }, /* Keep the following compatibles for device tree compatibility */ - { .compatible =3D "snps,spear-ahci", }, { .compatible =3D "ibm,476gtr-ahci", }, - { .compatible =3D "snps,dwc-ahci", }, { .compatible =3D "hisilicon,hisi-ahci", }, { .compatible =3D "cavium,octeon-7130-ahci", }, { /* sentinel */ } --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4656CECAAD3 for ; Fri, 9 Sep 2022 19:39:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232114AbiIITjR (ORCPT ); Fri, 9 Sep 2022 15:39:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231824AbiIITiM (ORCPT ); Fri, 9 Sep 2022 15:38:12 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BA7F3139C20; Fri, 9 Sep 2022 12:36:55 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id C62C5DB9; Fri, 9 Sep 2022 22:40:34 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com C62C5DB9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752434; bh=K3vap0FpFoGMz05xBagElq3cuTU5ZyDcEp63VapujxY=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=XEIlIEdjLShNl6K4fV3jXjZ4H4k53kd74RVy138R493p+QhQWmY1B2EKzjeAU/zg8 jVqyx+sYHEtQz5QZcMh3mgQGayUT0d8i33WWztv9swAplo+bxL602VOp3eHWJaioWV Bo2kDFKmsDQUBHL3El7AwbaSFgOVjW3oWhUwyQ2E= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:46 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Serge Semin , Rob Herring , Krzysztof Kozlowski CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , , , , Rob Herring Subject: [PATCH v8 20/23] dt-bindings: ata: ahci: Add Baikal-T1 AHCI SATA controller DT schema Date: Fri, 9 Sep 2022 22:36:18 +0300 Message-ID: <20220909193621.17380-21-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Baikal-T1 AHCI controller is based on the DWC AHCI SATA IP-core v4.10a with the next specific settings: two SATA ports, cascaded CSR access based on two clock domains (APB and AXI), selectable source of the reference clock (though stable work is currently available from the external source only), two reset lanes for the application and SATA ports domains. Other than that the device is fully compatible with the generic DWC AHCI SATA bindings. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke Reviewed-by: Rob Herring --- Changelog v2: - Rename 'syscon' property to 'baikal,bt1-syscon'. - Drop macro usage from the example node. Changelog v4: - Use the DWC AHCI port properties definition from the DWC AHCI SATA common schema. (@Rob) - Drop Baikal-T1 syscon reference and implement the clock signal source in the framework of the clock controller. (@Rob) Changelog v5: - Drop generic compatible fallback "snps,dwc-ahci". (@Rob) - Define SATA-port pattern property to be applicable for two ports only. - Drop "|" qualifier from the description property. --- .../bindings/ata/baikal,bt1-ahci.yaml | 115 ++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/baikal,bt1-ahci.y= aml diff --git a/Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml b/D= ocumentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml new file mode 100644 index 000000000000..9b7ca4759bd7 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 SoC AHCI SATA controller + +maintainers: + - Serge Semin + +description: + AHCI SATA controller embedded into the Baikal-T1 SoC is based on the + DWC AHCI SATA v4.10a IP-core. + +allOf: + - $ref: snps,dwc-ahci-common.yaml# + +properties: + compatible: + const: baikal,bt1-ahci + + clocks: + items: + - description: Peripheral APB bus clock + - description: Application AXI BIU clock + - description: SATA Ports reference clock + + clock-names: + items: + - const: pclk + - const: aclk + - const: ref + + resets: + items: + - description: Application AXI BIU domain reset + - description: SATA Ports clock domain reset + + reset-names: + items: + - const: arst + - const: ref + + ports-implemented: + maximum: 0x3 + +patternProperties: + "^sata-port@[0-1]$": + $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port + + properties: + reg: + minimum: 0 + maximum: 1 + + snps,tx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Due to having AXI3 bus interface utilized the maximum Tx DMA + transaction size can't exceed 16 beats (AxLEN[3:0]). + enum: [ 1, 2, 4, 8, 16 ] + + snps,rx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Due to having AXI3 bus interface utilized the maximum Rx DMA + transaction size can't exceed 16 beats (AxLEN[3:0]). + enum: [ 1, 2, 4, 8, 16 ] + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + sata@1f050000 { + compatible =3D "baikal,bt1-ahci"; + reg =3D <0x1f050000 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + interrupts =3D <0 64 4>; + + clocks =3D <&ccu_sys 1>, <&ccu_axi 2>, <&sata_ref_clk>; + clock-names =3D "pclk", "aclk", "ref"; + + resets =3D <&ccu_axi 2>, <&ccu_sys 0>; + reset-names =3D "arst", "ref"; + + ports-implemented =3D <0x3>; + + sata-port@0 { + reg =3D <0>; + + snps,tx-ts-max =3D <4>; + snps,rx-ts-max =3D <4>; + }; + + sata-port@1 { + reg =3D <1>; + + snps,tx-ts-max =3D <4>; + snps,rx-ts-max =3D <4>; + }; + }; +... --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05AB5ECAAD3 for ; Fri, 9 Sep 2022 19:38:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232099AbiIITiz (ORCPT ); Fri, 9 Sep 2022 15:38:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231772AbiIIThy (ORCPT ); Fri, 9 Sep 2022 15:37:54 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0D72413EE44; Fri, 9 Sep 2022 12:36:56 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 729BEDC6; Fri, 9 Sep 2022 22:40:35 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 729BEDC6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752435; bh=+d0IjE2Mjg9F9YXEHISfURAzUn09BiXSfgKgqDoXKZg=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=aZH3283x1HFlq5tQ7aFCuOq0wXrySF8QQ31yybk7lWf87P+XRLHZAeHjqk0WjFG6J hHB6LRJfPG6trmfvQKna4QWGJJRc07jSf+UF5GFECoHzhorke9+/MN9tAkQknx4W7o gsSH125vWmFqMESkm8g5ejCcEJQKWQHaXlIgV/AE= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:46 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Serge Semin CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 21/23] ata: ahci-dwc: Add platform-specific quirks support Date: Fri, 9 Sep 2022 22:36:19 +0300 Message-ID: <20220909193621.17380-22-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some DWC AHCI SATA IP-core derivatives require to perform small platform or IP-core specific setups. They are too small to be placed in a dedicated driver. It's just much easier to have a set of quirks for them right in the DWC AHCI driver code. Since we are about to add such platform support, as a pre-requisite we introduce a platform-data based DWC AHCI quirks API. The platform data can be used to define the flags passed to the ahci_platform_get_resources() method, additional AHCI host-flags and a set of callbacks to initialize, re-initialize and clear the platform settings. Signed-off-by: Serge Semin --- Changelog v2: - Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_'. (@Damien) Changelog v4: - Convert ahci_dwc_plat to being statically defined. (@kbot) --- drivers/ata/ahci_dwc.c | 52 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c index 40c389078ccc..6e64d3502669 100644 --- a/drivers/ata/ahci_dwc.c +++ b/drivers/ata/ahci_dwc.c @@ -90,7 +90,16 @@ #define AHCI_DWC_PORT_PHYCR 0x74 #define AHCI_DWC_PORT_PHYSR 0x78 =20 +struct ahci_dwc_plat_data { + unsigned int pflags; + unsigned int hflags; + int (*init)(struct ahci_host_priv *hpriv); + int (*reinit)(struct ahci_host_priv *hpriv); + void (*clear)(struct ahci_host_priv *hpriv); +}; + struct ahci_dwc_host_priv { + const struct ahci_dwc_plat_data *pdata; struct platform_device *pdev; =20 u32 timv; @@ -107,11 +116,15 @@ static struct ahci_host_priv *ahci_dwc_get_resources(= struct platform_device *pde return ERR_PTR(-ENOMEM); =20 dpriv->pdev =3D pdev; + dpriv->pdata =3D device_get_match_data(&pdev->dev); + if (!dpriv->pdata) + return ERR_PTR(-EINVAL); =20 - hpriv =3D ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS); + hpriv =3D ahci_platform_get_resources(pdev, dpriv->pdata->pflags); if (IS_ERR(hpriv)) return hpriv; =20 + hpriv->flags |=3D dpriv->pdata->hflags; hpriv->plat_data =3D (void *)dpriv; =20 return hpriv; @@ -242,22 +255,33 @@ static int ahci_dwc_init_dmacr(struct ahci_host_priv = *hpriv) =20 static int ahci_dwc_init_host(struct ahci_host_priv *hpriv) { + struct ahci_dwc_host_priv *dpriv =3D hpriv->plat_data; int rc; =20 rc =3D ahci_platform_enable_resources(hpriv); if (rc) return rc; =20 + if (dpriv->pdata->init) { + rc =3D dpriv->pdata->init(hpriv); + if (rc) + goto err_disable_resources; + } + ahci_dwc_check_cap(hpriv); =20 ahci_dwc_init_timer(hpriv); =20 rc =3D ahci_dwc_init_dmacr(hpriv); if (rc) - goto err_disable_resources; + goto err_clear_platform; =20 return 0; =20 +err_clear_platform: + if (dpriv->pdata->clear) + dpriv->pdata->clear(hpriv); + err_disable_resources: ahci_platform_disable_resources(hpriv); =20 @@ -275,6 +299,12 @@ static int ahci_dwc_reinit_host(struct ahci_host_priv = *hpriv) if (rc) return rc; =20 + if (dpriv->pdata->reinit) { + rc =3D dpriv->pdata->reinit(hpriv); + if (rc) + goto err_disable_resources; + } + writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS); =20 for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) { @@ -283,10 +313,20 @@ static int ahci_dwc_reinit_host(struct ahci_host_priv= *hpriv) } =20 return 0; + +err_disable_resources: + ahci_platform_disable_resources(hpriv); + + return rc; } =20 static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv) { + struct ahci_dwc_host_priv *dpriv =3D hpriv->plat_data; + + if (dpriv->pdata->clear) + dpriv->pdata->clear(hpriv); + ahci_platform_disable_resources(hpriv); } =20 @@ -370,9 +410,13 @@ static int ahci_dwc_resume(struct device *dev) static DEFINE_SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend, ahci_dwc_resume); =20 +static struct ahci_dwc_plat_data ahci_dwc_plat =3D { + .pflags =3D AHCI_PLATFORM_GET_RESETS, +}; + static const struct of_device_id ahci_dwc_of_match[] =3D { - { .compatible =3D "snps,dwc-ahci", }, - { .compatible =3D "snps,spear-ahci", }, + { .compatible =3D "snps,dwc-ahci", &ahci_dwc_plat }, + { .compatible =3D "snps,spear-ahci", &ahci_dwc_plat }, {}, }; MODULE_DEVICE_TABLE(of, ahci_dwc_of_match); --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63D1EECAAA1 for ; Fri, 9 Sep 2022 19:39:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232128AbiIITjj (ORCPT ); Fri, 9 Sep 2022 15:39:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231552AbiIITiP (ORCPT ); Fri, 9 Sep 2022 15:38:15 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 39BB9143429; Fri, 9 Sep 2022 12:36:57 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 4C37FDBB; Fri, 9 Sep 2022 22:40:36 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 4C37FDBB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752436; bh=B0pHOqIv7yMx94uq48K3bbTuVxKryRZMuCZVYN11Yys=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Mnwf1w7BMAcX3TDPe2HBJbSnwDvpoUA8LDKU/PMb0529rRhXqj34+TztZihC2L8lB wyWPwK04fhbxmY9Sp9opPswNdyV6kEfUReapgIQMPIsWhfdHxYmTDoGvE8kqIy8a5y nsocR/Gv4HrupwTKvoP3KsulY8tdXGVUGlgRE49k= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:47 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke , Serge Semin CC: Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 22/23] ata: ahci-dwc: Add Baikal-T1 AHCI SATA interface support Date: Fri, 9 Sep 2022 22:36:20 +0300 Message-ID: <20220909193621.17380-23-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It's almost fully compatible DWC AHCI SATA IP-core derivative except the reference clocks source, which need to be very carefully selected. In particular the DWC AHCI SATA PHY can be clocked either from the pads ref_pad_clk_{m,p} or from the internal wires ref_alt_clk_{m,n}. In the later case the clock signal is generated from the Baikal-T1 CCU SATA PLL. The clocks source is selected by means of the ref_use_pad wire connected to the CCU SATA reference clock CSR. In normal situation it would be much more handy to use the internal reference clock source, but alas we haven't managed to make the AHCI controller working well with it so far. So it's preferable to have the controller clocked from the external clock generator and fallback to the internal clock source only as a last resort. Other than that the controller is full compatible with the DWC AHCI SATA IP-core. Signed-off-by: Serge Semin Reviewed-by: Hannes Reinecke --- Changelog v2: - Rename 'syscon' property to 'baikal,bt1-syscon'. - Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_', from 'bt1_ahci_' to 'ahci_bt1_'. (@Damien) Changelog v4: - Convert ahci_bt1_plat to being statically defined. (@kbot) - Drop Baikal-T1 syscon reference relying on the clock controller and the platform setup having the proper clock source selected. (@Rob) --- drivers/ata/Kconfig | 1 + drivers/ata/ahci_dwc.c | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 2bd743995ab5..c8f9cf564b95 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -179,6 +179,7 @@ config AHCI_DM816 config AHCI_DWC tristate "Synopsys DWC AHCI SATA support" select SATA_HOST + select MFD_SYSCON if (MIPS_BAIKAL_T1 || COMPILE_TEST) help This option enables support for the Synopsys DWC AHCI SATA controller implementation. diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c index 6e64d3502669..8fb66860db31 100644 --- a/drivers/ata/ahci_dwc.c +++ b/drivers/ata/ahci_dwc.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include #include +#include =20 #include "ahci.h" =20 @@ -90,6 +92,20 @@ #define AHCI_DWC_PORT_PHYCR 0x74 #define AHCI_DWC_PORT_PHYSR 0x78 =20 +/* Baikal-T1 AHCI SATA specific registers */ +#define AHCI_BT1_HOST_PHYCR AHCI_DWC_HOST_GPCR +#define AHCI_BT1_HOST_MPLM_MASK GENMASK(29, 23) +#define AHCI_BT1_HOST_LOSDT_MASK GENMASK(22, 20) +#define AHCI_BT1_HOST_CRR BIT(19) +#define AHCI_BT1_HOST_CRW BIT(18) +#define AHCI_BT1_HOST_CRCD BIT(17) +#define AHCI_BT1_HOST_CRCA BIT(16) +#define AHCI_BT1_HOST_CRDI_MASK GENMASK(15, 0) + +#define AHCI_BT1_HOST_PHYSR AHCI_DWC_HOST_GPSR +#define AHCI_BT1_HOST_CRA BIT(16) +#define AHCI_BT1_HOST_CRDO_MASK GENMASK(15, 0) + struct ahci_dwc_plat_data { unsigned int pflags; unsigned int hflags; @@ -106,6 +122,39 @@ struct ahci_dwc_host_priv { u32 dmacr[AHCI_MAX_PORTS]; }; =20 +static int ahci_bt1_init(struct ahci_host_priv *hpriv) +{ + struct ahci_dwc_host_priv *dpriv =3D hpriv->plat_data; + int ret; + + /* APB, application and reference clocks are required */ + if (!ahci_platform_find_clk(hpriv, "pclk") || + !ahci_platform_find_clk(hpriv, "aclk") || + !ahci_platform_find_clk(hpriv, "ref")) { + dev_err(&dpriv->pdev->dev, "No system clocks specified\n"); + return -EINVAL; + } + + /* + * Fully reset the SATA AXI and ref clocks domain to ensure the state + * machine is working from scratch especially if the reference clocks + * source has been changed. + */ + ret =3D ahci_platform_assert_rsts(hpriv); + if (ret) { + dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n"); + return ret; + } + + ret =3D ahci_platform_deassert_rsts(hpriv); + if (ret) { + dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n"); + return ret; + } + + return 0; +} + static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_devic= e *pdev) { struct ahci_dwc_host_priv *dpriv; @@ -414,9 +463,15 @@ static struct ahci_dwc_plat_data ahci_dwc_plat =3D { .pflags =3D AHCI_PLATFORM_GET_RESETS, }; =20 +static struct ahci_dwc_plat_data ahci_bt1_plat =3D { + .pflags =3D AHCI_PLATFORM_GET_RESETS | AHCI_PLATFORM_RST_TRIGGER, + .init =3D ahci_bt1_init, +}; + static const struct of_device_id ahci_dwc_of_match[] =3D { { .compatible =3D "snps,dwc-ahci", &ahci_dwc_plat }, { .compatible =3D "snps,spear-ahci", &ahci_dwc_plat }, + { .compatible =3D "baikal,bt1-ahci", &ahci_bt1_plat }, {}, }; MODULE_DEVICE_TABLE(of, ahci_dwc_of_match); --=20 2.37.2 From nobody Wed Apr 8 08:01:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99F9FECAAD3 for ; Fri, 9 Sep 2022 19:39:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232136AbiIITjn (ORCPT ); Fri, 9 Sep 2022 15:39:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231848AbiIITiP (ORCPT ); Fri, 9 Sep 2022 15:38:15 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3AD1512A30C; Fri, 9 Sep 2022 12:36:59 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 1FF9DDBC; Fri, 9 Sep 2022 22:40:37 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 1FF9DDBC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662752437; bh=XhHryGSZHGP03Jv9lWNGiOTfawDZbC1lKYZsUpCgoPE=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=f3ZxPHEwbSW0BwgxmIIJuW7MNqads3okGsX9m8mbXX9xf3xo/edZr0OobgzCh5CME j3IzwQ9hARPRyYwOO7eCLAY2fOf+C4t2ENAI+IYdsq4b3CCY4yb9l2MH8C9JrW5nNC Uqlowcv/v3XqB3A/DiEb2HkUKPwGS/T0rd5YQg7k= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 9 Sep 2022 22:36:48 +0300 From: Serge Semin To: Damien Le Moal , Hans de Goede , Jens Axboe , Hannes Reinecke CC: Serge Semin , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Rob Herring , Krzysztof Kozlowski , , , Subject: [PATCH v8 23/23] MAINTAINERS: Add maintainers for DWC AHCI SATA driver Date: Fri, 9 Sep 2022 22:36:21 +0300 Message-ID: <20220909193621.17380-24-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> References: <20220909193621.17380-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add myself as a maintainer of the new DWC AHCI SATA driver and its DT-bindings schema. Signed-off-by: Serge Semin --- Changelog v2: - Use dlemoal/libata.git git tree for the LIBATA SATA AHCI SYNOPSYS DWC driver (@Damien). --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9d7f64dc0efe..7a1cb5ff19cd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11552,6 +11552,15 @@ F: drivers/ata/ahci_platform.c F: drivers/ata/libahci_platform.c F: include/linux/ahci_platform.h =20 +LIBATA SATA AHCI SYNOPSYS DWC CONTROLLER DRIVER +M: Serge Semin +L: linux-ide@vger.kernel.org +S: Maintained +T: git git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata.git +F: Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml +F: Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml +F: drivers/ata/ahci_dwc.c + LIBATA SATA PROMISE TX2/TX4 CONTROLLER DRIVER M: Mikael Pettersson L: linux-ide@vger.kernel.org --=20 2.37.2