From nobody Mon Apr 6 08:06:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF247C38145 for ; Thu, 8 Sep 2022 15:49:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231674AbiIHPtS (ORCPT ); Thu, 8 Sep 2022 11:49:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229624AbiIHPtM (ORCPT ); Thu, 8 Sep 2022 11:49:12 -0400 Received: from finn.localdomain (finn.gateworks.com [108.161.129.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB35EAD99F; Thu, 8 Sep 2022 08:49:11 -0700 (PDT) Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1oWJm5-00GV3a-J1; Thu, 08 Sep 2022 15:49:05 +0000 From: Tim Harvey To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: NXP Linux Team , Fabio Estevam , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Krzysztof Kozlowski , Rob Herring , Tim Harvey Subject: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add PCIe support Date: Thu, 8 Sep 2022 08:49:03 -0700 Message-Id: <20220908154903.4100386-1-tharvey@gateworks.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PCIe support on the Gateworks GW74xx board. While at it, fix the related gpio line names from the previous incorrect values. Signed-off-by: Tim Harvey --- .../dts/freescale/imx8mp-venice-gw74xx.dts | 40 +++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/= arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index e0fe356b662d..7644db61d631 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include "imx8mp.dtsi" =20 @@ -100,6 +101,12 @@ led-1 { }; }; =20 + pcie0_refclk: pcie0-refclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + pps { compatible =3D "pps-gpio"; pinctrl-names =3D "default"; @@ -215,8 +222,8 @@ &gpio1 { &gpio2 { gpio-line-names =3D "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", + "", "", "", "", "", "", "pcie3_wdis#", "", + "", "", "pcie2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; =20 @@ -562,6 +569,28 @@ &i2c4 { status =3D "okay"; }; =20 +&pcie_phy { + fsl,refclk-pad-mode =3D ; + fsl,clkreq-unsupported; + clocks =3D <&pcie0_refclk>; + clock-names =3D "ref"; + status =3D "okay"; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcie0>; + reset-gpio =3D <&gpio2 17 GPIO_ACTIVE_LOW>; + clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names =3D "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks =3D <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates =3D <10000000>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL2_50M>; + status =3D "okay"; +}; + /* GPS / off-board header */ &uart1 { pinctrl-names =3D "default"; @@ -694,7 +723,6 @@ pinctrl_hog: hoggrp { MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */ MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ @@ -807,6 +835,12 @@ MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 >; }; =20 + pinctrl_pcie0: pciegrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins =3D < MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 --=20 2.25.1