From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BB7BC38145 for ; Wed, 7 Sep 2022 15:59:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230002AbiIGP7W (ORCPT ); Wed, 7 Sep 2022 11:59:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229925AbiIGP7P (ORCPT ); Wed, 7 Sep 2022 11:59:15 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE8D4B8F19 for ; Wed, 7 Sep 2022 08:59:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566354; x=1694102354; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yfA4CNwJAJ4VUJ6uoZRsu0YLI1UJHJwg6/XHOvPCJnI=; b=PMmsrEACpHbTlSnTBgUIM8ccbpt+zbJqc294x1BB/LE8t2AltrdOUkcc aIpL6iWdY9oFLG+E4GCAfaSfTpXb04/YfMmiCE4AxHt4+rBRTVIhrbeTb 1K6BRryGGAVtae7dYGKbYklqmb5FW36lxMJH1+tI6uaqB8qoBSwT+Liw6 WrVOdnTbimsealywPl8VdNAz21foK5G+sn5/LsccwgFpvN+7YCr5NVPYy Ij8hhs94khwm00V4+paFlr8ibaM93Q43L+LuG8hTSRDjPv+qO5xLkZSVv /f/GqnwMgrYo5Ukm7ztSwmQDhaI9rDF3r5sUQ9dWy8cJEWqyoCjm1V/hv A==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="294501427" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="294501427" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:45 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676247503" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:40 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Daniele Ceraolo Spurio Subject: [PATCH v8 01/16] drm/i915/gsc: skip irq initialization if using polling Date: Wed, 7 Sep 2022 18:57:58 +0300 Message-Id: <20220907155813.1427526-2-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vitaly Lubart Some platforms require the host to poll on the GSC registers instead of relaying on the interrupts. For those platforms, irq initialization should be skipped Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Reviewed-by: Daniele Ceraolo Spurio Acked-by: Greg Kroah-Hartman --- drivers/gpu/drm/i915/gt/intel_gsc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index 0e494028b81d..e0236ff1d072 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -40,6 +40,7 @@ struct gsc_def { const char *name; unsigned long bar; size_t bar_size; + bool use_polling; }; =20 /* gsc resources and definitions (HECI1 and HECI2) */ @@ -117,6 +118,10 @@ static void gsc_init_one(struct drm_i915_private *i915, return; } =20 + /* skip irq initialization */ + if (def->use_polling) + goto add_device; + intf->irq =3D irq_alloc_desc(0); if (intf->irq < 0) { drm_err(&i915->drm, "gsc irq error %d\n", intf->irq); @@ -129,6 +134,7 @@ static void gsc_init_one(struct drm_i915_private *i915, goto fail; } =20 +add_device: adev =3D kzalloc(sizeof(*adev), GFP_KERNEL); if (!adev) goto fail; @@ -182,10 +188,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsig= ned int intf_id) return; } =20 - if (gt->gsc.intf[intf_id].irq < 0) { - drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set"); + if (gt->gsc.intf[intf_id].irq < 0) return; - } =20 ret =3D generic_handle_irq(gt->gsc.intf[intf_id].irq); if (ret) --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5AD2C6FA89 for ; Wed, 7 Sep 2022 15:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230047AbiIGP73 (ORCPT ); Wed, 7 Sep 2022 11:59:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229891AbiIGP7T (ORCPT ); Wed, 7 Sep 2022 11:59:19 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4349E8A7D9 for ; Wed, 7 Sep 2022 08:59:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566358; x=1694102358; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p2EcS4Ec16euTVgTxkfMDzoAcraThNKdjheL2DjQbLU=; b=RKke/zNnE7FLex3MN93HscHGbTafZw9Ft98yHGx7M8ulPqha1EmqNtUA vEbtpTJ96yjf7RZkIMhTkn9xLrbkGYnC05ZUvBSvRT4YN3/zXKd64YrIj PqnPfWAr82O3aR5YTZ/7Dm9SY4fWboKg1uuV+k+6rRmK5PB+KbyTRDw+N dMlWomBZgzb8T3I6rpdU69nIL2XK8XNRn+j27W76vNpuXkrHYvpEEVHs0 ZEIftflxvF48AR9Zex8V5crCiMRdEAajPimWhXsSWk1DEH4m3QLUKXH2c vBWDlR+s2kBv64KyJvPjxJJgznImYFL2dEs1cyRIc2ha8EovHBuxX8YZu w==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="294501457" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="294501457" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:48 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676247561" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:45 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart Subject: [PATCH v8 02/16] mei: add kdoc for struct mei_aux_device Date: Wed, 7 Sep 2022 18:57:59 +0300 Message-Id: <20220907155813.1427526-3-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" struct mei_aux_device is an interface structure requires proper documenation. Signed-off-by: Tomas Winkler Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- include/linux/mei_aux.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h index 587f25128848..a0cb587006d5 100644 --- a/include/linux/mei_aux.h +++ b/include/linux/mei_aux.h @@ -7,6 +7,12 @@ =20 #include =20 +/** + * struct mei_aux_device - mei auxiliary device + * @aux_dev: - auxiliary device object + * @irq: interrupt driving the mei auxiliary device + * @bar: mmio resource bar reserved to mei auxiliary device + */ struct mei_aux_device { struct auxiliary_device aux_dev; int irq; --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E62DCC38145 for ; Wed, 7 Sep 2022 15:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229700AbiIGP7h (ORCPT ); Wed, 7 Sep 2022 11:59:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230006AbiIGP71 (ORCPT ); Wed, 7 Sep 2022 11:59:27 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7034E2AD for ; Wed, 7 Sep 2022 08:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566362; x=1694102362; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Iy/GwtvTwnOLfIT1uF2eHNyE186PGpbmZLR7bVd678Q=; b=TO3m6x/YV5NnN7cX3xkOXGm7qWrXLzWMLKrxdOxbebFiTRigle6iIC0q U54oJYLfVTB13BgXlagLDgKlq1JWPuFEih2dmDUjmiCwyHqEhXag0gPcb l9kFdhpls45sJ3xiyUUG0J/DBQCLTMnfMQpENdrjtEZc7iLXA2tQ6/H62 eBIZ9K9HVjtRlx596OiNIHXNcGreDVlG2eeg5NUicShulivXrWh38c6Uh xOwQ0UWg4uGIiM2srP1nj2yurVLQF0Vl1tSX2HebEJSo4yM/XRx7JiJ1r +Q+HRKQyr2XHSRTBpPZh1lXTM9KOqY2ZxTTpoZCZdzd0TwWEIft6LaNKi A==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="294501509" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="294501509" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:53 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676247614" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:49 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Daniele Ceraolo Spurio Subject: [PATCH v8 03/16] mei: add slow_firmware flag to the mei auxiliary device Date: Wed, 7 Sep 2022 18:58:00 +0300 Message-Id: <20220907155813.1427526-4-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add slow_firmware flag to the mei auxiliary device info to inform the mei driver about slow underlying firmware. Such firmware will require to use larger operation timeouts. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio Acked-by: Greg Kroah-Hartman --- include/linux/mei_aux.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h index a0cb587006d5..4894d8bf4159 100644 --- a/include/linux/mei_aux.h +++ b/include/linux/mei_aux.h @@ -12,11 +12,14 @@ * @aux_dev: - auxiliary device object * @irq: interrupt driving the mei auxiliary device * @bar: mmio resource bar reserved to mei auxiliary device + * @slow_firmware: The device has slow underlying firmware. + * Such firmware will require to use larger operation time= outs. */ struct mei_aux_device { struct auxiliary_device aux_dev; int irq; struct resource bar; + bool slow_firmware; }; =20 #define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \ --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33ECAC38145 for ; Wed, 7 Sep 2022 15:59:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229531AbiIGP7N (ORCPT ); Wed, 7 Sep 2022 11:59:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229644AbiIGP7K (ORCPT ); Wed, 7 Sep 2022 11:59:10 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E91E8A7D9 for ; Wed, 7 Sep 2022 08:59:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566349; x=1694102349; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TTXR9ShdBo6b3pl//qZEyY3h/5RE4z/vTOv/CpOgz1M=; b=E1dxf2U9tL3du2i79Qi5JV6+uxjyCzOn9iAv48Qs3UKTUmqgSJwevNn4 wS6vMv9ymT2/RT+aWv28j2Ta4OiYF0ncNFW5nTnzjC9Es12vRiWJB4Rj2 JJ/Een43BHfwMvGEf9sJo9vgWUw4FpCLlx+tSZQuv8qJvgD1h+CXgIdHS RHfWu9NKsDFVvVDQY8xqBzjCSDq9qxJxJ7X5IhhenHYfHEWj7mRS2Q30t uol4kevcjY+CiepOlDCSjriCq0aCE7Ynux20eCNU3INAcjpSCR0dmujH8 9SpD3xxYR7EhBS8TRjIYbLOUSQhUodF+Ko/OW/PM6n5ZgDJ3jac66um9i A==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701071" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701071" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:59 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676247662" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:53 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Daniele Ceraolo Spurio Subject: [PATCH v8 04/16] drm/i915/gsc: add slow_firmware flag to the gsc device definition Date: Wed, 7 Sep 2022 18:58:01 +0300 Message-Id: <20220907155813.1427526-5-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Add slow_firmware flag to the gsc device definition and pass it to mei auxiliary device, this instructs the driver to use longer operation timeouts. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Reviewed-by: Daniele Ceraolo Spurio Acked-by: Greg Kroah-Hartman --- drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index e0236ff1d072..73498c2574c8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -41,6 +41,7 @@ struct gsc_def { unsigned long bar; size_t bar_size; bool use_polling; + bool slow_firmware; }; =20 /* gsc resources and definitions (HECI1 and HECI2) */ @@ -145,6 +146,7 @@ static void gsc_init_one(struct drm_i915_private *i915, adev->bar.end =3D adev->bar.start + def->bar_size - 1; adev->bar.flags =3D IORESOURCE_MEM; adev->bar.desc =3D IORES_DESC_NONE; + adev->slow_firmware =3D def->slow_firmware; =20 aux_dev =3D &adev->aux_dev; aux_dev->name =3D def->name; --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8503C38145 for ; Wed, 7 Sep 2022 15:59:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229559AbiIGP70 (ORCPT ); Wed, 7 Sep 2022 11:59:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229953AbiIGP7R (ORCPT ); Wed, 7 Sep 2022 11:59:17 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E47AB8F19 for ; Wed, 7 Sep 2022 08:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566357; x=1694102357; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TyuRlis55UMm+cKEWzJQdtL+A9hqNaNXtqYaGsH3QG4=; b=TCEXCl8g0M6ALugucF5n9z6ZlTdIdgrmdcH21+Im6cV2Zt+XQjVhcRuL /0brC7jcGW5ALU8sT6QNqqAPw1yNa5+gGNJ8S4F3k/e7JLl6Zi65THC06 dezhCQalJ4EcgEpFHdwvVXDdWE/zxLRTiYeA0Vm+3eCFjp9kDrt080kNz rz8A1BJB4em/LNa1UOFYLER6CWigWxoiZgwCvzAbNXGeJ7RWGdV5sR57S DSWdw2U+REFM0iR+fiVyl6Q7rKXOVe1OC1zxzBOz5KTEfrYXpdZK6R7qm ilgeUlIL4yh4Robr872KaaKGDR1yaGNEhcsefsVIc8iZIQ4lRhNTJpA9/ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701136" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701136" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:03 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676247706" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:58:58 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart Subject: [PATCH v8 05/16] drm/i915/gsc: add GSC XeHP SDV platform definition Date: Wed, 7 Sep 2022 18:58:02 +0300 Message-Id: <20220907155813.1427526-6-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Define GSC on XeHP SDV (Intel(R) dGPU without display) XeHP SDV uses the same hardware settings as DG1, but uses polling instead of interrupts and runs the firmware in slow pace due to hardware limitations. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index 73498c2574c8..e1040c8f2fd3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] =3D { } }; =20 +static const struct gsc_def gsc_def_xehpsdv[] =3D { + { + /* HECI1 not enabled on the device. */ + }, + { + .name =3D "mei-gscfi", + .bar =3D DG1_GSC_HECI2_BASE, + .bar_size =3D GSC_BAR_LENGTH, + .use_polling =3D true, + .slow_firmware =3D true, + } +}; + static const struct gsc_def gsc_def_dg2[] =3D { { .name =3D "mei-gsc", @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915, =20 if (IS_DG1(i915)) { def =3D &gsc_def_dg1[intf_id]; + } else if (IS_XEHPSDV(i915)) { + def =3D &gsc_def_xehpsdv[intf_id]; } else if (IS_DG2(i915)) { def =3D &gsc_def_dg2[intf_id]; } else { --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94F3FC54EE9 for ; Wed, 7 Sep 2022 15:59:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229582AbiIGP7n (ORCPT ); Wed, 7 Sep 2022 11:59:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230007AbiIGP71 (ORCPT ); Wed, 7 Sep 2022 11:59:27 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFB2CB27 for ; Wed, 7 Sep 2022 08:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566362; x=1694102362; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VreGbiZvIAINB9oLeQ724oWr+cN1/CMs6zSx+rr+P8I=; b=HuJC34FmtDxSfJSoPUW00MSkNSPqB5TVMFGUnhx+vL88qoo0W6y8oTAT xqwISavI8FOpFk3s9OUgOKxMWkUrXkVyxnanqXVPijEO2cII96Jxv4vC0 q8JZjR0TPv5S+TGIePLPpxx7ob3ZwXunkfXpvlB6nt9rGO8qbCPqOAy5V u7W83JJKiwM6c2YzWNC+rH5aHVhGnkyQXNntmzm+1HxzSc3D3tdO1Oz+p lXZORC7VztPHZ/wQOI+GFHw4vjFv36Y3P4yP+ZXXNBlz31IeT2VXYlyo9 vScAEHb7Py0eC81ruSyyoHq3igCcNBbvZBzYk13TLnD+X2ag/eXJCOtz4 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701212" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701212" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:07 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676247797" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:03 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , James Ausmus Subject: [PATCH v8 06/16] mei: gsc: use polling instead of interrupts Date: Wed, 7 Sep 2022 18:58:03 +0300 Message-Id: <20220907155813.1427526-7-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" A work-around for a HW issue in XEHPSDV that manifests itself when SW reads a gsc register when gsc is sending an interrupt. The work-around is to disable interrupts and to use polling instead. Cc: James Ausmus Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/gsc-me.c | 48 ++++++++++++++++++----- drivers/misc/mei/hw-me.c | 80 ++++++++++++++++++++++++++++++++++++--- drivers/misc/mei/hw-me.h | 15 +++++++- 3 files changed, 128 insertions(+), 15 deletions(-) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index c8145e9b62b6..2caba3a9ac35 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include "mei_dev.h" #include "hw-me.h" @@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_d= ev, =20 dev_set_drvdata(device, dev); =20 - ret =3D devm_request_threaded_irq(device, hw->irq, - mei_me_irq_quick_handler, - mei_me_irq_thread_handler, - IRQF_ONESHOT, KBUILD_MODNAME, dev); - if (ret) { - dev_err(device, "irq register failed %d\n", ret); - goto err; + /* use polling */ + if (mei_me_hw_use_polling(hw)) { + mei_disable_interrupts(dev); + mei_clear_interrupts(dev); + init_waitqueue_head(&hw->wait_active); + hw->is_active =3D true; /* start in active mode for initialization */ + hw->polling_thread =3D kthread_run(mei_me_polling_thread, dev, + "kmegscirqd/%s", dev_name(device)); + if (IS_ERR(hw->polling_thread)) { + ret =3D PTR_ERR(hw->polling_thread); + dev_err(device, "unable to create kernel thread: %d\n", ret); + goto err; + } + } else { + ret =3D devm_request_threaded_irq(device, hw->irq, + mei_me_irq_quick_handler, + mei_me_irq_thread_handler, + IRQF_ONESHOT, KBUILD_MODNAME, dev); + if (ret) { + dev_err(device, "irq register failed %d\n", ret); + goto err; + } } =20 pm_runtime_get_noresume(device); @@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_de= v, =20 register_err: mei_stop(dev); - devm_free_irq(device, hw->irq, dev); + if (!mei_me_hw_use_polling(hw)) + devm_free_irq(device, hw->irq, dev); =20 err: dev_err(device, "probe failed: %d\n", ret); @@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device *a= ux_dev) =20 mei_stop(dev); =20 + hw =3D to_me_hw(dev); + if (mei_me_hw_use_polling(hw)) + kthread_stop(hw->polling_thread); + mei_deregister(dev); =20 pm_runtime_disable(&aux_dev->dev); =20 mei_disable_interrupts(dev); - devm_free_irq(&aux_dev->dev, hw->irq, dev); + if (!mei_me_hw_use_polling(hw)) + devm_free_irq(&aux_dev->dev, hw->irq, dev); } =20 static int __maybe_unused mei_gsc_pm_suspend(struct device *device) @@ -185,6 +207,9 @@ static int __maybe_unused mei_gsc_pm_runtime_suspend(s= truct device *device) if (mei_write_is_idle(dev)) { hw =3D to_me_hw(dev); hw->pg_state =3D MEI_PG_ON; + + if (mei_me_hw_use_polling(hw)) + hw->is_active =3D false; ret =3D 0; } else { ret =3D -EAGAIN; @@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(st= ruct device *device) hw =3D to_me_hw(dev); hw->pg_state =3D MEI_PG_OFF; =20 + if (mei_me_hw_use_polling(hw)) { + hw->is_active =3D true; + wake_up(&hw->wait_active); + } + mutex_unlock(&dev->device_lock); =20 irq_ret =3D mei_me_irq_thread_handler(1, dev); diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 3a95fe7d4e33..23ad53efbcb7 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include "mei_dev.h" #include "hbm.h" @@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev) */ static void mei_me_intr_enable(struct mei_device *dev) { - u32 hcsr =3D mei_hcsr_read(dev); + u32 hcsr; + + if (mei_me_hw_use_polling(to_me_hw(dev))) + return; =20 - hcsr |=3D H_CSR_IE_MASK; + hcsr =3D mei_hcsr_read(dev) | H_CSR_IE_MASK; mei_hcsr_set(dev, hcsr); } =20 @@ -354,6 +358,9 @@ static void mei_me_synchronize_irq(struct mei_device *d= ev) { struct mei_me_hw *hw =3D to_me_hw(dev); =20 + if (mei_me_hw_use_polling(hw)) + return; + synchronize_irq(hw->irq); } =20 @@ -380,7 +387,10 @@ static void mei_me_host_set_ready(struct mei_device *d= ev) { u32 hcsr =3D mei_hcsr_read(dev); =20 - hcsr |=3D H_CSR_IE_MASK | H_IG | H_RDY; + if (!mei_me_hw_use_polling(to_me_hw(dev))) + hcsr |=3D H_CSR_IE_MASK; + + hcsr |=3D H_IG | H_RDY; mei_hcsr_set(dev, hcsr); } =20 @@ -1176,7 +1186,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bo= ol intr_enable) =20 hcsr |=3D H_RST | H_IG | H_CSR_IS_MASK; =20 - if (!intr_enable) + if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev))) hcsr &=3D ~H_CSR_IE_MASK; =20 dev->recvd_hw_ready =3D false; @@ -1331,6 +1341,66 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void = *dev_id) } EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler); =20 +#define MEI_POLLING_TIMEOUT_ACTIVE 100 +#define MEI_POLLING_TIMEOUT_IDLE 500 + +/** + * mei_me_polling_thread - interrupt register polling thread + * + * The thread monitors the interrupt source register and calls + * mei_me_irq_thread_handler() to handle the firmware + * input. + * + * The function polls in MEI_POLLING_TIMEOUT_ACTIVE timeout + * in case there was an event, in idle case the polling + * time increases yet again by MEI_POLLING_TIMEOUT_ACTIVE + * up to MEI_POLLING_TIMEOUT_IDLE. + * + * @_dev: mei device + * + * Return: always 0 + */ +int mei_me_polling_thread(void *_dev) +{ + struct mei_device *dev =3D _dev; + irqreturn_t irq_ret; + long polling_timeout =3D MEI_POLLING_TIMEOUT_ACTIVE; + + dev_dbg(dev->dev, "kernel thread is running\n"); + while (!kthread_should_stop()) { + struct mei_me_hw *hw =3D to_me_hw(dev); + u32 hcsr; + + wait_event_timeout(hw->wait_active, + hw->is_active || kthread_should_stop(), + msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE)); + + if (kthread_should_stop()) + break; + + hcsr =3D mei_hcsr_read(dev); + if (me_intr_src(hcsr)) { + polling_timeout =3D MEI_POLLING_TIMEOUT_ACTIVE; + irq_ret =3D mei_me_irq_thread_handler(1, dev); + if (irq_ret !=3D IRQ_HANDLED) + dev_err(dev->dev, "irq_ret %d\n", irq_ret); + } else { + /* + * Increase timeout by MEI_POLLING_TIMEOUT_ACTIVE + * up to MEI_POLLING_TIMEOUT_IDLE + */ + polling_timeout =3D clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACT= IVE, + MEI_POLLING_TIMEOUT_ACTIVE, + MEI_POLLING_TIMEOUT_IDLE); + } + + schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout)); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mei_me_polling_thread); + static const struct mei_hw_ops mei_me_hw_ops =3D { =20 .trc_status =3D mei_me_trc_status, diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h index a071c645e905..6256b36bdafd 100644 --- a/drivers/misc/mei/hw-me.h +++ b/drivers/misc/mei/hw-me.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2012-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2012-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -51,6 +51,9 @@ struct mei_cfg { * @d0i3_supported: di03 support * @hbuf_depth: depth of hardware host/write buffer in slots * @read_fws: read FW status register handler + * @polling_thread: interrupt polling thread + * @wait_active: the polling thread activity wait queue + * @is_active: the device is active */ struct mei_me_hw { const struct mei_cfg *cfg; @@ -60,10 +63,19 @@ struct mei_me_hw { bool d0i3_supported; u8 hbuf_depth; int (*read_fws)(const struct mei_device *dev, int where, u32 *val); + /* polling */ + struct task_struct *polling_thread; + wait_queue_head_t wait_active; + bool is_active; }; =20 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) =20 +static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw) +{ + return hw->irq < 0; +} + /** * enum mei_cfg_idx - indices to platform specific configurations. * @@ -127,5 +139,6 @@ int mei_me_pg_exit_sync(struct mei_device *dev); =20 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); +int mei_me_polling_thread(void *_dev); =20 #endif /* _MEI_INTERFACE_H_ */ --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91DBFC38145 for ; Wed, 7 Sep 2022 16:00:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230086AbiIGQAE (ORCPT ); Wed, 7 Sep 2022 12:00:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229808AbiIGP7s (ORCPT ); Wed, 7 Sep 2022 11:59:48 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6968611C3B for ; Wed, 7 Sep 2022 08:59:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566374; x=1694102374; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2LoTcrDdIIjhQQzEoUzp6PWW1yQHSMcHmGudjZ75118=; b=MQLn8MyVXk+5ejEzOhi3Ygng3PdjtiLn1f9FG4KDuTaMlwdu0NICSfdA dgd1Z7FL64hUh1KppAy5Q0VosFyAG2M2EVEDS1+IVyeJf0ZW0bcsKt4iz wO+qlmrHBO7YjysqLtAcsE9g4oGhpZo2HnFSMgzw/VjeJrU6jaoQz9H8Z OwG3Wuj3NqhEGsfw/hKcYjotDw05TcwN4JdaM9GnZ8Hv7ZUyPhrt6jKTY J9lvfGKLf91/sXLldWQwB5aa3lHpUfyxRFl+0IZwEhdXInBy520Kh+RBX H+6eWKxx6iL+FV9o4QP3kgjbTgPzVILWEfccUElY9sAqo7k/J/RO39MG8 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701322" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701322" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:11 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676247865" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:07 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart Subject: [PATCH v8 07/16] mei: gsc: wait for reset thread on stop Date: Wed, 7 Sep 2022 18:58:04 +0300 Message-Id: <20220907155813.1427526-8-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Wait for reset work to complete before initiating stop reset flow sequence. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/init.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c index eb052005ca86..bc054baf496c 100644 --- a/drivers/misc/mei/init.c +++ b/drivers/misc/mei/init.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2012-2019, Intel Corporation. All rights reserved. + * Copyright (c) 2012-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev) =20 mei_clear_interrupts(dev); mei_synchronize_irq(dev); + /* to catch HW-initiated reset */ + mei_cancel_work(dev); =20 mutex_lock(&dev->device_lock); =20 --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89552C6FA86 for ; Wed, 7 Sep 2022 16:00:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230132AbiIGQAL (ORCPT ); Wed, 7 Sep 2022 12:00:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230118AbiIGP7z (ORCPT ); Wed, 7 Sep 2022 11:59:55 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B78325E2 for ; Wed, 7 Sep 2022 08:59:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566379; x=1694102379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VKtVLhXkizlByvN7J6rFcR8hs+obHJZEOeNPCBCLfkw=; b=CrQGX4G42y0yPefXF95EPb9VurDLeHJZyhLcC/Ztl6tMqV0DnYDzTmsY cvAisME174MaCIKF0XTYLmFhWC/PtX0I5rhZxwjpUccf488qrJSLYqg3V hAKugjDAzpq1YXhO80dzCkhJAlqMIx90m5gp1FGmeDQt0BAKim+sIqfaX hSG0If5hPpDkYyCQa+S9MJhyrLMlZi5+r7wGSLmtQKoi/44boa5+W7nGu E6oTQvmytGS7d2nbS7/b+2RPwccc8Vp4LxWkE2N6IqRjng3+SBGjn0cVt K4zwNzSSmI9vJLKAYNnaZ8sjLEDNasby55+MKtCzRM36BnMtcfgefHzQO Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701398" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701398" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:16 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676247927" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:11 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart Subject: [PATCH v8 08/16] mei: extend timeouts on slow devices. Date: Wed, 7 Sep 2022 18:58:05 +0300 Message-Id: <20220907155813.1427526-9-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Parametrize operational timeouts in order to support slow firmware on some graphics devices. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/bus-fixup.c | 5 ++--- drivers/misc/mei/client.c | 16 ++++++++-------- drivers/misc/mei/gsc-me.c | 2 +- drivers/misc/mei/hbm.c | 14 +++++++------- drivers/misc/mei/hw-me.c | 30 ++++++++++++++++-------------- drivers/misc/mei/hw-me.h | 2 +- drivers/misc/mei/hw-txe.c | 4 ++-- drivers/misc/mei/hw.h | 7 ++++++- drivers/misc/mei/init.c | 19 ++++++++++++++++++- drivers/misc/mei/main.c | 4 ++-- drivers/misc/mei/mei_dev.h | 18 +++++++++++++++++- drivers/misc/mei/pci-me.c | 4 ++-- 12 files changed, 82 insertions(+), 43 deletions(-) diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 59506ba6fc48..344598fcf8e9 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2013-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2013-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev) sizeof(struct mkhi_fw_ver)) #define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \ sizeof(struct mkhi_fw_ver_block) * (__num)) -#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */ static int mei_fwver(struct mei_cl_device *cldev) { char buf[MKHI_FWVER_BUF_LEN]; @@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev) =20 ret =3D 0; bytes_recv =3D __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0, - MKHI_RCV_TIMEOUT); + cldev->bus->timeouts.mkhi_recv); if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) { /* * Should be at least one version block, diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c index 31264ab2eb13..0b2fbe1335a7 100644 --- a/drivers/misc/mei/client.c +++ b/drivers/misc/mei/client.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, st= ruct mei_cl_cb *cb) } =20 list_move_tail(&cb->list, &dev->ctrl_rd_list); - cl->timer_count =3D MEI_CONNECT_TIMEOUT; + cl->timer_count =3D dev->timeouts.connect; mei_schedule_stall_timer(dev); =20 return 0; @@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl) wait_event_timeout(cl->wait, cl->state =3D=3D MEI_FILE_DISCONNECT_REPLY || cl->state =3D=3D MEI_FILE_DISCONNECTED, - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 rets =3D cl->status; @@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, str= uct mei_cl_cb *cb) } =20 list_move_tail(&cb->list, &dev->ctrl_rd_list); - cl->timer_count =3D MEI_CONNECT_TIMEOUT; + cl->timer_count =3D dev->timeouts.connect; mei_schedule_stall_timer(dev); return 0; } @@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct mei_me_c= lient *me_cl, cl->state =3D=3D MEI_FILE_DISCONNECTED || cl->state =3D=3D MEI_FILE_DISCONNECT_REQUIRED || cl->state =3D=3D MEI_FILE_DISCONNECT_REPLY), - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 if (!mei_cl_is_connected(cl)) { @@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl, cl->notify_en =3D=3D request || cl->status || !mei_cl_is_connected(cl), - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 if (cl->notify_en !=3D request && !cl->status) @@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const= struct file *fp, mutex_unlock(&dev->device_lock); wait_event_timeout(cl->wait, cl->dma_mapped || cl->status, - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 if (!cl->dma_mapped && !cl->status) @@ -2415,7 +2415,7 @@ int mei_cl_dma_unmap(struct mei_cl *cl, const struct = file *fp) mutex_unlock(&dev->device_lock); wait_event_timeout(cl->wait, !cl->dma_mapped || cl->status, - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); =20 if (cl->dma_mapped && !cl->status) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 2caba3a9ac35..bfa6154b93e2 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -48,7 +48,7 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev, =20 device =3D &aux_dev->dev; =20 - dev =3D mei_me_dev_init(device, cfg); + dev =3D mei_me_dev_init(device, cfg, adev->slow_firmware); if (!dev) { ret =3D -ENOMEM; goto err; diff --git a/drivers/misc/mei/hbm.c b/drivers/misc/mei/hbm.c index cf2b8261da14..de712cbf5d07 100644 --- a/drivers/misc/mei/hbm.c +++ b/drivers/misc/mei/hbm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ #include @@ -232,7 +232,7 @@ int mei_hbm_start_wait(struct mei_device *dev) mutex_unlock(&dev->device_lock); ret =3D wait_event_timeout(dev->wait_hbm_start, dev->hbm_state !=3D MEI_HBM_STARTING, - mei_secs_to_jiffies(MEI_HBM_TIMEOUT)); + dev->timeouts.hbm); mutex_lock(&dev->device_lock); =20 if (ret =3D=3D 0 && (dev->hbm_state <=3D MEI_HBM_STARTING)) { @@ -275,7 +275,7 @@ int mei_hbm_start_req(struct mei_device *dev) } =20 dev->hbm_state =3D MEI_HBM_STARTING; - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); return 0; } @@ -316,7 +316,7 @@ static int mei_hbm_dma_setup_req(struct mei_device *dev) } =20 dev->hbm_state =3D MEI_HBM_DR_SETUP; - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); return 0; } @@ -351,7 +351,7 @@ static int mei_hbm_capabilities_req(struct mei_device *= dev) } =20 dev->hbm_state =3D MEI_HBM_CAP_SETUP; - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); return 0; } @@ -385,7 +385,7 @@ static int mei_hbm_enum_clients_req(struct mei_device *= dev) return ret; } dev->hbm_state =3D MEI_HBM_ENUM_CLIENTS; - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); return 0; } @@ -751,7 +751,7 @@ static int mei_hbm_prop_req(struct mei_device *dev, uns= igned long start_idx) return ret; } =20 - dev->init_clients_timer =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->init_clients_timer =3D dev->timeouts.client_init; mei_schedule_stall_timer(dev); =20 return 0; diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 23ad53efbcb7..3c41b61ccbe8 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -445,7 +445,7 @@ static int mei_me_hw_ready_wait(struct mei_device *dev) mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, - mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); + dev->timeouts.hw_ready); mutex_lock(&dev->device_lock); if (!dev->recvd_hw_ready) { dev_err(dev->dev, "wait hw ready failed\n"); @@ -707,7 +707,6 @@ static void mei_me_pg_unset(struct mei_device *dev) static int mei_me_pg_legacy_enter_sync(struct mei_device *dev) { struct mei_me_hw *hw =3D to_me_hw(dev); - unsigned long timeout =3D mei_secs_to_jiffies(MEI_PGI_TIMEOUT); int ret; =20 dev->pg_event =3D MEI_PG_EVENT_WAIT; @@ -718,7 +717,8 @@ static int mei_me_pg_legacy_enter_sync(struct mei_devic= e *dev) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 if (dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED) { @@ -744,7 +744,6 @@ static int mei_me_pg_legacy_enter_sync(struct mei_devic= e *dev) static int mei_me_pg_legacy_exit_sync(struct mei_device *dev) { struct mei_me_hw *hw =3D to_me_hw(dev); - unsigned long timeout =3D mei_secs_to_jiffies(MEI_PGI_TIMEOUT); int ret; =20 if (dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED) @@ -756,7 +755,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device= *dev) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 reply: @@ -772,7 +772,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device= *dev) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 if (dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED) @@ -887,8 +888,6 @@ static u32 mei_me_d0i3_unset(struct mei_device *dev) static int mei_me_d0i3_enter_sync(struct mei_device *dev) { struct mei_me_hw *hw =3D to_me_hw(dev); - unsigned long d0i3_timeout =3D mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); - unsigned long pgi_timeout =3D mei_secs_to_jiffies(MEI_PGI_TIMEOUT); int ret; u32 reg; =20 @@ -910,7 +909,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *de= v) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, pgi_timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_RECEIVED, + dev->timeouts.d0i3); mutex_lock(&dev->device_lock); =20 if (dev->pg_event !=3D MEI_PG_EVENT_RECEIVED) { @@ -930,7 +930,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *de= v) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, + dev->timeouts.d0i3); mutex_lock(&dev->device_lock); =20 if (dev->pg_event !=3D MEI_PG_EVENT_INTR_RECEIVED) { @@ -990,7 +991,6 @@ static int mei_me_d0i3_enter(struct mei_device *dev) static int mei_me_d0i3_exit_sync(struct mei_device *dev) { struct mei_me_hw *hw =3D to_me_hw(dev); - unsigned long timeout =3D mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); int ret; u32 reg; =20 @@ -1013,7 +1013,8 @@ static int mei_me_d0i3_exit_sync(struct mei_device *d= ev) =20 mutex_unlock(&dev->device_lock); wait_event_timeout(dev->wait_pg, - dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, timeout); + dev->pg_event =3D=3D MEI_PG_EVENT_INTR_RECEIVED, + dev->timeouts.pgi); mutex_lock(&dev->device_lock); =20 if (dev->pg_event !=3D MEI_PG_EVENT_INTR_RECEIVED) { @@ -1706,11 +1707,12 @@ EXPORT_SYMBOL_GPL(mei_me_get_cfg); * * @parent: device associated with physical device (pci/platform) * @cfg: per device generation config + * @slow_fw: configure longer timeouts as FW is slow * * Return: The mei_device pointer on success, NULL on failure. */ struct mei_device *mei_me_dev_init(struct device *parent, - const struct mei_cfg *cfg) + const struct mei_cfg *cfg, bool slow_fw) { struct mei_device *dev; struct mei_me_hw *hw; @@ -1725,7 +1727,7 @@ struct mei_device *mei_me_dev_init(struct device *par= ent, for (i =3D 0; i < DMA_DSCR_NUM; i++) dev->dr_dscr[i].size =3D cfg->dma_size[i]; =20 - mei_device_init(dev, parent, &mei_me_hw_ops); + mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops); hw->cfg =3D cfg; =20 dev->fw_f_fw_ver_supported =3D cfg->fw_ver_supported; diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h index 6256b36bdafd..95cf830b7c7b 100644 --- a/drivers/misc/mei/hw-me.h +++ b/drivers/misc/mei/hw-me.h @@ -132,7 +132,7 @@ enum mei_cfg_idx { const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx); =20 struct mei_device *mei_me_dev_init(struct device *parent, - const struct mei_cfg *cfg); + const struct mei_cfg *cfg, bool slow_fw); =20 int mei_me_pg_enter_sync(struct mei_device *dev); int mei_me_pg_exit_sync(struct mei_device *dev); diff --git a/drivers/misc/mei/hw-txe.c b/drivers/misc/mei/hw-txe.c index 00652c137cc7..9862c6cd3e32 100644 --- a/drivers/misc/mei/hw-txe.c +++ b/drivers/misc/mei/hw-txe.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2013-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2013-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -1201,7 +1201,7 @@ struct mei_device *mei_txe_dev_init(struct pci_dev *p= dev) if (!dev) return NULL; =20 - mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); + mei_device_init(dev, &pdev->dev, false, &mei_txe_hw_ops); =20 hw =3D to_txe_hw(dev); =20 diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h index b46077b17114..e7e020dba6b1 100644 --- a/drivers/misc/mei/hw.h +++ b/drivers/misc/mei/hw.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -16,11 +16,16 @@ #define MEI_CONNECT_TIMEOUT 3 /* HPS: at least 2 seconds */ =20 #define MEI_CL_CONNECT_TIMEOUT 15 /* HPS: Client Connect Timeout */ +#define MEI_CL_CONNECT_TIMEOUT_SLOW 30 /* HPS: Client Connect Timeout, slo= w FW */ #define MEI_CLIENTS_INIT_TIMEOUT 15 /* HPS: Clients Enumeration Timeout= */ =20 #define MEI_PGI_TIMEOUT 1 /* PG Isolation time response 1 sec= */ #define MEI_D0I3_TIMEOUT 5 /* D0i3 set/unset max response time= */ #define MEI_HBM_TIMEOUT 1 /* 1 second */ +#define MEI_HBM_TIMEOUT_SLOW 5 /* 5 second, slow FW */ + +#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */ +#define MKHI_RCV_TIMEOUT_SLOW 10000 /* receive timeout in msec, slow FW */ =20 /* * FW page size for DMA allocations diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c index bc054baf496c..5473b1fa6fff 100644 --- a/drivers/misc/mei/init.c +++ b/drivers/misc/mei/init.c @@ -359,14 +359,16 @@ bool mei_write_is_idle(struct mei_device *dev) EXPORT_SYMBOL_GPL(mei_write_is_idle); =20 /** - * mei_device_init -- initialize mei_device structure + * mei_device_init - initialize mei_device structure * * @dev: the mei device * @device: the device structure + * @slow_fw: configure longer timeouts as FW is slow * @hw_ops: hw operations */ void mei_device_init(struct mei_device *dev, struct device *device, + bool slow_fw, const struct mei_hw_ops *hw_ops) { /* setup our list array */ @@ -404,6 +406,21 @@ void mei_device_init(struct mei_device *dev, dev->pg_event =3D MEI_PG_EVENT_IDLE; dev->ops =3D hw_ops; dev->dev =3D device; + + dev->timeouts.hw_ready =3D mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT); + dev->timeouts.connect =3D MEI_CONNECT_TIMEOUT; + dev->timeouts.client_init =3D MEI_CLIENTS_INIT_TIMEOUT; + dev->timeouts.pgi =3D mei_secs_to_jiffies(MEI_PGI_TIMEOUT); + dev->timeouts.d0i3 =3D mei_secs_to_jiffies(MEI_D0I3_TIMEOUT); + if (slow_fw) { + dev->timeouts.cl_connect =3D mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT_= SLOW); + dev->timeouts.hbm =3D mei_secs_to_jiffies(MEI_HBM_TIMEOUT_SLOW); + dev->timeouts.mkhi_recv =3D msecs_to_jiffies(MKHI_RCV_TIMEOUT_SLOW); + } else { + dev->timeouts.cl_connect =3D mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT); + dev->timeouts.hbm =3D mei_secs_to_jiffies(MEI_HBM_TIMEOUT); + dev->timeouts.mkhi_recv =3D msecs_to_jiffies(MKHI_RCV_TIMEOUT); + } } EXPORT_SYMBOL_GPL(mei_device_init); =20 diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c index 786f7c8f7f61..930887e7e38d 100644 --- a/drivers/misc/mei/main.c +++ b/drivers/misc/mei/main.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -571,7 +571,7 @@ static int mei_ioctl_connect_vtag(struct file *file, cl->state =3D=3D MEI_FILE_DISCONNECTED || cl->state =3D=3D MEI_FILE_DISCONNECT_REQUIRED || cl->state =3D=3D MEI_FILE_DISCONNECT_REPLY), - mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT)); + dev->timeouts.cl_connect); mutex_lock(&dev->device_lock); } =20 diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h index 694f866f87ef..babbb0944b7f 100644 --- a/drivers/misc/mei/mei_dev.h +++ b/drivers/misc/mei/mei_dev.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2003-2019, Intel Corporation. All rights reserved. + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -415,6 +415,17 @@ struct mei_fw_version { =20 #define MEI_MAX_FW_VER_BLOCKS 3 =20 +struct mei_dev_timeouts { + unsigned long hw_ready; /* Timeout on ready message, in jiffies */ + int connect; /* HPS: at least 2 seconds, in seconds */ + unsigned long cl_connect; /* HPS: Client Connect Timeout, in jiffies */ + int client_init; /* HPS: Clients Enumeration Timeout, in seconds */ + unsigned long pgi; /* PG Isolation time response, in jiffies */ + unsigned int d0i3; /* D0i3 set/unset max response time, in jiffies */ + unsigned long hbm; /* HBM operation timeout, in jiffies */ + unsigned long mkhi_recv; /* receive timeout, in jiffies */ +}; + /** * struct mei_device - MEI private device struct * @@ -480,6 +491,8 @@ struct mei_fw_version { * @allow_fixed_address: allow user space to connect a fixed client * @override_fixed_address: force allow fixed address behavior * + * @timeouts: actual timeout values + * * @reset_work : work item for the device reset * @bus_rescan_work : work item for the bus rescan * @@ -568,6 +581,8 @@ struct mei_device { bool allow_fixed_address; bool override_fixed_address; =20 + struct mei_dev_timeouts timeouts; + struct work_struct reset_work; struct work_struct bus_rescan_work; =20 @@ -632,6 +647,7 @@ static inline u32 mei_slots2data(int slots) */ void mei_device_init(struct mei_device *dev, struct device *device, + bool slow_fw, const struct mei_hw_ops *hw_ops); int mei_reset(struct mei_device *dev); int mei_start(struct mei_device *dev); diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c index 5435604327a7..704cd0caa172 100644 --- a/drivers/misc/mei/pci-me.c +++ b/drivers/misc/mei/pci-me.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved. + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -203,7 +203,7 @@ static int mei_me_probe(struct pci_dev *pdev, const str= uct pci_device_id *ent) } =20 /* allocates and initializes the mei dev structure */ - dev =3D mei_me_dev_init(&pdev->dev, cfg); + dev =3D mei_me_dev_init(&pdev->dev, cfg, false); if (!dev) { err =3D -ENOMEM; goto end; --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C218DC6FA86 for ; Wed, 7 Sep 2022 16:00:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230186AbiIGQA2 (ORCPT ); Wed, 7 Sep 2022 12:00:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230179AbiIGQAB (ORCPT ); Wed, 7 Sep 2022 12:00:01 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52C6C33407 for ; Wed, 7 Sep 2022 08:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566383; x=1694102383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7LPD4nhApM8sqGjNR6JnkE4Y4ACFhfMxX7DGMWYyNmI=; b=ldFqP8M77lqH9J826/7yRSwSoR93Sv82yL1uXBj8RWasSLmodoGQ8pe9 MplXn2ySkcAkaYUE7uStY/YOxeByZNOF8NWGNiFh9GiHfG8n1CW28VaCD J2k89RRAoiXWHDFZTaEXPVOcWTO5+uKeasYkdO/M5a5VJ2mugKwF2h4qE QdkhnQSw1MjoURt14eIfW4gL3uFWcJDW0yQcPnCaHnzDm7pRyKu8yv4eb NYZrXEkGfSYNJF4LmtwyZH2/cy2P0H2qI88mIDWPjdrltLOWzBASkZCas ovEjZrTe49zx2O6EJltaAuSddNAHaHKWmvoKNODSMtLCVRPMe3oYL+PQ0 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701421" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701421" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:18 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676248010" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:15 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart Subject: [PATCH v8 09/16] mei: bus: export common mkhi definitions into a separate header Date: Wed, 7 Sep 2022 18:58:06 +0300 Message-Id: <20220907155813.1427526-10-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vitaly Lubart Exported common mkhi definitions from bus-fixup.c into a separate header file mkhi.h for other driver usage. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/bus-fixup.c | 31 +------------------- drivers/misc/mei/mkhi.h | 57 ++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 30 deletions(-) create mode 100644 drivers/misc/mei/mkhi.h diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 344598fcf8e9..c4e527803299 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -15,6 +15,7 @@ =20 #include "mei_dev.h" #include "client.h" +#include "mkhi.h" =20 #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \ 0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06) @@ -89,20 +90,6 @@ struct mei_os_ver { u8 reserved2; } __packed; =20 -#define MKHI_FEATURE_PTT 0x10 - -struct mkhi_rule_id { - __le16 rule_type; - u8 feature_id; - u8 reserved; -} __packed; - -struct mkhi_fwcaps { - struct mkhi_rule_id id; - u8 len; - u8 data[]; -} __packed; - struct mkhi_fw_ver_block { u16 minor; u8 major; @@ -115,22 +102,6 @@ struct mkhi_fw_ver { struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS]; } __packed; =20 -#define MKHI_FWCAPS_GROUP_ID 0x3 -#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 -#define MKHI_GEN_GROUP_ID 0xFF -#define MKHI_GEN_GET_FW_VERSION_CMD 0x2 -struct mkhi_msg_hdr { - u8 group_id; - u8 command; - u8 reserved; - u8 result; -} __packed; - -struct mkhi_msg { - struct mkhi_msg_hdr hdr; - u8 data[]; -} __packed; - #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \ sizeof(struct mkhi_fwcaps) + \ sizeof(struct mei_os_ver)) diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h new file mode 100644 index 000000000000..43cadfb1b990 --- /dev/null +++ b/drivers/misc/mei/mkhi.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. + * Intel Management Engine Interface (Intel MEI) Linux driver + */ + +#ifndef _MEI_MKHI_H_ +#define _MEI_MKHI_H_ + +#include + +#define MKHI_FEATURE_PTT 0x10 + +#define MKHI_FWCAPS_GROUP_ID 0x3 +#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 +#define MKHI_GEN_GROUP_ID 0xFF +#define MKHI_GEN_GET_FW_VERSION_CMD 0x2 + +#define MKHI_GROUP_ID_GFX 0x30 +#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0 +#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1 + +/* Allow transition to PXP mode without approval */ +#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1 + +#define MKHI_GROUP_ID_GFX 0x30 +#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0 +#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1 + +/* Allow transition to PXP mode without approval */ +#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1 + +struct mkhi_rule_id { + __le16 rule_type; + u8 feature_id; + u8 reserved; +} __packed; + +struct mkhi_fwcaps { + struct mkhi_rule_id id; + u8 len; + u8 data[]; +} __packed; + +struct mkhi_msg_hdr { + u8 group_id; + u8 command; + u8 reserved; + u8 result; +} __packed; + +struct mkhi_msg { + struct mkhi_msg_hdr hdr; + u8 data[]; +} __packed; + +#endif /* _MEI_MKHI_H_ */ --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DBF5C54EE9 for ; Wed, 7 Sep 2022 16:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230213AbiIGQAp (ORCPT ); Wed, 7 Sep 2022 12:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230146AbiIGQAM (ORCPT ); Wed, 7 Sep 2022 12:00:12 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 577B3248DD for ; Wed, 7 Sep 2022 08:59:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566386; x=1694102386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k8WXuqM2Btnztwxu+hZDAOvoXEutBVbE7ajm9wvLA1E=; b=jWAMiCFJm9y7W/Hrm40wosgZ+Xvbf+LhqpCFTUejjPSo36kOj5lrGudr nMOH9eu2pOeYjoAk6aBezhs+erYRNxVRLaisiB+4DD/2Q/isfDK2M1/ac x894zuhAPKU3z6MmWxRVFgh7l1PmePrYakdsCvCLED2Zvhn1Orsq8a6m+ tqmhJ0RtLiKER4EnYlSQRgXYSiEpJIUF0Wr41xcWFzkguvjcWkjs9qWSa zetOob5YFxzduS1jBWpS15SbqqguRsFtMV+dSenR0mqLnZIkoNkJIdv4n tJz1U8lB1FV3mJK0oRANpjsqJRzPR5TJG660YNCBepK4TvK9EvG+p9sMi Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701444" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701444" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:22 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676248078" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:18 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Daniele Ceraolo Spurio Subject: [PATCH v8 10/16] mei: mkhi: add memory ready command Date: Wed, 7 Sep 2022 18:58:07 +0300 Message-Id: <20220907155813.1427526-11-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add GSC memory ready command. The command indicates to the firmware that extend operation memory was setup and the firmware may enter PXP mode. CC: Daniele Ceraolo Spurio Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/mkhi.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h index 43cadfb1b990..c9d0b2b9dfa0 100644 --- a/drivers/misc/mei/mkhi.h +++ b/drivers/misc/mei/mkhi.h @@ -30,6 +30,13 @@ /* Allow transition to PXP mode without approval */ #define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1 =20 +#define MKHI_GROUP_ID_GFX 0x30 +#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0 +#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1 + +/* Allow transition to PXP mode without approval */ +#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1 + struct mkhi_rule_id { __le16 rule_type; u8 feature_id; @@ -54,4 +61,9 @@ struct mkhi_msg { u8 data[]; } __packed; =20 +struct mkhi_gfx_mem_ready { + struct mkhi_msg_hdr hdr; + u32 flags; +} __packed; + #endif /* _MEI_MKHI_H_ */ --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD029C54EE9 for ; Wed, 7 Sep 2022 16:00:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230233AbiIGQAh (ORCPT ); Wed, 7 Sep 2022 12:00:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230205AbiIGQAE (ORCPT ); Wed, 7 Sep 2022 12:00:04 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4598252092 for ; Wed, 7 Sep 2022 08:59:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566389; x=1694102389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=akALbdp1bBC8erj1kUpBaA6ehDkMX5BY+p3XKMqXJ9k=; b=UIpqcaIvAQNmEstwntqZHn4yPaqOZYIJmwPIr9nQNo1Pm2fkTCpR1eEy /HDajONhhGZrBn1ud4mksRUNixao18A6TqPBsigmSm+BWDSmCtuRzTqPp s4ZUDF9U4jHI3gsWCPbAOjr1lzPUTI49yu3K/dogoMhUcVEq6YuNqUpX2 HiTEm+M+5KkkMYOZ6Mng/0NLaZWM9CaD8Im73ls0xOkE2LcS483oLNr3x eOcByO8wTqE1UNUzQH9pPd1X3sU99KFrmq3VPjnfnQqUtL4BEwFlnwMi9 KkS46G9Ze//PxGl9W+xAN9t5vSU6yNJzvVjcFeS+y8ZAuWJpa3wMACcvn w==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701474" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701474" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:26 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676248143" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:22 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Daniele Ceraolo Spurio Subject: [PATCH v8 11/16] mei: gsc: setup gsc extended operational memory Date: Wed, 7 Sep 2022 18:58:08 +0300 Message-Id: <20220907155813.1427526-12-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" 1. Retrieve extended operational memory physical pointers from the auxiliary device info. 2. Setup memory registers. 3. Notify firmware that the memory is ready by sending the memory ready command. 4. Disable PXP device if GSC is not in PXP mode. CC: Daniele Ceraolo Spurio Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/bus-fixup.c | 70 ++++++++++++++++++++++++++++++++++- drivers/misc/mei/gsc-me.c | 16 ++++++++ drivers/misc/mei/hw-me-regs.h | 9 ++++- drivers/misc/mei/hw-me.c | 28 +++++++++++++- drivers/misc/mei/init.c | 2 + drivers/misc/mei/mei_dev.h | 17 +++++++++ include/linux/mei_aux.h | 3 ++ 7 files changed, 141 insertions(+), 4 deletions(-) diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index c4e527803299..79305e4acce2 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -188,6 +188,19 @@ static int mei_fwver(struct mei_cl_device *cldev) return ret; } =20 +static int mei_gfx_memory_ready(struct mei_cl_device *cldev) +{ + struct mkhi_gfx_mem_ready req =3D {0}; + unsigned int mode =3D MEI_CL_IO_TX_INTERNAL; + + req.hdr.group_id =3D MKHI_GROUP_ID_GFX; + req.hdr.command =3D MKHI_GFX_MEMORY_READY_CMD_REQ; + req.flags =3D MKHI_GFX_MEM_READY_PXP_ALLOWED; + + dev_dbg(&cldev->dev, "Sending memory ready command\n"); + return __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, mode); +} + static void mei_mkhi_fix(struct mei_cl_device *cldev) { int ret; @@ -234,6 +247,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cld= ev) dev_err(&cldev->dev, "FW version command failed %d\n", ret); mei_cldev_disable(cldev); } + +static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev) +{ + int ret; + + /* No need to enable the client if nothing is needed from it */ + if (!cldev->bus->fw_f_fw_ver_supported && + cldev->bus->pxp_mode !=3D MEI_DEV_PXP_INIT) + return; + + ret =3D mei_cldev_enable(cldev); + if (ret) + return; + + if (cldev->bus->pxp_mode =3D=3D MEI_DEV_PXP_INIT) { + ret =3D mei_gfx_memory_ready(cldev); + if (ret < 0) + dev_err(&cldev->dev, "memory ready command failed %d\n", ret); + else + dev_dbg(&cldev->dev, "memory ready command sent\n"); + /* we go to reset after that */ + cldev->bus->pxp_mode =3D MEI_DEV_PXP_SETUP; + goto out; + } + + ret =3D mei_fwver(cldev); + if (ret < 0) + dev_err(&cldev->dev, "FW version command failed %d\n", + ret); +out: + mei_cldev_disable(cldev); +} + /** * mei_wd - wd client on the bus, change protocol version * as the API has changed. @@ -473,6 +519,26 @@ static void vt_support(struct mei_cl_device *cldev) cldev->do_match =3D 1; } =20 +/** + * pxp_is_ready - enable bus client if pxp is ready + * + * @cldev: me clients device + */ +static void pxp_is_ready(struct mei_cl_device *cldev) +{ + struct mei_device *bus =3D cldev->bus; + + switch (bus->pxp_mode) { + case MEI_DEV_PXP_READY: + case MEI_DEV_PXP_DEFAULT: + cldev->do_match =3D 1; + break; + default: + cldev->do_match =3D 0; + break; + } +} + #define MEI_FIXUP(_uuid, _hook) { _uuid, _hook } =20 static struct mei_fixup { @@ -486,10 +552,10 @@ static struct mei_fixup { MEI_FIXUP(MEI_UUID_WD, mei_wd), MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix), MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver), - MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver), + MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver), MEI_FIXUP(MEI_UUID_HDCP, whitelist), MEI_FIXUP(MEI_UUID_ANY, vt_support), - MEI_FIXUP(MEI_UUID_PAVP, whitelist), + MEI_FIXUP(MEI_UUID_PAVP, pxp_is_ready), }; =20 /** diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index bfa6154b93e2..6b22726aed55 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev= , int where, u32 *val) return 0; } =20 +static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct reso= urce *mem) +{ + u32 low =3D lower_32_bits(mem->start); + u32 hi =3D upper_32_bits(mem->start); + u32 limit =3D (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID; + + iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG); + iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG); + iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG); +} + static int mei_gsc_probe(struct auxiliary_device *aux_dev, const struct auxiliary_device_id *aux_dev_id) { @@ -67,6 +78,11 @@ static int mei_gsc_probe(struct auxiliary_device *aux_de= v, =20 dev_set_drvdata(device, dev); =20 + if (adev->ext_op_mem.start) { + mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem); + dev->pxp_mode =3D MEI_DEV_PXP_INIT; + } + /* use polling */ if (mei_me_hw_use_polling(hw)) { mei_disable_interrupts(dev); diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h index 15e8e2b322b1..99966cd3e7d8 100644 --- a/drivers/misc/mei/hw-me-regs.h +++ b/drivers/misc/mei/hw-me-regs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* - * Copyright (c) 2003-2019, Intel Corporation. All rights reserved. + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ #ifndef _MEI_HW_MEI_REGS_H_ @@ -127,6 +127,8 @@ # define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060 #define PCI_CFG_HFS_4 0x64 #define PCI_CFG_HFS_5 0x68 +# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003 +# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3 #define PCI_CFG_HFS_6 0x6C =20 /* MEI registers */ @@ -143,6 +145,11 @@ /* H_D0I3C - D0I3 Control */ #define H_D0I3C 0x800 =20 +#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100 +#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104 +#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108 +#define GSC_EXT_OP_MEM_VALID BIT(31) + /* register bits of H_CSR (Host Control Status register) */ /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */ #define H_CBD 0xFF000000 diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c index 3c41b61ccbe8..a5bcc475c0e9 100644 --- a/drivers/misc/mei/hw-me.c +++ b/drivers/misc/mei/hw-me.c @@ -433,6 +433,29 @@ static bool mei_me_hw_is_resetting(struct mei_device *= dev) return (mecsr & ME_RST_HRA) =3D=3D ME_RST_HRA; } =20 +/** + * mei_gsc_pxp_check - check for gsc firmware entering pxp mode + * + * @dev: the device structure + */ +static void mei_gsc_pxp_check(struct mei_device *dev) +{ + struct mei_me_hw *hw =3D to_me_hw(dev); + u32 fwsts5 =3D 0; + + if (dev->pxp_mode =3D=3D MEI_DEV_PXP_DEFAULT) + return; + + hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5); + trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5); + if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) =3D=3D GSC_CFG_HFS_5_BOOT_TYPE= _PXP) { + dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5); + dev->pxp_mode =3D MEI_DEV_PXP_READY; + } else { + dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5); + } +} + /** * mei_me_hw_ready_wait - wait until the me(hw) has turned ready * or timeout is reached @@ -452,6 +475,8 @@ static int mei_me_hw_ready_wait(struct mei_device *dev) return -ETIME; } =20 + mei_gsc_pxp_check(dev); + mei_me_hw_reset_release(dev); dev->recvd_hw_ready =3D false; return 0; @@ -1270,7 +1295,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *= dev_id) =20 /* check if ME wants a reset */ if (!mei_hw_is_ready(dev) && dev->dev_state !=3D MEI_DEV_RESETTING) { - dev_warn(dev->dev, "FW not ready: resetting.\n"); + dev_warn(dev->dev, "FW not ready: resetting: dev_state =3D %d pxp =3D %d= \n", + dev->dev_state, dev->pxp_mode); if (dev->dev_state =3D=3D MEI_DEV_POWERING_DOWN || dev->dev_state =3D=3D MEI_DEV_POWER_DOWN) mei_cl_all_disconnect(dev); diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c index 5473b1fa6fff..1b4d5d7870b9 100644 --- a/drivers/misc/mei/init.c +++ b/drivers/misc/mei/init.c @@ -397,6 +397,8 @@ void mei_device_init(struct mei_device *dev, bitmap_zero(dev->host_clients_map, MEI_CLIENTS_MAX); dev->open_handle_count =3D 0; =20 + dev->pxp_mode =3D MEI_DEV_PXP_DEFAULT; + /* * Reserving the first client ID * 0: Reserved for MEI Bus Message communications diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h index babbb0944b7f..6bb3e1ba9ded 100644 --- a/drivers/misc/mei/mei_dev.h +++ b/drivers/misc/mei/mei_dev.h @@ -62,6 +62,21 @@ enum mei_dev_state { MEI_DEV_POWER_UP }; =20 +/** + * enum mei_dev_pxp_mode - MEI PXP mode state + * + * @MEI_DEV_PXP_DEFAULT: PCH based device, no initailization required + * @MEI_DEV_PXP_INIT: device requires initialization, send setup messag= e to firmware + * @MEI_DEV_PXP_SETUP: device is in setup stage, waiting for firmware re= psonse + * @MEI_DEV_PXP_READY: device initialized + */ +enum mei_dev_pxp_mode { + MEI_DEV_PXP_DEFAULT =3D 0, + MEI_DEV_PXP_INIT =3D 1, + MEI_DEV_PXP_SETUP =3D 2, + MEI_DEV_PXP_READY =3D 3, +}; + const char *mei_dev_state_str(int state); =20 enum mei_file_transaction_states { @@ -454,6 +469,7 @@ struct mei_dev_timeouts { * @reset_count : number of consecutive resets * @dev_state : device state * @hbm_state : state of host bus message protocol + * @pxp_mode : PXP device mode * @init_clients_timer : HBM init handshake timeout * * @pg_event : power gating event @@ -537,6 +553,7 @@ struct mei_device { unsigned long reset_count; enum mei_dev_state dev_state; enum mei_hbm_state hbm_state; + enum mei_dev_pxp_mode pxp_mode; u16 init_clients_timer; =20 /* diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h index 4894d8bf4159..506912ad363b 100644 --- a/include/linux/mei_aux.h +++ b/include/linux/mei_aux.h @@ -12,6 +12,8 @@ * @aux_dev: - auxiliary device object * @irq: interrupt driving the mei auxiliary device * @bar: mmio resource bar reserved to mei auxiliary device + * @ext_op_mem: resource for extend operational memory + * used in graphics PXP mode. * @slow_firmware: The device has slow underlying firmware. * Such firmware will require to use larger operation time= outs. */ @@ -19,6 +21,7 @@ struct mei_aux_device { struct auxiliary_device aux_dev; int irq; struct resource bar; + struct resource ext_op_mem; bool slow_firmware; }; =20 --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8F98C38145 for ; Wed, 7 Sep 2022 16:00:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229601AbiIGQA4 (ORCPT ); Wed, 7 Sep 2022 12:00:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230153AbiIGQAN (ORCPT ); Wed, 7 Sep 2022 12:00:13 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50BFDE0E2 for ; Wed, 7 Sep 2022 08:59:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; 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07 Sep 2022 08:59:26 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Daniele Ceraolo Spurio Subject: [PATCH v8 12/16] mei: gsc: add transition to PXP mode in resume flow Date: Wed, 7 Sep 2022 18:58:09 +0300 Message-Id: <20220907155813.1427526-13-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vitaly Lubart Added transition to PXP mode in resume flow. CC: Daniele Ceraolo Spurio Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/gsc-me.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index 6b22726aed55..75765e4df4ed 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct d= evice *device) static int __maybe_unused mei_gsc_pm_resume(struct device *device) { struct mei_device *dev =3D dev_get_drvdata(device); + struct auxiliary_device *aux_dev; + struct mei_aux_device *adev; int err; + struct mei_me_hw *hw; =20 if (!dev) return -ENODEV; =20 + hw =3D to_me_hw(dev); + aux_dev =3D to_auxiliary_dev(device); + adev =3D auxiliary_dev_to_mei_aux_dev(aux_dev); + if (adev->ext_op_mem.start) { + mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem); + dev->pxp_mode =3D MEI_DEV_PXP_INIT; + } + err =3D mei_restart(dev); if (err) return err; --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EC6DC38145 for ; Wed, 7 Sep 2022 16:01:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230273AbiIGQBM (ORCPT ); Wed, 7 Sep 2022 12:01:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230090AbiIGQAd (ORCPT ); Wed, 7 Sep 2022 12:00:33 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F0DA915CD for ; Wed, 7 Sep 2022 09:00:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566403; x=1694102403; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hO/ygtyyqutcViUvWsaXsvt/Qi8P3M4tyR8fhZGvumg=; b=HPpl33S+4gWJv9hBeay5NyRyCX1LaKPhMshz3rB3KPegETjGjQr/RUZI qDmQGoDK5OKMx+rN7WfDySkxdN+ENCfhSv3II1F9zmuhuqlwYSPvMhvU3 Rxru66+Ph2ZUkUOR/LZh4sxDpvbOXtEe8j6or55I8xxY0MOghdcUgrGiA c3TqCzpH0S7kXrQ1MiR2lbzVfVzDQVAcGLdg31IMZdhRdMiX1M/SZGjE0 /YI66cVe+RZwI9canfLuPOY83QLH8U2PC6lOWqJfbPWlDRfqLzmIQ3QkL 9UU6A7J2mVA4doA6m5z5eW/zrEXIq4fDAwgoppZSQbAI9JDBzE4qdFLLp g==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701570" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701570" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:34 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676248208" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:30 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart Subject: [PATCH v8 13/16] mei: drop ready bits check after start Date: Wed, 7 Sep 2022 18:58:10 +0300 Message-Id: <20220907155813.1427526-14-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin The check that hardware and host ready bits are set after start is redundant and may fail and disable driver if there is back-to-back link reset issued right after start. This happens during pxp mode transitions when firmware undergo reset. Remove these checks to eliminate such failures. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/init.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c index 1b4d5d7870b9..bac8852aad51 100644 --- a/drivers/misc/mei/init.c +++ b/drivers/misc/mei/init.c @@ -218,16 +218,6 @@ int mei_start(struct mei_device *dev) goto err; } =20 - if (!mei_host_is_ready(dev)) { - dev_err(dev->dev, "host is not ready.\n"); - goto err; - } - - if (!mei_hw_is_ready(dev)) { - dev_err(dev->dev, "ME is not ready.\n"); - goto err; - } - if (!mei_hbm_version_is_supported(dev)) { dev_dbg(dev->dev, "MEI start failed.\n"); goto err; --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 029B2C38145 for ; Wed, 7 Sep 2022 16:01:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230295AbiIGQBU (ORCPT ); Wed, 7 Sep 2022 12:01:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230103AbiIGQAe (ORCPT ); Wed, 7 Sep 2022 12:00:34 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F18F9413A for ; Wed, 7 Sep 2022 09:00:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566404; x=1694102404; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ctTJMUTnAD3HTjtYrfTyMDMJuY75ucboxfaHNzv14NA=; b=e3QKD24OYT3rz+uoeP+64t9sFtKJFqhy4dD+tHL5F1f9X9jlLbfkOxWn vItiGmYCb6piFq0eBgxaBzKzw1DIcoXZphh6SkyPVhw0co/kE1NjoA1AI jUN4dDetNBtXFRJUXz4X/6mjKe/dOsZHg9tDU4x9sHpDYrGbNEiD2u6Zb +haq2OuNBOAZ5C9lcr1jMzRGBT+BoP11YjbHlousM0di3loQFUGiqQ2td 6/dlI91N1xGqxAzIooUPZlHlPXTJTUfi4Cc7ZEvkr5wfN/meh/9QQzGqi b41OUujniMHS0QnGzUYc0zuXDPC+VM/R3Cz3aYyUVa2BhSugy183sBqmw Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="297701606" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="297701606" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:38 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676248239" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:34 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart Subject: [PATCH v8 14/16] mei: debugfs: add pxp mode to devstate in debugfs Date: Wed, 7 Sep 2022 18:58:11 +0300 Message-Id: <20220907155813.1427526-15-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pxp mode devstate to debugfs to monitor pxp state machine progress. This is useful to debug issues in scenarios in which the pxp state needs to be re-initialized, like during power transitions such as suspend/resume. With this debugfs the state could be monitored to ensure that pxp is in the ready state. CC: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/misc/mei/debugfs.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c index 1ce61e9e24fc..3b098d4c8e3d 100644 --- a/drivers/misc/mei/debugfs.c +++ b/drivers/misc/mei/debugfs.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2012-2016, Intel Corporation. All rights reserved + * Copyright (c) 2012-2022, Intel Corporation. All rights reserved * Intel Management Engine Interface (Intel MEI) Linux driver */ =20 @@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, voi= d *unused) } DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active); =20 +static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state) +{ +#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state + switch (state) { + MEI_PXP_MODE(DEFAULT); + MEI_PXP_MODE(INIT); + MEI_PXP_MODE(SETUP); + MEI_PXP_MODE(READY); + default: + return "unknown"; + } +#undef MEI_PXP_MODE +} + static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused) { struct mei_device *dev =3D m->private; @@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, = void *unused) seq_printf(m, "pg: %s, %s\n", mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED", mei_pg_state_str(mei_pg_state(dev))); + + seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode)); + return 0; } DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate); --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F504C54EE9 for ; Wed, 7 Sep 2022 16:01:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230209AbiIGQBF (ORCPT ); Wed, 7 Sep 2022 12:01:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230228AbiIGQAc (ORCPT ); Wed, 7 Sep 2022 12:00:32 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CB22923EE for ; Wed, 7 Sep 2022 09:00:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662566403; x=1694102403; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=czKBK1I1t6IX3MrJeeUjnEh9lCUYn7EwGmpszO7xZsU=; b=f0YjKyBtcF92ESWCSyYoNUTCCnAYicq0EycyvXEdVCkp/F+w1jP4Uh51 VeVr86dOxoM5LJQHB/klL7rjrCCERed3AKJalKQs9+PEZLXMIo/ynbqZH 51N1zPFbv/m8NBNM/K2S6GuH3Kr1CR7KrO55Pb4KjpO+ZpRGOXvducVEw mBnrEUMajlsDNFH+4JechjRHMC/UPf2klB/EzGA4OINc8+Schfjn99mXG ihx6VmYkaWaPngOr5xVpMiAsIDdPq4ilA4pLGyIInRMOn5TX2WvMXHUDn EN5UO6zgCYamnK1MMW/92guxFYZjJFK8AXQAnp1bHpQmP2yN+ZQ7EBmzQ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="298232343" X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="298232343" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:45 -0700 X-IronPort-AV: E=Sophos;i="5.93,297,1654585200"; d="scan'208";a="676248308" Received: from twinkler-lnx.jer.intel.com ([10.12.87.143]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 08:59:38 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Alan Previn , Daniele Ceraolo Spurio Subject: [PATCH v8 15/16] drm/i915/gsc: allocate extended operational memory in LMEM Date: Wed, 7 Sep 2022 18:58:12 +0300 Message-Id: <20220907155813.1427526-16-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" GSC requires more operational memory than available on chip. Reserve 4M of LMEM for GSC operation. The memory is provided to the GSC as struct resource to the auxiliary data of the child device. Cc: Alan Previn Signed-off-by: Tomas Winkler Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Alexander Usyskin Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_gsc.c | 91 ++++++++++++++++++++++++++--- drivers/gpu/drm/i915/gt/intel_gsc.h | 3 + 2 files changed, 87 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/= intel_gsc.c index e1040c8f2fd3..162bea57fbb5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -7,6 +7,7 @@ #include #include "i915_drv.h" #include "i915_reg.h" +#include "gem/i915_gem_region.h" #include "gt/intel_gsc.h" #include "gt/intel_gt.h" =20 @@ -36,12 +37,68 @@ static int gsc_irq_init(int irq) return irq_set_chip_data(irq, NULL); } =20 +static int +gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_= t size) +{ + struct intel_gt *gt =3D gsc_to_gt(gsc); + struct drm_i915_gem_object *obj; + void *vaddr; + int err; + + obj =3D i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGU= OUS); + if (IS_ERR(obj)) { + drm_err(>->i915->drm, "Failed to allocate gsc memory\n"); + return PTR_ERR(obj); + } + + err =3D i915_gem_object_pin_pages_unlocked(obj); + if (err) { + drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n"); + goto out_put; + } + + vaddr =3D i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt= ->i915, obj, true)); + if (IS_ERR(vaddr)) { + err =3D PTR_ERR(vaddr); + drm_err(>->i915->drm, "Failed to map gsc memory\n"); + goto out_unpin; + } + + memset(vaddr, 0, obj->base.size); + + i915_gem_object_unpin_map(obj); + + intf->gem_obj =3D obj; + + return 0; + +out_unpin: + i915_gem_object_unpin_pages(obj); +out_put: + i915_gem_object_put(obj); + return err; +} + +static void gsc_ext_om_destroy(struct intel_gsc_intf *intf) +{ + struct drm_i915_gem_object *obj =3D fetch_and_zero(&intf->gem_obj); + + if (!obj) + return; + + if (i915_gem_object_has_pinned_pages(obj)) + i915_gem_object_unpin_pages(obj); + + i915_gem_object_put(obj); +} + struct gsc_def { const char *name; unsigned long bar; size_t bar_size; bool use_polling; bool slow_firmware; + size_t lmem_size; }; =20 /* gsc resources and definitions (HECI1 and HECI2) */ @@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] =3D { .name =3D "mei-gsc", .bar =3D DG2_GSC_HECI1_BASE, .bar_size =3D GSC_BAR_LENGTH, + .lmem_size =3D SZ_4M, }, { .name =3D "mei-gscfi", @@ -90,26 +148,32 @@ static void gsc_release_dev(struct device *dev) kfree(adev); } =20 -static void gsc_destroy_one(struct intel_gsc_intf *intf) +static void gsc_destroy_one(struct drm_i915_private *i915, + struct intel_gsc *gsc, unsigned int intf_id) { + struct intel_gsc_intf *intf =3D &gsc->intf[intf_id]; + if (intf->adev) { auxiliary_device_delete(&intf->adev->aux_dev); auxiliary_device_uninit(&intf->adev->aux_dev); intf->adev =3D NULL; } + if (intf->irq >=3D 0) irq_free_desc(intf->irq); intf->irq =3D -1; + + gsc_ext_om_destroy(intf); } =20 -static void gsc_init_one(struct drm_i915_private *i915, - struct intel_gsc_intf *intf, +static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *= gsc, unsigned int intf_id) { struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); struct mei_aux_device *adev; struct auxiliary_device *aux_dev; const struct gsc_def *def; + struct intel_gsc_intf *intf =3D &gsc->intf[intf_id]; int ret; =20 intf->irq =3D -1; @@ -141,7 +205,7 @@ static void gsc_init_one(struct drm_i915_private *i915, intf->irq =3D irq_alloc_desc(0); if (intf->irq < 0) { drm_err(&i915->drm, "gsc irq error %d\n", intf->irq); - return; + goto fail; } =20 ret =3D gsc_irq_init(intf->irq); @@ -155,6 +219,19 @@ static void gsc_init_one(struct drm_i915_private *i915, if (!adev) goto fail; =20 + if (def->lmem_size) { + drm_dbg(&i915->drm, "setting up GSC lmem\n"); + + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) { + drm_err(&i915->drm, "setting up gsc extended operational memory failed\= n"); + kfree(adev); + goto fail; + } + + adev->ext_op_mem.start =3D i915_gem_object_get_dma_address(intf->gem_obj= , 0); + adev->ext_op_mem.end =3D adev->ext_op_mem.start + def->lmem_size; + } + adev->irq =3D intf->irq; adev->bar.parent =3D &pdev->resource[0]; adev->bar.start =3D def->bar + pdev->resource[0].start; @@ -188,7 +265,7 @@ static void gsc_init_one(struct drm_i915_private *i915, =20 return; fail: - gsc_destroy_one(intf); + gsc_destroy_one(i915, gsc, intf->id); } =20 static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id) @@ -229,7 +306,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i= 915_private *i915) return; =20 for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) - gsc_init_one(i915, &gsc->intf[i], i); + gsc_init_one(i915, gsc, i); } =20 void intel_gsc_fini(struct intel_gsc *gsc) @@ -241,5 +318,5 @@ void intel_gsc_fini(struct intel_gsc *gsc) return; =20 for (i =3D 0; i < INTEL_GSC_NUM_INTERFACES; i++) - gsc_destroy_one(&gsc->intf[i]); + gsc_destroy_one(gt->i915, gsc, i); } diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/= intel_gsc.h index 68582f912b21..fcac1775e9c3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.h +++ b/drivers/gpu/drm/i915/gt/intel_gsc.h @@ -20,11 +20,14 @@ struct mei_aux_device; =20 /** * struct intel_gsc - graphics security controller + * + * @gem_obj: scratch memory GSC operations * @intf : gsc interface */ struct intel_gsc { struct intel_gsc_intf { struct mei_aux_device *adev; + struct drm_i915_gem_object *gem_obj; int irq; unsigned int id; } intf[INTEL_GSC_NUM_INTERFACES]; --=20 2.37.2 From nobody Wed Apr 8 12:36:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF883C54EE9 for ; Wed, 7 Sep 2022 16:01:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230290AbiIGQBR (ORCPT ); Wed, 7 Sep 2022 12:01:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230191AbiIGQAe (ORCPT ); Wed, 7 Sep 2022 12:00:34 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F0C794102 for ; Wed, 7 Sep 2022 09:00:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; 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07 Sep 2022 08:59:43 -0700 From: Tomas Winkler To: Greg Kroah-Hartman , David Airlie , Daniel Vetter Cc: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , Daniele Ceraolo Spurio Subject: [PATCH v8 16/16] HAX: drm/i915: force INTEL_MEI_GSC on for CI Date: Wed, 7 Sep 2022 18:58:13 +0300 Message-Id: <20220907155813.1427526-17-tomas.winkler@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220907155813.1427526-1-tomas.winkler@intel.com> References: <20220907155813.1427526-1-tomas.winkler@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniele Ceraolo Spurio After the new config option is merged we'll enable it by default in the CI config, but for now just force it on via the i915 Kconfig so we can get pre-merge CI results for it. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Acked-by: Greg Kroah-Hartman Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kcon= fig.debug index e7fd3e76f8a2..be4ef485d6c1 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -48,6 +48,7 @@ config DRM_I915_DEBUG select DRM_I915_DEBUG_RUNTIME_PM select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST + select INTEL_MEI_GSC select BROKEN # for prototype uAPI default n help --=20 2.37.2