From nobody Wed Apr 8 12:49:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E7D9C54EE9 for ; Wed, 7 Sep 2022 13:13:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229964AbiIGNM6 (ORCPT ); Wed, 7 Sep 2022 09:12:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229703AbiIGNMu (ORCPT ); Wed, 7 Sep 2022 09:12:50 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF8267CAB3; Wed, 7 Sep 2022 06:12:48 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id c11so16103402wrp.11; Wed, 07 Sep 2022 06:12:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=ChvOmSu5GMdmA6vtxRRGmQLc6VAohBorLSB7RCrJOu8=; b=akGKdeXu89Uh6JyTP01iqJjWtIfb1YzVaMPl6uIA8nDO4WhVwYIF6fscB6M4WFNz1V +2aMhOQX39U5l1qNJ46YHpV2aHOZ6PirFJWivmk0cWAOrKjHaRjbDT3IzQYyQG4Z66EN Aoi/JpvemWPDWu4+zJclXOqksPRIljM1zK0v2KKW61LxGbJ5EZiwjig75NU8cMhuwws5 JYKWrTLrpz9mDfoAIloVIAbNAzilMwvRewj/9oBuIdqYHRJ/hpeTK2IwZ1uRF+vZV27D lXFtYvHBg/rtTTGNpOKwwXUSb08X45mA1PlrM2OYDy4j/4NllqMx7PWpRW7o8nb3hb/D Bm/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=ChvOmSu5GMdmA6vtxRRGmQLc6VAohBorLSB7RCrJOu8=; b=4DRTWdAsE8nndX+IM7Hfxqq4QDhs8krL7aeOhjuJgJeVh3jKncSBODBtlKQ+0FCyUT T4Qyz1jjrNYiNM8Bm3IEG8CyNTG1qJoShJx9mqykApu4aBzVAmlacMWIQgqHqjqJnLrN A3utv98MevJ4OVd0nJT4p27TfvO9TmIwK0rGsOgyOToHWrz07Mi6hdRABLAJ3GkIvp4K Hq4nOvPyB/U5wLRy1bgBAuDyUNjHNHEA/7QRn8HW+x3TRSk5kmWbtIKvCSQLfBBH/kRp jgrlYnnyv58uSw4AT4kyQ9SenlUeJi9xYU8CsBL6juN89Beo+KgUWzOVMqqGlK1g7U9w xGig== X-Gm-Message-State: ACgBeo2tTx0MidgeQ3fdyl8gsl2vuM5BHWgn/7qpBOTAn1prTaOYwQco ohD+q8loz+GLtd8I1vlqxlxsW2hsu8M= X-Google-Smtp-Source: AA6agR7F4oF9Ad/R2XJmtlXeddAaXEO1rNnkfG5wkXsaCDF4gY+KG0aQwBHya4Mr3b1EDa/759BhuQ== X-Received: by 2002:adf:b646:0:b0:221:76eb:b3ba with SMTP id i6-20020adfb646000000b0022176ebb3bamr2076477wre.237.1662556366956; Wed, 07 Sep 2022 06:12:46 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id m23-20020a05600c3b1700b003a5e7435190sm28667784wms.32.2022.09.07.06.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 06:12:46 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] dt-bindings: pwm: Add Mstar MSC313e PWM devicetree bindings documentation Date: Wed, 7 Sep 2022 15:12:37 +0200 Message-Id: <20220907131241.31941-2-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the documentation for the devicetree bindings of the Mstar MSC313e PWM driver, it includes MSC313e SoCs and SSD20xd. Signed-off-by: Romain Perier Reviewed-by: Rob Herring --- .../bindings/pwm/mstar,msc313e-pwm.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm= .yaml diff --git a/Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml b= /Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml new file mode 100644 index 000000000000..07f3f576f21b --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/mstar,msc313e-pwm.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/mstar,msc313e-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mstar MSC313e PWM controller + +allOf: + - $ref: "pwm.yaml#" + +maintainers: + - Daniel Palmer + - Romain Perier + +properties: + compatible: + items: + - enum: + - mstar,msc313e-pwm + - mstar,ssd20xd-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm: pwm@3400 { + compatible =3D "mstar,msc313e-pwm"; + reg =3D <0x3400 0x400>; + #pwm-cells =3D <2>; + clocks =3D <&xtal_div2>; + }; --=20 2.35.1 From nobody Wed Apr 8 12:49:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42FF6C38145 for ; Wed, 7 Sep 2022 13:13:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230041AbiIGNNG (ORCPT ); Wed, 7 Sep 2022 09:13:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229780AbiIGNMw (ORCPT ); Wed, 7 Sep 2022 09:12:52 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8AEF7F247; Wed, 7 Sep 2022 06:12:49 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id bd26-20020a05600c1f1a00b003a5e82a6474so9474395wmb.4; Wed, 07 Sep 2022 06:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=QgQzrH/5u6O4v9L6yKc0YnpRc+Pdf5VnE9vcckt75yk=; b=W4kDYvSWcWVYU846PJOgv2OoteQcSTm4QUKlIaSCMjq5dcqWzh7hWWPtrHuK1zcUNr caTvBBbLAL4FpbU3QHD+OcVi9GWzwq/Dy7TEaBSSu0UlXSAiDLg990u0/cwV+p/bln3r tBuHcqzdY48mmbunNRgOkC6q8cM21otf5/TALhvJFr2ZJ1XLBAWUwJsgqCZQJOsOf8J2 mZRVtJZ3670h5XYaM7iVCNGHX24tbP0W3I9YQ6Aly68KJI+CNPzBhKd70KdiPwDd46a8 A6+HcFQtf0aNHFXhRxJh37W52Np85p728nevElpNPCQOkgLkSFL4aRpYqPbz+8c/I9Zv u68w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=QgQzrH/5u6O4v9L6yKc0YnpRc+Pdf5VnE9vcckt75yk=; b=M1XaJcJSyu1hQgiGDPrPArJDaREkETqF6nHVv9T4b2/1ZsBVvgNxxbY6/BwqfHHGKi TgcgSICRNFe4ooWKTxrfGsJLVxR+5yfo9FvhLx45nBqz25BNYc1JCPL0j3/fGjUslmjk iBM167pC2d523CGQSfme7G7aMXt22foSUa2wmHuMzX59Ltucmby64L2L6582XKA4+IF/ BwwC7TxrOOrR3QpUaukDtdliGi1CkzNvR+qYJFToJAbpeoZRRXdWrpMbT83UNqVrV8H7 suUMU5Hi+ZvXRx9NIeaNT452nGpu1bA+BEltMOonSgoPmcS2bVRGifvlbJstgjdRB9GN vufQ== X-Gm-Message-State: ACgBeo3ADphEg+0O5xLxGsNnqNaFO+f0ts1irCRfap2ba841uOToKb5t YB6F3kMDfH5R7oXfCzOlh6ha354fd74= X-Google-Smtp-Source: AA6agR451FJk9pwztH7RtTiFRro2EoTxpghDJ12xgov2F7TD2BIRO6eN2TJisuk6uvmCSczE+3dZvw== X-Received: by 2002:a05:600c:3541:b0:3a6:28e4:c458 with SMTP id i1-20020a05600c354100b003a628e4c458mr1998543wmq.188.1662556368121; Wed, 07 Sep 2022 06:12:48 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id w14-20020adfd4ce000000b00228de351fc0sm5150512wrk.38.2022.09.07.06.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 06:12:47 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] pwm: Add support for the MSTAR MSC313 PWM Date: Wed, 7 Sep 2022 15:12:38 +0200 Message-Id: <20220907131241.31941-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Daniel Palmer This adds support for the PWM block on the Mstar MSC313e SoCs and newer. Signed-off-by: Daniel Palmer Co-developed-by: Romain Perier Signed-off-by: Romain Perier --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-msc313e.c | 269 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 280 insertions(+) create mode 100644 drivers/pwm/pwm-msc313e.c diff --git a/MAINTAINERS b/MAINTAINERS index 9d7f64dc0efe..c3b39b09097c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2439,6 +2439,7 @@ F: arch/arm/mach-mstar/ F: drivers/clk/mstar/ F: drivers/clocksource/timer-msc313e.c F: drivers/gpio/gpio-msc313.c +F: drivers/pwm/pwm-msc313e.c F: drivers/rtc/rtc-msc313.c F: drivers/watchdog/msc313e_wdt.c F: include/dt-bindings/clock/mstar-* diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..8049fd03a821 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -372,6 +372,15 @@ config PWM_MESON To compile this driver as a module, choose M here: the module will be called pwm-meson. =20 +config PWM_MSC313E + tristate "MStar MSC313e PWM support" + depends on ARCH_MSTARV7 || COMPILE_TEST + help + Generic PWM framework driver for MSTAR MSC313e. + + To compile this driver as a module, choose M here: the module + will be called pwm-msc313e. + config PWM_MTK_DISP tristate "MediaTek display PWM driver" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..bc285c054f2a 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -62,4 +62,5 @@ obj-$(CONFIG_PWM_TWL) +=3D pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) +=3D pwm-twl-led.o obj-$(CONFIG_PWM_VISCONTI) +=3D pwm-visconti.o obj-$(CONFIG_PWM_VT8500) +=3D pwm-vt8500.o +obj-$(CONFIG_PWM_MSC313E) +=3D pwm-msc313e.o obj-$(CONFIG_PWM_XILINX) +=3D pwm-xilinx.o diff --git a/drivers/pwm/pwm-msc313e.c b/drivers/pwm/pwm-msc313e.c new file mode 100644 index 000000000000..a71f39ba66c3 --- /dev/null +++ b/drivers/pwm/pwm-msc313e.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Daniel Palmer + * Copyright (C) 2022 Romain Perier + */ + +#include +#include +#include +#include + +#define DRIVER_NAME "msc313e-pwm" + +#define CHANNEL_OFFSET 0x80 +#define REG_DUTY 0x8 +#define REG_PERIOD 0x10 +#define REG_DIV 0x18 +#define REG_CTRL 0x1c +#define REG_SWRST 0x1fc + +struct msc313e_pwm_channel { + struct regmap_field *clkdiv; + struct regmap_field *polarity; + struct regmap_field *dutyl; + struct regmap_field *dutyh; + struct regmap_field *periodl; + struct regmap_field *periodh; + struct regmap_field *swrst; +}; + +struct msc313e_pwm { + struct regmap *regmap; + struct pwm_chip pwmchip; + struct clk *clk; + struct msc313e_pwm_channel channels[]; +}; + +struct msc313e_pwm_info { + unsigned int channels; +}; + +#define to_msc313e_pwm(ptr) container_of(ptr, struct msc313e_pwm, pwmchip) + +static const struct regmap_config msc313e_pwm_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 16, + .reg_stride =3D 4, +}; + +static const struct msc313e_pwm_info msc313e_data =3D { + .channels =3D 8, +}; + +static const struct msc313e_pwm_info ssd20xd_data =3D { + .channels =3D 4, +}; + +static void msc313e_pwm_writecounter(struct regmap_field *low, struct regm= ap_field *high, u32 value) +{ + /* The bus that connects the CPU to the peripheral registers splits 32 bi= t registers into + * two 16bit registers placed 4 bytes apart. It's the hardware design the= y used. The counter + * we are about to write has this contrainst. + */ + regmap_field_write(low, value & 0xffff); + regmap_field_write(high, value >> 16); +} + +static void msc313e_pwm_readcounter(struct regmap_field *low, struct regma= p_field *high, u32 *value) +{ + unsigned int val =3D 0; + + regmap_field_read(low, &val); + *value =3D val; + regmap_field_read(high, &val); + *value =3D (val << 16) | *value; +} + +static int msc313e_pwm_config(struct pwm_chip *chip, struct pwm_device *de= vice, + int duty_ns, int period_ns) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + unsigned long long nspertick =3D DIV_ROUND_DOWN_ULL(NSEC_PER_SEC, clk_get= _rate(pwm->clk)); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + unsigned long long div =3D 1; + + /* Fit the period into the period register by prescaling the clk */ + while (DIV_ROUND_DOWN_ULL(period_ns, nspertick) > 0x3ffff) { + div++; + if (div > (0xffff + 1)) { + /* Force clk div to the maximum allowed value */ + div =3D 0xffff; + break; + } + nspertick =3D DIV_ROUND_DOWN_ULL(nspertick, div); + } + + regmap_field_write(channel->clkdiv, div - 1); + msc313e_pwm_writecounter(channel->dutyl, channel->dutyh, + DIV_ROUND_DOWN_ULL(duty_ns, nspertick)); + msc313e_pwm_writecounter(channel->periodl, channel->periodh, + DIV_ROUND_DOWN_ULL(period_ns, nspertick)); + return 0; +}; + +static int msc313e_pwm_set_polarity(struct pwm_chip *chip, struct pwm_devi= ce *device, + enum pwm_polarity polarity) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + unsigned int pol =3D 0; + + if (polarity =3D=3D PWM_POLARITY_INVERSED) + pol =3D 1; + regmap_field_update_bits(channel->polarity, 1, pol); + + return 0; +} + +static int msc313e_pwm_enable(struct pwm_chip *chip, struct pwm_device *de= vice) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + int ret; + + ret =3D clk_prepare_enable(pwm->clk); + if (ret) + return ret; + return regmap_field_write(channel->swrst, 0); +} + +static int msc313e_pwm_disable(struct pwm_chip *chip, struct pwm_device *d= evice) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + int ret; + + ret =3D regmap_field_write(channel->swrst, 1); + clk_disable_unprepare(pwm->clk); + return ret; +} + +static int msc313e_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + int ret; + + if (state->enabled) { + if (!pwm->state.enabled) { + ret =3D msc313e_pwm_enable(chip, pwm); + if (ret) + return ret; + } + msc313e_pwm_set_polarity(chip, pwm, state->polarity); + msc313e_pwm_config(chip, pwm, state->duty_cycle, state->period); + } else if (pwm->state.enabled) { + ret =3D msc313e_pwm_disable(chip, pwm); + } + return 0; +} + +static void msc313e_get_state(struct pwm_chip *chip, struct pwm_device *de= vice, + struct pwm_state *state) +{ + struct msc313e_pwm *pwm =3D to_msc313e_pwm(chip); + struct msc313e_pwm_channel *channel =3D &pwm->channels[device->hwpwm]; + unsigned long long nspertick =3D DIV_ROUND_DOWN_ULL(NSEC_PER_SEC, clk_get= _rate(pwm->clk)); + unsigned int val =3D 0; + + regmap_field_read(channel->polarity, &val); + state->polarity =3D val ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + + regmap_field_read(channel->swrst, &val); + state->enabled =3D val =3D=3D 0 ? true : false; + + msc313e_pwm_readcounter(channel->dutyl, channel->dutyh, &val); + state->duty_cycle =3D val * nspertick; + + msc313e_pwm_readcounter(channel->periodl, channel->periodh, &val); + state->period =3D val * nspertick; +} + +static const struct pwm_ops msc313e_pwm_ops =3D { + .apply =3D msc313e_apply, + .get_state =3D msc313e_get_state, + .owner =3D THIS_MODULE +}; + +static int msc313e_pwm_probe(struct platform_device *pdev) +{ + const struct msc313e_pwm_info *match_data; + struct device *dev =3D &pdev->dev; + struct msc313e_pwm *pwm; + __iomem void *base; + int i; + + match_data =3D of_device_get_match_data(dev); + if (!match_data) + return -EINVAL; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + pwm =3D devm_kzalloc(dev, struct_size(pwm, channels, match_data->channels= ), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + pwm->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), "Cannot get clk\n"); + + pwm->regmap =3D devm_regmap_init_mmio(dev, base, &msc313e_pwm_regmap_conf= ig); + if (IS_ERR(pwm->regmap)) + return dev_err_probe(dev, PTR_ERR(pwm->regmap), "Cannot get regmap\n"); + + for (i =3D 0; i < match_data->channels; i++) { + unsigned int offset =3D CHANNEL_OFFSET * i; + struct reg_field div_clkdiv_field =3D REG_FIELD(offset + REG_DIV, 0, 7); + struct reg_field ctrl_polarity_field =3D REG_FIELD(offset + REG_CTRL, 4,= 4); + struct reg_field dutyl_field =3D REG_FIELD(offset + REG_DUTY, 0, 15); + struct reg_field dutyh_field =3D REG_FIELD(offset + REG_DUTY + 4, 0, 2); + struct reg_field periodl_field =3D REG_FIELD(offset + REG_PERIOD, 0, 15); + struct reg_field periodh_field =3D REG_FIELD(offset + REG_PERIOD + 4, 0,= 2); + struct reg_field swrst_field =3D REG_FIELD(REG_SWRST, i, i); + + pwm->channels[i].clkdiv =3D devm_regmap_field_alloc(dev, pwm->regmap, + div_clkdiv_field); + pwm->channels[i].polarity =3D devm_regmap_field_alloc(dev, pwm->regmap, + ctrl_polarity_field); + pwm->channels[i].dutyl =3D devm_regmap_field_alloc(dev, pwm->regmap, dut= yl_field); + pwm->channels[i].dutyh =3D devm_regmap_field_alloc(dev, pwm->regmap, dut= yh_field); + pwm->channels[i].periodl =3D devm_regmap_field_alloc(dev, pwm->regmap, p= eriodl_field); + pwm->channels[i].periodh =3D devm_regmap_field_alloc(dev, pwm->regmap, p= eriodh_field); + pwm->channels[i].swrst =3D devm_regmap_field_alloc(dev, pwm->regmap, swr= st_field); + + /* Channels are enabled on boot, disable it until the pwm subsystem re-e= nable it + * explicitly + */ + regmap_field_write(pwm->channels[i].swrst, 1); + } + + pwm->pwmchip.dev =3D dev; + pwm->pwmchip.ops =3D &msc313e_pwm_ops; + pwm->pwmchip.npwm =3D match_data->channels; + + platform_set_drvdata(pdev, pwm); + + return devm_pwmchip_add(dev, &pwm->pwmchip); +} + +static const struct of_device_id msc313e_pwm_dt_ids[] =3D { + { .compatible =3D "mstar,msc313e-pwm", .data =3D &msc313e_data }, + { .compatible =3D "mstar,ssd20xd-pwm", .data =3D &ssd20xd_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, msc313e_pwm_dt_ids); + +static struct platform_driver msc313e_pwm_driver =3D { + .probe =3D msc313e_pwm_probe, + .driver =3D { + .name =3D DRIVER_NAME, + .of_match_table =3D msc313e_pwm_dt_ids, + }, +}; +module_platform_driver(msc313e_pwm_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Mstar MSC313e PWM driver"); +MODULE_AUTHOR("Daniel Palmer "); --=20 2.35.1 From nobody Wed Apr 8 12:49:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C039C6FA82 for ; Wed, 7 Sep 2022 13:13:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230084AbiIGNNL (ORCPT ); Wed, 7 Sep 2022 09:13:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229892AbiIGNMw (ORCPT ); Wed, 7 Sep 2022 09:12:52 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0BCB7F134; Wed, 7 Sep 2022 06:12:50 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id b17so6992085wrq.3; Wed, 07 Sep 2022 06:12:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=LwR7/AOTal+NwY86Mp0FPWEx+VIIdg+npTDhkz4uRZA=; b=j9qF+fk8yh03/leBQqIXtPMvvBhD5gSXNrahxJyOe9cRJ6n5TD/11Wq8it7YInP4Sq 9gBLObzPvIVgluWs5kKyquuPe1KuZVirw/j2xrUL5c3J6Bj8wlij7lYTMG/YKrdzgL6n VFKyBpEeMbBvsfI49oNtmBMQtvCTIz3+hk4OcHXlraNnOLc4xxMDEe+nID7kBgemXQ/m rQfeOhYr/0l9h83oswFfP40PPW8GAAB8Lt4cLHIMx0TFFKxzM1ci7zgPL84xlqmRw6zk pmcxGOmtUrpDQn8pPLj7SfRi4mGL3xiiup6KJIZkGqk+0O2QG35GoM+kP4kM0RS7oAto Fsjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=LwR7/AOTal+NwY86Mp0FPWEx+VIIdg+npTDhkz4uRZA=; b=lOtDU0kz93p/WxYgf3BJfPlhC1ZgY4BAzCdY3EzoIbBdkHxixdKo7yDlrf/YYRB1ii 36oUFGE2gEiY2AEn2cuHz8Zcl0oWaiN9s9SmCemgQ/q+AyTkaGq5tR8r1UYW1Eda66ly VwRpr0DVWFHZ/4ftg/M7BFs/aE9p6MK0BeN1l9D6Q3GqY8BdZwV1WLmmrZDWTGQv45LW mvsuZV4QN0qKB0Vp1g94NmS6+2TKkpFpot1CI8fvI4o7Foa6Yoy3cXPHRLmMW+KVf7td wWugN+RP+urUkPtlLMh9UhbMKvieVqvJGHAPsPAxI4OGTqDqs55Rnj2Vl5+zJeK01v8h G7WQ== X-Gm-Message-State: ACgBeo2HlgfsRE42+Pp5lqVPtEGfVVT+h2/HbUh910tYR4+SnwtiEGF5 imIG5GRvtPQFJymnxypYhnI+9LVwJzw= X-Google-Smtp-Source: AA6agR4V8GZNQUSgq/mg1BWNRizQZ43PEteRk2TrUnEBu3a9kle2wJbkTv937CeaDzNABkhdnSQ9jQ== X-Received: by 2002:a5d:6388:0:b0:228:c792:aabe with SMTP id p8-20020a5d6388000000b00228c792aabemr2041911wru.689.1662556369167; Wed, 07 Sep 2022 06:12:49 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id t4-20020a05600001c400b00228aea99efcsm10398230wrx.14.2022.09.07.06.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 06:12:48 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] ARM: dts: mstar: Add pwm device node to infinity Date: Wed, 7 Sep 2022 15:12:39 +0200 Message-Id: <20220907131241.31941-4-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the definition of the pwm device node. The PWM being able to work with the oscillator at 12Mhz for now, it shares the same xtal than other devices (rtc or watchdog for instance). Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/msta= r-infinity.dtsi index 441a917b88ba..752f4c26b31c 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -38,6 +38,16 @@ opp-800000000 { }; }; =20 +&soc { + pm_pwm: pwm@1f001da0 { + compatible =3D "mstar,msc313-pwm"; + reg =3D <0x1f001da0 0xc>; + #pwm-cells =3D <2>; + clocks =3D <&xtal_div2>; + status =3D "disabled"; + }; +}; + &cpu0 { operating-points-v2 =3D <&cpu0_opp_table>; }; --=20 2.35.1 From nobody Wed Apr 8 12:49:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4E48C54EE9 for ; Wed, 7 Sep 2022 13:13:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230061AbiIGNNQ (ORCPT ); Wed, 7 Sep 2022 09:13:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229903AbiIGNMx (ORCPT ); Wed, 7 Sep 2022 09:12:53 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCB3A7F267; Wed, 7 Sep 2022 06:12:51 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id k6-20020a05600c1c8600b003a54ecc62f6so9476565wms.5; Wed, 07 Sep 2022 06:12:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Cg9l8Dw5kbbaSW9iT/X0V7LIeInZuZuCPQHiyAl6l3A=; b=WaxsfxNy7+St/xFCEq7LB6yj5uX8QOofkkoPrnD7B01kaNBbXyjj14aMyijZX9eI5G iTmj9nFSUckNUW7x6cceUhVqxFrMHXAkuc/ztty+ZyEbCsXSsmcx5AxBjdSp89FUA9F1 O0jIG3qMaAyESeUqR1waMk7oXzcKR7QKXuFKWlWNH6Lpl4nknF6Lt50ejCl9RCw6I4BE 9/aDHlEYQK+PIvnT0tiobQZlvZhPZRGrx9JqRZBHdcS36UN89+FjwQjiImsBYTXq/ZSr hJYCR+MUlUUq1z8ZQ295H6dcYKc+vqxdJu9Dyx/1na33KCB09LznhkMcjeY3FJCkOQJ9 PhFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Cg9l8Dw5kbbaSW9iT/X0V7LIeInZuZuCPQHiyAl6l3A=; b=k8NJ8zo2wjDyFhawC74tPYxPebcpa1dFoSrO/OTO0JZQ5gZ1C69Bv8EyqJ4d0LuMRh 2rm2S4vOvDD9+uM5Thxb8kaARqCO9LuygfnuCapoKfxms4M6R9PRJgyrFoXC8q7EI0PV 0thPOcch4YuUKJoz8v7tMBmUmI8eFeepkcKFq+RHytL2IyatGydnZ12In+rTB+tgNuYU zj8qjmpO+DBmZUKTbC5JIqlg2lvZwoE8/5Ms5C95Xf1HHydqMF7L+kvFDftIUdoGqRM8 A/Mx1uHJv9Uh2Yn488jz167O9QEn05a60WAH2k0xhNRZpAcqcs/t9bZiqp2dp7HZ0P4/ Sy+w== X-Gm-Message-State: ACgBeo3mazjvrEr/8kQClEkrsw5HqOgiScOHHp4A+bOEtu9+SGxYpv3a hZiOd2rTVX2kysi0mqfOuHwPU7zdTyc= X-Google-Smtp-Source: AA6agR63JPlJ6/mZi4VqQFezZCqRtSgr+iT8vrl1gV+TaEHGA7RlV1QdCx55mc8jEd6KlXF3pkuycg== X-Received: by 2002:a05:600c:34c2:b0:3a5:d2f5:9d02 with SMTP id d2-20020a05600c34c200b003a5d2f59d02mr2083482wmq.153.1662556370181; Wed, 07 Sep 2022 06:12:50 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id bh5-20020a05600005c500b0021ee65426a2sm16745847wrb.65.2022.09.07.06.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 06:12:49 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] ARM: dts: mstar: Add pwm device node to infinity3 Date: Wed, 7 Sep 2022 15:12:40 +0200 Message-Id: <20220907131241.31941-5-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the definition of the pwm device node. The PWM being able to work with the oscillator at 12Mhz for now, it shares the same xtal than other devices (rtc or watchdog for instance). Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity3.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mst= ar-infinity3.dtsi index a56cf29e5d82..aa26f25392d0 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -67,3 +67,13 @@ opp-1512000000 { &imi { reg =3D <0xa0000000 0x20000>; }; + +&riu { + pwm: pwm@3400 { + compatible =3D "mstar,msc313e-pwm"; + reg =3D <0x3400 0x400>; + #pwm-cells =3D <2>; + clocks =3D <&xtal_div2>; + status =3D "disabled"; + }; +}; --=20 2.35.1 From nobody Wed Apr 8 12:49:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3515C38145 for ; Wed, 7 Sep 2022 13:13:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229487AbiIGNNV (ORCPT ); Wed, 7 Sep 2022 09:13:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbiIGNM6 (ORCPT ); Wed, 7 Sep 2022 09:12:58 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06E147E314; Wed, 7 Sep 2022 06:12:52 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id t14so13045987wrx.8; Wed, 07 Sep 2022 06:12:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=XhHHfhBS4JEZS5T4Cqsky8UODYiFkR3zFwNbdfWOgRM=; b=cNPthfE851d7tnORcRK51E1iI5AqPMQEo0UIapDJ1GUAaS8Z4ZppZZ7rLg5TOY1tuS ZQK4JcssPZtZ+Kdff2MXU4oAn9W8OdKmOU47c4ciwwvc8VP5azQaVUJAe1PXJ4JAeNVJ NpWGMfDVf9SkB5y1Jf7d3M50H+FHDReUXNXtfON70iPH30Jr0e525XQLwBypbmfGG9kB DcCNrQwNETpxUHoco8WOnCDHLrYOt5wx2EdQUnsyo9+QtJbnCV5yED/uhhNjO0+/fHz8 cfgTeIlHOoCh9mMrKmIIkNc6du8op7r5JLownxHSaCuG26MzZ76XmnF4rXSsJlPTGjPh c39w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=XhHHfhBS4JEZS5T4Cqsky8UODYiFkR3zFwNbdfWOgRM=; b=AALWwaLBh/kYJ2zt2atQ6EYKBaXmK/B3z6IvOhNA/Bmbx15EuP5oDr3KkKEcB5wKE2 CzMiTDZhvIXx1/LEjCQpmTYIOA7yqtTqTTuBhOPjuRKWsk8OU2sGvNeUTzL9BBMJkJAQ UcHdyb6+p8C3+6hcIF5iozConXJut5piE5CnCPV60M0FKjWXHxr4PMQZKfjpX7et1VjL h7MbXmQdukHoLQ5LUHFGhqBChD5UuGwfM/qYOHwwB6ubAJP0SKoa80mmyBQa5Nz9j+PX gfx1l5VUR52QCVCAt0LISWh3jpKM/azJaPe5O9eywjAPcHk/EdI9j/a5j/xBH9MvSFyM /0HA== X-Gm-Message-State: ACgBeo1IbkYFp6lSmVoaAKz0rLldZpwi4U+jQue0dEHxADwZakaSh+pQ E5nGty56JDzvChKmAEKpHq6mbMt66vU= X-Google-Smtp-Source: AA6agR4RcR+HDYfOlSTd0KPvM/Pn5D6JH1gw1MsiVX4ajkgr5c2JDjkO5ziK3Y8MEQ6KyTtY0oTSDQ== X-Received: by 2002:adf:dbc4:0:b0:225:333d:8404 with SMTP id e4-20020adfdbc4000000b00225333d8404mr2215948wrj.671.1662556371220; Wed, 07 Sep 2022 06:12:51 -0700 (PDT) Received: from debby ([2a01:e0a:a6d:a8d0:7ff4:8f61:5574:9f95]) by smtp.gmail.com with ESMTPSA id d11-20020adffd8b000000b00228df23bd51sm3975325wrr.82.2022.09.07.06.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 06:12:50 -0700 (PDT) From: Romain Perier To: Thierry Reding , Lee Jones , Daniel Palmer , Romain Perier , Rob Herring Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] ARM: dts: mstar: Add pwm device node to infinity2m Date: Wed, 7 Sep 2022 15:12:41 +0200 Message-Id: <20220907131241.31941-6-romain.perier@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220907131241.31941-1-romain.perier@gmail.com> References: <20220907131241.31941-1-romain.perier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds definition of the pwm device node, infinity2m has its own hardware variant, so use the one for ssd20xd. Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/ms= tar-infinity2m.dtsi index 1b485efd7156..70561e512483 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -32,6 +32,14 @@ cpu1: cpu@1 { }; =20 &riu { + pwm: pwm@3400 { + compatible =3D "mstar,ssd20xd-pwm"; + reg =3D <0x3400 0x400>; + #pwm-cells =3D <2>; + clocks =3D <&xtal_div2>; + status =3D "disabled"; + }; + smpctrl: smpctrl@204000 { reg =3D <0x204000 0x200>; status =3D "disabled"; --=20 2.35.1