From nobody Wed Apr 8 07:44:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31D59C38145 for ; Wed, 7 Sep 2022 08:04:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230283AbiIGIEs (ORCPT ); Wed, 7 Sep 2022 04:04:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230309AbiIGIE3 (ORCPT ); Wed, 7 Sep 2022 04:04:29 -0400 Received: from mail-sz.amlogic.com (mail-sz.amlogic.com [211.162.65.117]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9884693501; Wed, 7 Sep 2022 01:04:20 -0700 (PDT) Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2507.6; Wed, 7 Sep 2022 16:04:10 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v9 1/5] dt-bindings: nand: meson: fix meson nfc clock Date: Wed, 7 Sep 2022 16:04:01 +0800 Message-ID: <20220907080405.28240-2-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220907080405.28240-1-liang.yang@amlogic.com> References: <20220907080405.28240-1-liang.yang@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. At the beginning, a common MMC and NAND sub-clock was discussed and planed to be implemented as NFC clock provider, but now this series of patches of a common MMC and NAND sub-clock are never being accepted and the current binding was never valid. the reasons for giving up are: 1. EMMC and NAND, which are mutually exclusive anyway 2. coupling the EMMC and NAND. 3. it seems that a common MMC and NAND sub-clock is over engineered. and let us see the link fot more information: https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com so The meson nfc can't work now, let us rework the clock. Acked-by: Rob Herring Signed-off-by: Liang Yang --- .../bindings/mtd/amlogic,meson-nand.txt | 29 ++++++++----------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b= /Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt index 5794ab1147c1..5d5cdfef417f 100644 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt @@ -7,18 +7,19 @@ Required properties: - compatible : contains one of: - "amlogic,meson-gxl-nfc" - "amlogic,meson-axg-nfc" + +- reg : Offset and length of the register set + +- reg-names : "nfc" is the register set for NFC controller and "emmc" + is the register set for MCI controller. + - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. =20 - clock-names: Should contain the following: "core" - NFC module gate clock - "device" - device clock from eMMC sub clock controller - "rx" - rx clock phase - "tx" - tx clock phase - -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC - controller port C + "device" - parent clock for internal NFC =20 Optional children nodes: Children nodes represent the available nand chips. @@ -28,24 +29,18 @@ see Documentation/devicetree/bindings/mtd/nand-controll= er.yaml for generic bindi =20 Example demonstrate on AXG SoC: =20 - sd_emmc_c_clkc: mmc@7000 { - compatible =3D "amlogic,meson-axg-mmc-clkc", "syscon"; - reg =3D <0x0 0x7000 0x0 0x800>; - }; - nand-controller@7800 { compatible =3D "amlogic,meson-axg-nfc"; - reg =3D <0x0 0x7800 0x0 0x100>; + reg =3D <0x0 0x7800 0x0 0x100>, + <0x0 0x7000 0x0 0x800>; + reg-names =3D "nfc", "emmc"; #address-cells =3D <1>; #size-cells =3D <0>; interrupts =3D ; =20 clocks =3D <&clkc CLKID_SD_EMMC_C>, - <&sd_emmc_c_clkc CLKID_MMC_DIV>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; - clock-names =3D "core", "device", "rx", "tx"; - amlogic,mmc-syscon =3D <&sd_emmc_c_clkc>; + <&clkc CLKID_FCLK_DIV2>; + clock-names =3D "core", "device"; =20 pinctrl-names =3D "default"; pinctrl-0 =3D <&nand_pins>; --=20 2.37.1 From nobody Wed Apr 8 07:44:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC8FAC54EE9 for ; Wed, 7 Sep 2022 08:04:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230223AbiIGIEv (ORCPT ); Wed, 7 Sep 2022 04:04:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229703AbiIGIEg (ORCPT ); Wed, 7 Sep 2022 04:04:36 -0400 Received: from mail-sz.amlogic.com (mail-sz.amlogic.com [211.162.65.117]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0813B2AC2; Wed, 7 Sep 2022 01:04:29 -0700 (PDT) Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2507.6; Wed, 7 Sep 2022 16:04:12 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Kevin Hilman , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v9 2/5] mtd: rawnand: meson: fix the clock Date: Wed, 7 Sep 2022 16:04:02 +0800 Message-ID: <20220907080405.28240-3-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220907080405.28240-1-liang.yang@amlogic.com> References: <20220907080405.28240-1-liang.yang@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. At the beginning, a common MMC and NAND sub-clock was discussed and planed to be implemented as NFC clock provider, but now this series of patches of a common MMC and NAND sub-clock are never being accepted. the reasons for giving up are: 1. EMMC and NAND, which are mutually exclusive anyway 2. coupling the EMMC and NAND. 3. it seems that a common MMC and NAND sub-clock is over engineered. and let us see the link fot more information: https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com so The meson nfc can't work now, let us rework the clock. Reviewed-by: Kevin Hilman Signed-off-by: Liang Yang --- drivers/mtd/nand/raw/meson_nand.c | 82 +++++++++++++++---------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson= _nand.c index 817bddccb775..6b1c813c0795 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -56,6 +57,9 @@ =20 #define NFC_RB_IRQ_EN BIT(21) =20 +#define CLK_DIV_SHIFT 0 +#define CLK_DIV_WIDTH 6 + #define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \ ( \ (cmd_dir) | \ @@ -151,15 +155,15 @@ struct meson_nfc { struct nand_controller controller; struct clk *core_clk; struct clk *device_clk; - struct clk *phase_tx; - struct clk *phase_rx; + struct clk *nand_clk; + struct clk_divider nand_divider; =20 unsigned long clk_rate; u32 bus_timing; =20 struct device *dev; void __iomem *reg_base; - struct regmap *reg_clk; + void __iomem *reg_clk; struct completion completion; struct list_head chips; const struct meson_nfc_data *data; @@ -235,7 +239,7 @@ static void meson_nfc_select_chip(struct nand_chip *nan= d, int chip) nfc->timing.tbers_max =3D meson_chip->tbers_max; =20 if (nfc->clk_rate !=3D meson_chip->clk_rate) { - ret =3D clk_set_rate(nfc->device_clk, meson_chip->clk_rate); + ret =3D clk_set_rate(nfc->nand_clk, meson_chip->clk_rate); if (ret) { dev_err(nfc->dev, "failed to set clock rate\n"); return; @@ -987,6 +991,8 @@ static const struct mtd_ooblayout_ops meson_ooblayout_o= ps =3D { =20 static int meson_nfc_clk_init(struct meson_nfc *nfc) { + struct clk_parent_data nfc_divider_parent_data[1]; + struct clk_init_data init =3D {0}; int ret; =20 /* request core clock */ @@ -1002,21 +1008,28 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) return PTR_ERR(nfc->device_clk); } =20 - nfc->phase_tx =3D devm_clk_get(nfc->dev, "tx"); - if (IS_ERR(nfc->phase_tx)) { - dev_err(nfc->dev, "failed to get TX clk\n"); - return PTR_ERR(nfc->phase_tx); - } - - nfc->phase_rx =3D devm_clk_get(nfc->dev, "rx"); - if (IS_ERR(nfc->phase_rx)) { - dev_err(nfc->dev, "failed to get RX clk\n"); - return PTR_ERR(nfc->phase_rx); - } + init.name =3D devm_kasprintf(nfc->dev, + GFP_KERNEL, "%s#div", + dev_name(nfc->dev)); + init.ops =3D &clk_divider_ops; + nfc_divider_parent_data[0].fw_name =3D "device"; + init.parent_data =3D nfc_divider_parent_data; + init.num_parents =3D 1; + nfc->nand_divider.reg =3D nfc->reg_clk; + nfc->nand_divider.shift =3D CLK_DIV_SHIFT; + nfc->nand_divider.width =3D CLK_DIV_WIDTH; + nfc->nand_divider.hw.init =3D &init; + nfc->nand_divider.flags =3D CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ROUND_CLOSEST | + CLK_DIVIDER_ALLOW_ZERO; + + nfc->nand_clk =3D devm_clk_register(nfc->dev, &nfc->nand_divider.hw); + if (IS_ERR(nfc->nand_clk)) + return PTR_ERR(nfc->nand_clk); =20 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - regmap_update_bits(nfc->reg_clk, - 0, CLK_SELECT_NAND, CLK_SELECT_NAND); + writel(CLK_SELECT_NAND | readl(nfc->reg_clk), + nfc->reg_clk); =20 ret =3D clk_prepare_enable(nfc->core_clk); if (ret) { @@ -1030,29 +1043,21 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) goto err_device_clk; } =20 - ret =3D clk_prepare_enable(nfc->phase_tx); + ret =3D clk_prepare_enable(nfc->nand_clk); if (ret) { - dev_err(nfc->dev, "failed to enable TX clock\n"); - goto err_phase_tx; + dev_err(nfc->dev, "pre enable NFC divider fail\n"); + goto err_nand_clk; } =20 - ret =3D clk_prepare_enable(nfc->phase_rx); - if (ret) { - dev_err(nfc->dev, "failed to enable RX clock\n"); - goto err_phase_rx; - } - - ret =3D clk_set_rate(nfc->device_clk, 24000000); + ret =3D clk_set_rate(nfc->nand_clk, 24000000); if (ret) - goto err_disable_rx; + goto err_disable_clk; =20 return 0; =20 -err_disable_rx: - clk_disable_unprepare(nfc->phase_rx); -err_phase_rx: - clk_disable_unprepare(nfc->phase_tx); -err_phase_tx: +err_disable_clk: + clk_disable_unprepare(nfc->nand_clk); +err_nand_clk: clk_disable_unprepare(nfc->device_clk); err_device_clk: clk_disable_unprepare(nfc->core_clk); @@ -1061,8 +1066,7 @@ static int meson_nfc_clk_init(struct meson_nfc *nfc) =20 static void meson_nfc_disable_clk(struct meson_nfc *nfc) { - clk_disable_unprepare(nfc->phase_rx); - clk_disable_unprepare(nfc->phase_tx); + clk_disable_unprepare(nfc->nand_clk); clk_disable_unprepare(nfc->device_clk); clk_disable_unprepare(nfc->core_clk); } @@ -1396,13 +1400,9 @@ static int meson_nfc_probe(struct platform_device *p= dev) if (IS_ERR(nfc->reg_base)) return PTR_ERR(nfc->reg_base); =20 - nfc->reg_clk =3D - syscon_regmap_lookup_by_phandle(dev->of_node, - "amlogic,mmc-syscon"); - if (IS_ERR(nfc->reg_clk)) { - dev_err(dev, "Failed to lookup clock base\n"); + nfc->reg_clk =3D devm_platform_ioremap_resource_byname(pdev, "emmc"); + if (IS_ERR(nfc->reg_clk)) return PTR_ERR(nfc->reg_clk); - } =20 irq =3D platform_get_irq(pdev, 0); if (irq < 0) --=20 2.37.1 From nobody Wed Apr 8 07:44:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F360BECAAD3 for ; Wed, 7 Sep 2022 08:04:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230335AbiIGIE6 (ORCPT ); Wed, 7 Sep 2022 04:04:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230212AbiIGIEj (ORCPT ); Wed, 7 Sep 2022 04:04:39 -0400 Received: from mail-sz.amlogic.com (mail-sz.amlogic.com [211.162.65.117]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0951CCE29; Wed, 7 Sep 2022 01:04:36 -0700 (PDT) Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2507.6; Wed, 7 Sep 2022 16:04:14 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Kevin Hilman , Neil Armstrong , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Martin Blumenstingl , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v9 3/5] mtd: rawnand: meson: refine resource getting in probe Date: Wed, 7 Sep 2022 16:04:03 +0800 Message-ID: <20220907080405.28240-4-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220907080405.28240-1-liang.yang@amlogic.com> References: <20220907080405.28240-1-liang.yang@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" simply use devm_platform_ioremap_resource_byname() instead of two steps: res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0) and reg_base =3D devm_ioremap_resource(dev, res) Reviewed-by: Kevin Hilman Reviewed-by: Neil Armstrong Signed-off-by: Liang Yang --- drivers/mtd/nand/raw/meson_nand.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson= _nand.c index 6b1c813c0795..e7109d8f6e22 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -1378,7 +1378,6 @@ static int meson_nfc_probe(struct platform_device *pd= ev) { struct device *dev =3D &pdev->dev; struct meson_nfc *nfc; - struct resource *res; int ret, irq; =20 nfc =3D devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); @@ -1395,8 +1394,7 @@ static int meson_nfc_probe(struct platform_device *pd= ev) =20 nfc->dev =3D dev; =20 - res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); - nfc->reg_base =3D devm_ioremap_resource(dev, res); + nfc->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "nfc"); if (IS_ERR(nfc->reg_base)) return PTR_ERR(nfc->reg_base); =20 --=20 2.37.1 From nobody Wed Apr 8 07:44:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D0E8C54EE9 for ; Wed, 7 Sep 2022 08:05:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230360AbiIGIFD (ORCPT ); Wed, 7 Sep 2022 04:05:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230043AbiIGIEl (ORCPT ); Wed, 7 Sep 2022 04:04:41 -0400 Received: from mail-sz.amlogic.com (mail-sz.amlogic.com [211.162.65.117]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D502E12095; Wed, 7 Sep 2022 01:04:39 -0700 (PDT) Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2507.6; Wed, 7 Sep 2022 16:04:15 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v9 4/5] dt-bindings: nand: meson: convert txt to yaml Date: Wed, 7 Sep 2022 16:04:04 +0800 Message-ID: <20220907080405.28240-5-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220907080405.28240-1-liang.yang@amlogic.com> References: <20220907080405.28240-1-liang.yang@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" convert the amlogic,meson-name.txt to amlogic,meson-nand.yaml Signed-off-by: Liang Yang Reviewed-by: Rob Herring --- .../bindings/mtd/amlogic,meson-nand.txt | 55 ----------- .../bindings/mtd/amlogic,meson-nand.yaml | 93 +++++++++++++++++++ 2 files changed, 93 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nan= d.txt create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nan= d.yaml diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b= /Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt deleted file mode 100644 index 5d5cdfef417f..000000000000 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ /dev/null @@ -1,55 +0,0 @@ -Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs - -This file documents the properties in addition to those available in -the MTD NAND bindings. - -Required properties: -- compatible : contains one of: - - "amlogic,meson-gxl-nfc" - - "amlogic,meson-axg-nfc" - -- reg : Offset and length of the register set - -- reg-names : "nfc" is the register set for NFC controller and "emmc" - is the register set for MCI controller. - -- clocks : - A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. - -- clock-names: Should contain the following: - "core" - NFC module gate clock - "device" - parent clock for internal NFC - -Optional children nodes: -Children nodes represent the available nand chips. - -Other properties: -see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic= bindings. - -Example demonstrate on AXG SoC: - - nand-controller@7800 { - compatible =3D "amlogic,meson-axg-nfc"; - reg =3D <0x0 0x7800 0x0 0x100>, - <0x0 0x7000 0x0 0x800>; - reg-names =3D "nfc", "emmc"; - #address-cells =3D <1>; - #size-cells =3D <0>; - interrupts =3D ; - - clocks =3D <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_FCLK_DIV2>; - clock-names =3D "core", "device"; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&nand_pins>; - - nand@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <1>; - - nand-on-flash-bbt; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml = b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml new file mode 100644 index 000000000000..28fb9a7dd70f --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs + +allOf: + - $ref: nand-controller.yaml + +maintainers: + - liang.yang@amlogic.com + +properties: + compatible: + enum: + - amlogic,meson-gxl-nfc + - amlogic,meson-axg-nfc + + reg: + maxItems: 2 + + reg-names: + items: + - const: nfc + - const: emmc + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: device + +patternProperties: + "^nand@[0-7]$": + type: object + properties: + reg: + minimum: 0 + maximum: 1 + + nand-ecc-mode: + const: hw + + nand-ecc-step-size: + const: 1024 + + nand-ecc-strength: + enum: [8, 16, 24, 30, 40, 50, 60] + description: | + The ECC configurations that can be supported are as follows. + meson-gxl-nfc 8, 16, 24, 30, 40, 50, 60 + meson-axg-nfc 8 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + nand-controller@ffe07800 { + compatible =3D "amlogic,meson-axg-nfc"; + reg =3D <0xffe07800 0x100>, <0xffe07000 0x800>; + reg-names =3D "nfc", "emmc"; + interrupts =3D ; + clocks =3D <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>; + clock-names =3D "core", "device"; + + pinctrl-0 =3D <&nand_pins>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + nand@0 { + reg =3D <0>; + }; + }; + +... --=20 2.37.1 From nobody Wed Apr 8 07:44:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97FBAC38145 for ; Wed, 7 Sep 2022 08:06:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230232AbiIGIGA (ORCPT ); Wed, 7 Sep 2022 04:06:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230099AbiIGIFv (ORCPT ); Wed, 7 Sep 2022 04:05:51 -0400 Received: from mail-sz.amlogic.com (mail-sz.amlogic.com [211.162.65.117]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 246B2402E6; Wed, 7 Sep 2022 01:05:49 -0700 (PDT) Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2507.6; Wed, 7 Sep 2022 16:05:46 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , kernel test robot , Neil Armstrong , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v9 5/5] mtd: rawnand: meson: not support legacy clock Date: Wed, 7 Sep 2022 16:04:05 +0800 Message-ID: <20220907080405.28240-6-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220907080405.28240-1-liang.yang@amlogic.com> References: <20220907080405.28240-1-liang.yang@amlogic.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" meson NFC driver use common clock interfaces. so the test robot report some errors once using the legacy clock with HAVE_LEGACY_CLK on. Reported-by: kernel test robot Reviewed-by: Neil Armstrong Signed-off-by: Liang Yang --- drivers/mtd/nand/raw/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 30f061939560..dd2e7cdd7e84 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -395,7 +395,7 @@ config MTD_NAND_STM32_FMC2 =20 config MTD_NAND_MESON tristate "Support for NAND controller on Amlogic's Meson SoCs" - depends on ARCH_MESON || COMPILE_TEST + depends on COMMON_CLK && (ARCH_MESON || COMPILE_TEST) select MFD_SYSCON help Enables support for NAND controller on Amlogic's Meson SoCs. --=20 2.37.1