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charset="utf-8" The ddr-pmu on i.mx8dxl has a different interrupt number. Add a node label to ddr-pmu so that it could be referred and changed in i.mx8dxl dts. Signed-off-by: Shenwei Wang --- arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/bo= ot/dts/freescale/imx8-ss-ddr.dtsi index 8b5cad4e2700..7d5183c6c5be 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi @@ -10,7 +10,7 @@ ddr_subsys: bus@5c000000 { #size-cells =3D <1>; ranges =3D <0x5c000000 0x0 0x5c000000 0x1000000>; =20 - ddr-pmu@5c020000 { + ddr_pmu0: ddr-pmu@5c020000 { compatible =3D "fsl,imx8-ddr-pmu"; reg =3D <0x5c020000 0x10000>; interrupts =3D ; --=20 2.25.1 From nobody Mon Apr 6 14:10:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED94EECAAD5 for ; Tue, 6 Sep 2022 14:34:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbiIFOe4 (ORCPT ); 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charset="utf-8" Add the missing resource IDs for imx8dxl. Signed-off-by: Shenwei Wang Acked-by: Rob Herring --- include/dt-bindings/firmware/imx/rsrc.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/= firmware/imx/rsrc.h index 43885056557c..1675de05ad33 100644 --- a/include/dt-bindings/firmware/imx/rsrc.h +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -37,10 +37,14 @@ #define IMX_SC_R_DC_0_BLIT2 21 #define IMX_SC_R_DC_0_BLIT_OUT 22 #define IMX_SC_R_PERF 23 +#define IMX_SC_R_USB_1_PHY 24 #define IMX_SC_R_DC_0_WARP 25 +#define IMX_SC_R_V2X_MU_0 26 +#define IMX_SC_R_V2X_MU_1 27 #define IMX_SC_R_DC_0_VIDEO0 28 #define IMX_SC_R_DC_0_VIDEO1 29 #define IMX_SC_R_DC_0_FRAC0 30 +#define IMX_SC_R_V2X_MU_2 31 #define IMX_SC_R_DC_0 32 #define IMX_SC_R_GPU_2_PID0 33 #define IMX_SC_R_DC_0_PLL_0 34 @@ -49,7 +53,10 @@ #define IMX_SC_R_DC_1_BLIT1 37 #define IMX_SC_R_DC_1_BLIT2 38 #define IMX_SC_R_DC_1_BLIT_OUT 39 +#define IMX_SC_R_V2X_MU_3 40 +#define IMX_SC_R_V2X_MU_4 41 #define IMX_SC_R_DC_1_WARP 42 +#define IMX_SC_R_SECVIO 44 #define IMX_SC_R_DC_1_VIDEO0 45 #define IMX_SC_R_DC_1_VIDEO1 46 #define IMX_SC_R_DC_1_FRAC0 47 --=20 2.25.1 From nobody Mon Apr 6 14:10:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18FFAECAAD5 for ; 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charset="utf-8" i.MX8DXL is a device targeting the automotive and industrial market segments. The chip is designed to achieve both high performance and low power consumption. It has a dual (2x) Cortex-A35 processor. This patch adds the basic support for i.MX8DXL SoC. Signed-off-by: Shenwei Wang --- .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 52 ++++ .../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 142 +++++++++++ .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 9 + .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 74 ++++++ arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 238 ++++++++++++++++++ 5 files changed, 515 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8dxl-ss-adma.dtsi new file mode 100644 index 000000000000..795d1d472fae --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +&audio_ipg_clk { + clock-frequency =3D <160000000>; +}; + +&dma_ipg_clk { + clock-frequency =3D <160000000>; +}; + +&i2c0 { + compatible =3D "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi= 2c"; + interrupts =3D ; +}; + +&i2c1 { + compatible =3D "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi= 2c"; + interrupts =3D ; +}; + +&i2c2 { + compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts =3D ; +}; + +&i2c3 { + compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts =3D ; +}; + +&lpuart0 { + compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts =3D ; +}; + +&lpuart1 { + compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts =3D ; +}; + +&lpuart2 { + compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts =3D ; +}; + +&lpuart3 { + compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts =3D ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8dxl-ss-conn.dtsi new file mode 100644 index 000000000000..69c4849f2132 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +/delete-node/ &enet1_lpcg; +/delete-node/ &fec2; + +&conn_subsys { + conn_enet0_root_clk: clock-conn-enet0-root { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <250000000>; + clock-output-names =3D "conn_enet0_root_clk"; + }; + + eqos: ethernet@5b050000 { + compatible =3D "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; + reg =3D <0x5b050000 0x10000>; + interrupt-parent =3D <&gic>; + interrupts =3D , + ; + interrupt-names =3D "eth_wake_irq", "macirq"; + clocks =3D <&eqos_lpcg IMX_LPCG_CLK_4>, + <&eqos_lpcg IMX_LPCG_CLK_6>, + <&eqos_lpcg IMX_LPCG_CLK_0>, + <&eqos_lpcg IMX_LPCG_CLK_5>, + <&eqos_lpcg IMX_LPCG_CLK_2>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks =3D <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates =3D <125000000>; + power-domains =3D <&pd IMX_SC_R_ENET_1>; + status =3D "disabled"; + }; + + usbotg2: usb@5b0e0000 { + compatible =3D "fsl,imx8dxl-usb", "fsl,imx7ulp-usb"; + reg =3D <0x5b0e0000 0x200>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + fsl,usbphy =3D <&usbphy2>; + fsl,usbmisc =3D <&usbmisc2 0>; + /* + * usbotg1 and usbotg2 share one clcok. + * scu firmware disables the access to the clock and keeps + * it always on in case other core (M4) uses one of these. + */ + clocks =3D <&clk_dummy>; + ahb-burst-config =3D <0x0>; + tx-burst-size-dword =3D <0x10>; + rx-burst-size-dword =3D <0x10>; + #stream-id-cells =3D <1>; + power-domains =3D <&pd IMX_SC_R_USB_1>; + status =3D "disabled"; + + clk_dummy: clock-dummy { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + clock-output-names =3D "clk_dummy"; + }; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells =3D <1>; + compatible =3D "fsl,imx7ulp-usbmisc"; + reg =3D <0x5b0e0200 0x200>; + }; + + usbphy2: usbphy@0x5b110000 { + compatible =3D "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; + reg =3D <0x5b110000 0x1000>; + clocks =3D <&usb2_2_lpcg IMX_LPCG_CLK_7>; + power-domains =3D <&pd IMX_SC_R_USB_1_PHY>; + status =3D "disabled"; + }; + + eqos_lpcg: clock-controller@5b240000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x5b240000 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>; + clock-indices =3D , , + , , + ; + clock-output-names =3D "eqos_ptp", + "eqos_mem_clk", + "eqos_aclk", + "eqos_clk", + "eqos_csr_clk"; + power-domains =3D <&pd IMX_SC_R_ENET_1>; + }; + + usb2_2_lpcg: clock-controller@5b280000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x5b280000 0x10000>; + #clock-cells =3D <1>; + clock-indices =3D ; + clocks =3D <&conn_ipg_clk>; + clock-output-names =3D "usboh3_2_phy_ipg_clk"; + power-domains =3D <&pd IMX_SC_R_USB_1_PHY>; + }; + +}; + +&enet0_lpcg { + clocks =3D <&conn_enet0_root_clk>, + <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; +}; + +&fec1 { + compatible =3D "fsl,imx8qm-fec"; + interrupts =3D , + , + , + ; + assigned-clocks =3D <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates =3D <125000000>; +}; + +&usdhc1 { + compatible =3D "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; + interrupts =3D ; +}; + +&usdhc2 { + compatible =3D "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; + interrupts =3D ; +}; + +&usdhc3 { + compatible =3D "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; + interrupts =3D ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64= /boot/dts/freescale/imx8dxl-ss-ddr.dtsi new file mode 100644 index 000000000000..550f513708d8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +&ddr_pmu0 { + compatible =3D "fsl,imx8-ddr-pmu"; + interrupts =3D ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8dxl-ss-lsio.dtsi new file mode 100644 index 000000000000..815bd987b09b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +&lsio_gpio0 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio1 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio2 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio3 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio4 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio5 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio6 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio7 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_mu0 { + compatible =3D "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu1 { + compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu2 { + compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu3 { + compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu4 { + compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu5 { + compatible =3D "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/d= ts/freescale/imx8dxl.dtsi new file mode 100644 index 000000000000..5ddbda0b4def --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + ethernet0 =3D &fec1; + ethernet1 =3D &eqos; + gpio0 =3D &lsio_gpio0; + gpio1 =3D &lsio_gpio1; + gpio2 =3D &lsio_gpio2; + gpio3 =3D &lsio_gpio3; + gpio4 =3D &lsio_gpio4; + gpio5 =3D &lsio_gpio5; + gpio6 =3D &lsio_gpio6; + gpio7 =3D &lsio_gpio7; + mu1 =3D &lsio_mu1; + }; + + cpus: cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + /* We have 1 clusters with 2 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&A35_L2>; + clocks =3D <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&a35_opp_table>; + }; + + A35_1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&A35_L2>; + clocks =3D <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&a35_opp_table>; + }; + + A35_L2: l2-cache0 { + compatible =3D "cache"; + }; + }; + + a35_opp_table: opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <150000>; + }; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <1100000>; + clock-latency-ns =3D <150000>; + opp-suspend; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + dsp_reserved: dsp@92400000 { + reg =3D <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + system-controller { + compatible =3D "fsl,imx-scu"; + mbox-names =3D "tx0", + "rx0", + "gip3"; + mboxes =3D <&lsio_mu1 0 0 + &lsio_mu1 1 0 + &lsio_mu1 3 3>; + + pd: power-controller { + compatible =3D "fsl,scu-pd"; + #power-domain-cells =3D <1>; + wakeup-irq =3D <160 163 235 236 237 228 229 230 231 238 + 239 240 166 169>; + }; + + clk: clock-controller { + compatible =3D "fsl,imx8dxl-clk", "fsl,scu-clk"; + #clock-cells =3D <2>; + clocks =3D <&xtal32k &xtal24m>; + clock-names =3D "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible =3D "fsl,imx8dxl-iomuxc"; + }; + + ocotp: ocotp { + compatible =3D "fsl,imx8qxp-scu-ocotp"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + fec_mac0: mac@2c4 { + reg =3D <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg =3D <0x2c6 6>; + }; + }; + + rtc: rtc { + compatible =3D "fsl,imx8qxp-sc-rtc"; + }; + + sc_pwrkey: keys { + compatible =3D "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; + linux,keycode =3D ; + wakeup-source; + }; + + watchdog { + compatible =3D "fsl,imx-sc-wdt"; + timeout-sec =3D <60>; + }; + + tsens: thermal-sensor { + compatible =3D "fsl,imx-sc-thermal"; + #thermal-sensor-cells =3D <1>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive =3D <250>; + polling-delay =3D <2000>; + thermal-sensors =3D <&tsens IMX_SC_R_SYSTEM>; + + trips { + cpu_alert0: trip0 { + temperature =3D <107000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu_crit0: trip1 { + temperature =3D <127000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_alert0>; + cooling-device =3D + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + /* The two values below cannot be changed by the board */ + xtal32k: clock-xtal32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "xtal_24MHz"; + }; + + /* sorted in register address */ + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" +}; + +#include "imx8dxl-ss-adma.dtsi" +#include "imx8dxl-ss-conn.dtsi" +#include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-ddr.dtsi" --=20 2.25.1 From nobody Mon Apr 6 14:10:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9303ECAAD5 for ; Tue, 6 Sep 2022 14:36:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242048AbiIFOgO (ORCPT ); Tue, 6 Sep 2022 10:36:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242062AbiIFOew (ORCPT ); Tue, 6 Sep 2022 10:34:52 -0400 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2087.outbound.protection.outlook.com [40.107.22.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 876D3201A8; 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charset="utf-8" i.MX8DXL is a device targeting the automotive and industrial market segments. The chip is designed to achieve both high performance and low power consumption. It has a dual (2x) Cortex-A35 processor. Signed-off-by: Shenwei Wang Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 7431579ab0e8..4f4c9c0a1315 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1034,6 +1034,12 @@ properties: - toradex,colibri-imx8x # Colibri iMX8X Modules - const: fsl,imx8qxp =20 + - description: i.MX8DXL based Boards + items: + - enum: + - fsl,imx8dxl-evk # i.MX8DXL EVK Board + - const: fsl,imx8dxl + - description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules items: - enum: --=20 2.25.1 From nobody Mon Apr 6 14:10:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1F79C6FA83 for ; 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charset="utf-8" This is to support the EVK (Evaluation Kit Board) for the i.MX8DXL. The patch has enabled the serial console, SD/EMMC interface, and the eqos and fec ethernet network. Signed-off-by: Shenwei Wang --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 426 ++++++++++++++++++ 2 files changed, 427 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 8bf7f7ecebaa..2741205efe84 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) +=3D fsl-ls1028a-qds-85bb.d= tb dtb-$(CONFIG_ARCH_LAYERSCAPE) +=3D fsl-ls1028a-qds-899b.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) +=3D fsl-ls1028a-qds-9999.dtb =20 +dtb-$(CONFIG_ARCH_MXC) +=3D imx8dxl-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-ddr4-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boo= t/dts/freescale/imx8dxl-evk.dts new file mode 100644 index 000000000000..868c75945af3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +/dts-v1/; + +#include "imx8dxl.dtsi" + +/ { + model =3D "Freescale i.MX8DXL EVK"; + compatible =3D "fsl,imx8dxl-evk", "fsl,imx8dxl"; + + aliases { + i2c2 =3D &i2c2; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + serial0 =3D &lpuart0; + }; + + chosen { + stdout-path =3D &lpuart0; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00000000 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * Memory reserved for optee usage. Please do not use. + * This will be automatically added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg =3D <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0 0x14000000>; + alloc-ranges =3D <0 0x98000000 0 0x14000000>; + linux,cma-default; + }; + }; + + mux3_en: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "mux3_en"; + gpio =3D <&pca6416_2 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + reg_fec1_sel: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fec1_supply"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + regulator-always-on; + status =3D "disabled"; + }; + + reg_fec1_io: regulator-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fec1_io_supply"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + gpio =3D <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + status =3D "disabled"; + }; + + reg_usdhc2_vmmc: regulator-3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "SD1_SPWR"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + gpio =3D <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us =3D <3480>; + }; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + nvmem-cells =3D <&fec_mac1>; + nvmem-cell-names =3D "mac-address"; + snps,reset-gpios =3D <&pca6416_1 2 GPIO_ACTIVE_LOW>; + snps,reset-delays-us =3D <10 20 200000>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + eee-broken-1000t; + qca,disable-smarteee; + vddio-supply =3D <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + }; + }; +}; + +/* + * fec1 shares the some PINs with usdhc2. + * by default usdhc2 is enabled in this dts. + * Please disable usdhc2 to enable fec1 + */ +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec1>; + phy-mode =3D "rgmii-txid"; + phy-handle =3D <ðphy1>; + fsl,magic-packet; + rx-internal-delay-ps =3D <2000>; + nvmem-cells =3D <&fec_mac0>; + nvmem-cell-names =3D "mac-address"; + status =3D "disabled"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pca6416_1 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + qca,disable-smarteee; + vddio-supply =3D <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + }; + }; +}; + +&i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + status =3D "okay"; + + pca6416_1: gpio@20 { + compatible =3D "ti,tca6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + pca6416_2: gpio@21 { + compatible =3D "ti,tca6416"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + pca9548_1: i2c-mux@70 { + compatible =3D "nxp,pca9548"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0>; + + max7322: gpio@68 { + compatible =3D "maxim,max7322"; + reg =3D <0x68>; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; + }; + + i2c@4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x4>; + }; + + i2c@5 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x5>; + }; + + i2c@6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x6>; + }; + }; +}; + +&lpuart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart0>; + status =3D "okay"; +}; + +&lsio_gpio4 { + status =3D "okay"; +}; + +&lsio_gpio5 { + status =3D "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive =3D <250>; + polling-delay =3D <2000>; + thermal-sensors =3D <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + pmic_crit0: trip1 { + temperature =3D <125000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&pmic_alert0>; + cooling-device =3D + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + bus-width =3D <8>; + no-sd; + no-sdio; + non-removable; + status =3D "okay"; +}; + +&usdhc2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width =3D <4>; + vmmc-supply =3D <®_usdhc2_vmmc>; + cd-gpios =3D <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios =3D <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 + IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins =3D < + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins =3D < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins =3D < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins =3D < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + pinctrl_cm40_lpuart: cm40lpuartgrp { + fsl,pins =3D < + IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 + IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins =3D < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; --=20 2.25.1 From nobody Mon Apr 6 14:10:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B3D9ECAAD5 for ; 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charset="utf-8" The ddr-pmu on i.mx8dxl has a different interrupt number. Add a node label to ddr-pmu so that it could be referred and changed in i.mx8dxl dts. Signed-off-by: Shenwei Wang --- arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/bo= ot/dts/freescale/imx8-ss-ddr.dtsi index 8b5cad4e2700..7d5183c6c5be 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi @@ -10,7 +10,7 @@ ddr_subsys: bus@5c000000 { #size-cells =3D <1>; ranges =3D <0x5c000000 0x0 0x5c000000 0x1000000>; =20 - ddr-pmu@5c020000 { + ddr_pmu0: ddr-pmu@5c020000 { compatible =3D "fsl,imx8-ddr-pmu"; reg =3D <0x5c020000 0x10000>; interrupts =3D ; --=20 2.25.1 From nobody Mon Apr 6 14:10:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FF6DECAAD5 for ; Tue, 6 Sep 2022 14:37:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238402AbiIFOhs (ORCPT ); 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charset="utf-8" i.MX8DXL is a device targeting the automotive and industrial market segments. The chip is designed to achieve both high performance and low power consumption. It has a dual (2x) Cortex-A35 processor. This patch adds the basic support for i.MX8DXL SoC. Signed-off-by: Shenwei Wang --- .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 52 ++++ .../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 142 +++++++++++ .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 9 + .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 74 ++++++ arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 238 ++++++++++++++++++ 5 files changed, 515 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8dxl-ss-adma.dtsi new file mode 100644 index 000000000000..795d1d472fae --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +&audio_ipg_clk { + clock-frequency =3D <160000000>; +}; + +&dma_ipg_clk { + clock-frequency =3D <160000000>; +}; + +&i2c0 { + compatible =3D "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi= 2c"; + interrupts =3D ; +}; + +&i2c1 { + compatible =3D "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi= 2c"; + interrupts =3D ; +}; + +&i2c2 { + compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts =3D ; +}; + +&i2c3 { + compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + interrupts =3D ; +}; + +&lpuart0 { + compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts =3D ; +}; + +&lpuart1 { + compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts =3D ; +}; + +&lpuart2 { + compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts =3D ; +}; + +&lpuart3 { + compatible =3D "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + interrupts =3D ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8dxl-ss-conn.dtsi new file mode 100644 index 000000000000..69c4849f2132 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +/delete-node/ &enet1_lpcg; +/delete-node/ &fec2; + +&conn_subsys { + conn_enet0_root_clk: clock-conn-enet0-root { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <250000000>; + clock-output-names =3D "conn_enet0_root_clk"; + }; + + eqos: ethernet@5b050000 { + compatible =3D "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; + reg =3D <0x5b050000 0x10000>; + interrupt-parent =3D <&gic>; + interrupts =3D , + ; + interrupt-names =3D "eth_wake_irq", "macirq"; + clocks =3D <&eqos_lpcg IMX_LPCG_CLK_4>, + <&eqos_lpcg IMX_LPCG_CLK_6>, + <&eqos_lpcg IMX_LPCG_CLK_0>, + <&eqos_lpcg IMX_LPCG_CLK_5>, + <&eqos_lpcg IMX_LPCG_CLK_2>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks =3D <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates =3D <125000000>; + power-domains =3D <&pd IMX_SC_R_ENET_1>; + status =3D "disabled"; + }; + + usbotg2: usb@5b0e0000 { + compatible =3D "fsl,imx8dxl-usb", "fsl,imx7ulp-usb"; + reg =3D <0x5b0e0000 0x200>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + fsl,usbphy =3D <&usbphy2>; + fsl,usbmisc =3D <&usbmisc2 0>; + /* + * usbotg1 and usbotg2 share one clcok. + * scu firmware disables the access to the clock and keeps + * it always on in case other core (M4) uses one of these. + */ + clocks =3D <&clk_dummy>; + ahb-burst-config =3D <0x0>; + tx-burst-size-dword =3D <0x10>; + rx-burst-size-dword =3D <0x10>; + #stream-id-cells =3D <1>; + power-domains =3D <&pd IMX_SC_R_USB_1>; + status =3D "disabled"; + + clk_dummy: clock-dummy { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + clock-output-names =3D "clk_dummy"; + }; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells =3D <1>; + compatible =3D "fsl,imx7ulp-usbmisc"; + reg =3D <0x5b0e0200 0x200>; + }; + + usbphy2: usbphy@0x5b110000 { + compatible =3D "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; + reg =3D <0x5b110000 0x1000>; + clocks =3D <&usb2_2_lpcg IMX_LPCG_CLK_7>; + power-domains =3D <&pd IMX_SC_R_USB_1_PHY>; + status =3D "disabled"; + }; + + eqos_lpcg: clock-controller@5b240000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x5b240000 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>; + clock-indices =3D , , + , , + ; + clock-output-names =3D "eqos_ptp", + "eqos_mem_clk", + "eqos_aclk", + "eqos_clk", + "eqos_csr_clk"; + power-domains =3D <&pd IMX_SC_R_ENET_1>; + }; + + usb2_2_lpcg: clock-controller@5b280000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x5b280000 0x10000>; + #clock-cells =3D <1>; + clock-indices =3D ; + clocks =3D <&conn_ipg_clk>; + clock-output-names =3D "usboh3_2_phy_ipg_clk"; + power-domains =3D <&pd IMX_SC_R_USB_1_PHY>; + }; + +}; + +&enet0_lpcg { + clocks =3D <&conn_enet0_root_clk>, + <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; +}; + +&fec1 { + compatible =3D "fsl,imx8qm-fec"; + interrupts =3D , + , + , + ; + assigned-clocks =3D <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; + assigned-clock-rates =3D <125000000>; +}; + +&usdhc1 { + compatible =3D "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; + interrupts =3D ; +}; + +&usdhc2 { + compatible =3D "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; + interrupts =3D ; +}; + +&usdhc3 { + compatible =3D "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; + interrupts =3D ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64= /boot/dts/freescale/imx8dxl-ss-ddr.dtsi new file mode 100644 index 000000000000..550f513708d8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +&ddr_pmu0 { + compatible =3D "fsl,imx8-ddr-pmu"; + interrupts =3D ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8dxl-ss-lsio.dtsi new file mode 100644 index 000000000000..815bd987b09b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +&lsio_gpio0 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio1 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio2 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio3 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio4 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio5 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio6 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_gpio7 { + compatible =3D "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; + interrupts =3D ; +}; + +&lsio_mu0 { + compatible =3D "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu1 { + compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu2 { + compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu3 { + compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu4 { + compatible =3D "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; + +&lsio_mu5 { + compatible =3D "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + interrupts =3D ; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/d= ts/freescale/imx8dxl.dtsi new file mode 100644 index 000000000000..5ddbda0b4def --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + ethernet0 =3D &fec1; + ethernet1 =3D &eqos; + gpio0 =3D &lsio_gpio0; + gpio1 =3D &lsio_gpio1; + gpio2 =3D &lsio_gpio2; + gpio3 =3D &lsio_gpio3; + gpio4 =3D &lsio_gpio4; + gpio5 =3D &lsio_gpio5; + gpio6 =3D &lsio_gpio6; + gpio7 =3D &lsio_gpio7; + mu1 =3D &lsio_mu1; + }; + + cpus: cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + /* We have 1 clusters with 2 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&A35_L2>; + clocks =3D <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&a35_opp_table>; + }; + + A35_1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + next-level-cache =3D <&A35_L2>; + clocks =3D <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; + #cooling-cells =3D <2>; + operating-points-v2 =3D <&a35_opp_table>; + }; + + A35_L2: l2-cache0 { + compatible =3D "cache"; + }; + }; + + a35_opp_table: opp-table { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <150000>; + }; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <1100000>; + clock-latency-ns =3D <150000>; + opp-suspend; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + dsp_reserved: dsp@92400000 { + reg =3D <0 0x92400000 0 0x2000000>; + no-map; + }; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + system-controller { + compatible =3D "fsl,imx-scu"; + mbox-names =3D "tx0", + "rx0", + "gip3"; + mboxes =3D <&lsio_mu1 0 0 + &lsio_mu1 1 0 + &lsio_mu1 3 3>; + + pd: power-controller { + compatible =3D "fsl,scu-pd"; + #power-domain-cells =3D <1>; + wakeup-irq =3D <160 163 235 236 237 228 229 230 231 238 + 239 240 166 169>; + }; + + clk: clock-controller { + compatible =3D "fsl,imx8dxl-clk", "fsl,scu-clk"; + #clock-cells =3D <2>; + clocks =3D <&xtal32k &xtal24m>; + clock-names =3D "xtal_32KHz", "xtal_24Mhz"; + }; + + iomuxc: pinctrl { + compatible =3D "fsl,imx8dxl-iomuxc"; + }; + + ocotp: ocotp { + compatible =3D "fsl,imx8qxp-scu-ocotp"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + fec_mac0: mac@2c4 { + reg =3D <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg =3D <0x2c6 6>; + }; + }; + + rtc: rtc { + compatible =3D "fsl,imx8qxp-sc-rtc"; + }; + + sc_pwrkey: keys { + compatible =3D "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; + linux,keycode =3D ; + wakeup-source; + }; + + watchdog { + compatible =3D "fsl,imx-sc-wdt"; + timeout-sec =3D <60>; + }; + + tsens: thermal-sensor { + compatible =3D "fsl,imx-sc-thermal"; + #thermal-sensor-cells =3D <1>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + thermal_zones: thermal-zones { + cpu-thermal0 { + polling-delay-passive =3D <250>; + polling-delay =3D <2000>; + thermal-sensors =3D <&tsens IMX_SC_R_SYSTEM>; + + trips { + cpu_alert0: trip0 { + temperature =3D <107000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu_crit0: trip1 { + temperature =3D <127000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_alert0>; + cooling-device =3D + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + /* The two values below cannot be changed by the board */ + xtal32k: clock-xtal32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "xtal_32KHz"; + }; + + xtal24m: clock-xtal24m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "xtal_24MHz"; + }; + + /* sorted in register address */ + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" + #include "imx8-ss-lsio.dtsi" +}; + +#include "imx8dxl-ss-adma.dtsi" +#include "imx8dxl-ss-conn.dtsi" +#include "imx8dxl-ss-lsio.dtsi" +#include "imx8dxl-ss-ddr.dtsi" --=20 2.25.1 From nobody Mon Apr 6 14:10:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20434ECAAD5 for ; Tue, 6 Sep 2022 14:39:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234668AbiIFOj1 (ORCPT ); Tue, 6 Sep 2022 10:39:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242094AbiIFOiH (ORCPT ); Tue, 6 Sep 2022 10:38:07 -0400 Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2061f.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe1a::61f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCF3E7E00E; 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Tue, 6 Sep 2022 13:55:51 +0000 From: Shenwei Wang To: Rob Herring , Sascha Hauer , Fabio Estevam , Denys Drozdov Cc: Krzysztof Kozlowski , Shawn Guo , Pengutronix Kernel Team , NXP Linux Team , Marcel Ziswiler , Alexander Stein , Marek Vasut , Max Krummenacher , Matthias Schiffer , Tim Harvey , Vladimir Oltean , Peng Fan , Alex Marginean , Reinhold Mueller , Shenwei Wang , Viorel Suman , Abel Vesa , Ming Qian , Li Yang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev Subject: [PATCH v7 5/5] arm64: dts: freescale: add support for i.MX8DXL EVK board Date: Tue, 6 Sep 2022 08:53:45 -0500 Message-Id: <20220906135345.38345-9-shenwei.wang@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906135345.38345-1-shenwei.wang@nxp.com> References: <20220906135345.38345-1-shenwei.wang@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY5PR04CA0008.namprd04.prod.outlook.com (2603:10b6:a03:1d0::18) To PAXPR04MB9185.eurprd04.prod.outlook.com (2603:10a6:102:231::11) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 72ce3571-a959-4fae-18ab-08da900f823d X-MS-TrafficTypeDiagnostic: VI1PR04MB5181:EE_ X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" This is to support the EVK (Evaluation Kit Board) for the i.MX8DXL. The patch has enabled the serial console, SD/EMMC interface, and the eqos and fec ethernet network. Signed-off-by: Shenwei Wang --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 426 ++++++++++++++++++ 2 files changed, 427 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 8bf7f7ecebaa..2741205efe84 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) +=3D fsl-ls1028a-qds-85bb.d= tb dtb-$(CONFIG_ARCH_LAYERSCAPE) +=3D fsl-ls1028a-qds-899b.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) +=3D fsl-ls1028a-qds-9999.dtb =20 +dtb-$(CONFIG_ARCH_MXC) +=3D imx8dxl-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-ddr4-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boo= t/dts/freescale/imx8dxl-evk.dts new file mode 100644 index 000000000000..868c75945af3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020, 2022 NXP + */ + +/dts-v1/; + +#include "imx8dxl.dtsi" + +/ { + model =3D "Freescale i.MX8DXL EVK"; + compatible =3D "fsl,imx8dxl-evk", "fsl,imx8dxl"; + + aliases { + i2c2 =3D &i2c2; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + serial0 =3D &lpuart0; + }; + + chosen { + stdout-path =3D &lpuart0; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00000000 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * Memory reserved for optee usage. Please do not use. + * This will be automatically added to dtb if OP-TEE is installed. + * optee@96000000 { + * reg =3D <0 0x96000000 0 0x2000000>; + * no-map; + * }; + */ + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0 0x14000000>; + alloc-ranges =3D <0 0x98000000 0 0x14000000>; + linux,cma-default; + }; + }; + + mux3_en: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "mux3_en"; + gpio =3D <&pca6416_2 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + reg_fec1_sel: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fec1_supply"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + regulator-always-on; + status =3D "disabled"; + }; + + reg_fec1_io: regulator-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fec1_io_supply"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + gpio =3D <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + status =3D "disabled"; + }; + + reg_usdhc2_vmmc: regulator-3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "SD1_SPWR"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + gpio =3D <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us =3D <3480>; + }; +}; + +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + nvmem-cells =3D <&fec_mac1>; + nvmem-cell-names =3D "mac-address"; + snps,reset-gpios =3D <&pca6416_1 2 GPIO_ACTIVE_LOW>; + snps,reset-delays-us =3D <10 20 200000>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + eee-broken-1000t; + qca,disable-smarteee; + vddio-supply =3D <&vddio0>; + + vddio0: vddio-regulator { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + }; + }; +}; + +/* + * fec1 shares the some PINs with usdhc2. + * by default usdhc2 is enabled in this dts. + * Please disable usdhc2 to enable fec1 + */ +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec1>; + phy-mode =3D "rgmii-txid"; + phy-handle =3D <ðphy1>; + fsl,magic-packet; + rx-internal-delay-ps =3D <2000>; + nvmem-cells =3D <&fec_mac0>; + nvmem-cell-names =3D "mac-address"; + status =3D "disabled"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pca6416_1 0 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + qca,disable-smarteee; + vddio-supply =3D <&vddio1>; + + vddio1: vddio-regulator { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + }; + }; +}; + +&i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + status =3D "okay"; + + pca6416_1: gpio@20 { + compatible =3D "ti,tca6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + pca6416_2: gpio@21 { + compatible =3D "ti,tca6416"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + pca9548_1: i2c-mux@70 { + compatible =3D "nxp,pca9548"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0>; + + max7322: gpio@68 { + compatible =3D "maxim,max7322"; + reg =3D <0x68>; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; + }; + + i2c@4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x4>; + }; + + i2c@5 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x5>; + }; + + i2c@6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x6>; + }; + }; +}; + +&lpuart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart0>; + status =3D "okay"; +}; + +&lsio_gpio4 { + status =3D "okay"; +}; + +&lsio_gpio5 { + status =3D "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive =3D <250>; + polling-delay =3D <2000>; + thermal-sensors =3D <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + pmic_crit0: trip1 { + temperature =3D <125000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&pmic_alert0>; + cooling-device =3D + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + bus-width =3D <8>; + no-sd; + no-sdio; + non-removable; + status =3D "okay"; +}; + +&usdhc2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width =3D <4>; + vmmc-supply =3D <®_usdhc2_vmmc>; + cd-gpios =3D <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios =3D <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 + IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c + IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins =3D < + IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins =3D < + IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 + IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 + IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 + IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 + IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 + IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 + IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 + IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 + IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 + IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 + IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 + IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins =3D < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins =3D < + IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 + IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 + IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 + IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + >; + }; + + pinctrl_cm40_lpuart: cm40lpuartgrp { + fsl,pins =3D < + IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 + IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins =3D < + IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 + IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ + IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +}; --=20 2.25.1