From nobody Mon Apr 6 17:06:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A288CECAAD3 for ; Mon, 5 Sep 2022 11:10:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238233AbiIELKu (ORCPT ); Mon, 5 Sep 2022 07:10:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236361AbiIELKq (ORCPT ); Mon, 5 Sep 2022 07:10:46 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB122543E2 for ; Mon, 5 Sep 2022 04:10:43 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oV9zw-0005hc-TA; Mon, 05 Sep 2022 13:10:36 +0200 From: Heiko Stuebner To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: guoren@kernel.org, apatel@ventanamicro.com, atishp@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner , Conor Dooley , Andrew Jones Subject: [PATCH v2 1/5] riscv: cleanup svpbmt cpufeature probing Date: Mon, 5 Sep 2022 13:10:23 +0200 Message-Id: <20220905111027.2463297-2-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220905111027.2463297-1-heiko@sntech.de> References: <20220905111027.2463297-1-heiko@sntech.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For better readability (and compile time coverage) use IS_ENABLED instead of ifdef and drop the new unneeded switch statement. Signed-off-by: Heiko Stuebner Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 553d755483ed..764ea220161f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void) #ifdef CONFIG_RISCV_ALTERNATIVE static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) { -#ifdef CONFIG_RISCV_ISA_SVPBMT - switch (stage) { - case RISCV_ALTERNATIVES_EARLY_BOOT: + if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT)) return false; - default: - return riscv_isa_extension_available(NULL, SVPBMT); - } -#endif =20 - return false; + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return false; + + return riscv_isa_extension_available(NULL, SVPBMT); } =20 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) --=20 2.35.1 From nobody Mon Apr 6 17:06:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52C78ECAAD5 for ; Mon, 5 Sep 2022 11:11:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238278AbiIELLH (ORCPT ); Mon, 5 Sep 2022 07:11:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236989AbiIELKq (ORCPT ); Mon, 5 Sep 2022 07:10:46 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 576785A2EB for ; Mon, 5 Sep 2022 04:10:44 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oV9zx-0005hc-9Q; Mon, 05 Sep 2022 13:10:37 +0200 From: Heiko Stuebner To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: guoren@kernel.org, apatel@ventanamicro.com, atishp@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner , Conor Dooley , Andrew Jones Subject: [PATCH v2 2/5] riscv: drop some idefs from CMO initialization Date: Mon, 5 Sep 2022 13:10:24 +0200 Message-Id: <20220905111027.2463297-3-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220905111027.2463297-1-heiko@sntech.de> References: <20220905111027.2463297-1-heiko@sntech.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Wrapping things in #ifdefs makes the code harder to read while we also have IS_ENABLED() macros to do this in regular code and the extension detection is not _that_ runtime critical. So define a stub for riscv_noncoherent_supported() in the non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to us IS_ENABLED. Suggested-by: Conor Dooley Signed-off-by: Heiko Stuebner Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/errata/thead/errata.c | 7 +++---- arch/riscv/include/asm/cacheflush.h | 2 ++ arch/riscv/kernel/cpufeature.c | 22 +++++++++------------- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index 202c83f677b2..bffa711aaf64 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage, static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id, unsigned long impid) { -#ifdef CONFIG_ERRATA_THEAD_CMO + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO)) + return false; + if (arch_id !=3D 0 || impid !=3D 0) return false; =20 @@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage, =20 riscv_noncoherent_supported(); return true; -#else - return false; -#endif } =20 static u32 thead_errata_probe(unsigned int stage, diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/c= acheflush.h index a60acaecfeda..4363d0beb38a 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { } =20 #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); +#else +static inline void riscv_noncoherent_supported(void) {} #endif =20 /* diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 764ea220161f..729f7a218093 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(= unsigned int stage) =20 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) { -#ifdef CONFIG_RISCV_ISA_ZICBOM - switch (stage) { - case RISCV_ALTERNATIVES_EARLY_BOOT: + if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM)) + return false; + + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return false; + + if (!riscv_isa_extension_available(NULL, ZICBOM)) return false; - default: - if (riscv_isa_extension_available(NULL, ZICBOM)) { - riscv_noncoherent_supported(); - return true; - } else { - return false; - } - } -#endif =20 - return false; + riscv_noncoherent_supported(); + return true; } =20 /* --=20 2.35.1 From nobody Mon Apr 6 17:06:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19681ECAAD5 for ; Mon, 5 Sep 2022 11:11:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238257AbiIELLC (ORCPT ); Mon, 5 Sep 2022 07:11:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236714AbiIELKq (ORCPT ); Mon, 5 Sep 2022 07:10:46 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 506475A3D5 for ; Mon, 5 Sep 2022 04:10:45 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oV9zx-0005hc-Lt; Mon, 05 Sep 2022 13:10:37 +0200 From: Heiko Stuebner To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: guoren@kernel.org, apatel@ventanamicro.com, atishp@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner , Conor Dooley , Andrew Jones Subject: [PATCH v2 3/5] riscv: use BIT() macros in t-head errata init Date: Mon, 5 Sep 2022 13:10:25 +0200 Message-Id: <20220905111027.2463297-4-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220905111027.2463297-1-heiko@sntech.de> References: <20220905111027.2463297-1-heiko@sntech.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using the appropriate BIT macro makes the code better readable. Suggested-by: Conor Dooley Signed-off-by: Heiko Stuebner Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/errata/thead/errata.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index bffa711aaf64..a6f4bd8ccf3f 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -49,10 +49,10 @@ static u32 thead_errata_probe(unsigned int stage, u32 cpu_req_errata =3D 0; =20 if (errata_probe_pbmt(stage, archid, impid)) - cpu_req_errata |=3D (1U << ERRATA_THEAD_PBMT); + cpu_req_errata |=3D BIT(ERRATA_THEAD_PBMT); =20 if (errata_probe_cmo(stage, archid, impid)) - cpu_req_errata |=3D (1U << ERRATA_THEAD_CMO); + cpu_req_errata |=3D BIT(ERRATA_THEAD_CMO); =20 return cpu_req_errata; } --=20 2.35.1 From nobody Mon Apr 6 17:06:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A4CFECAAD3 for ; Mon, 5 Sep 2022 11:11:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238247AbiIELLE (ORCPT ); Mon, 5 Sep 2022 07:11:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237459AbiIELKr (ORCPT ); Mon, 5 Sep 2022 07:10:47 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A7FC5A3E3 for ; Mon, 5 Sep 2022 04:10:45 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oV9zy-0005hc-23; Mon, 05 Sep 2022 13:10:38 +0200 From: Heiko Stuebner To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: guoren@kernel.org, apatel@ventanamicro.com, atishp@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner , Conor Dooley Subject: [PATCH v2 4/5] riscv: use BIT() marco for cpufeature probing Date: Mon, 5 Sep 2022 13:10:26 +0200 Message-Id: <20220905111027.2463297-5-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220905111027.2463297-1-heiko@sntech.de> References: <20220905111027.2463297-1-heiko@sntech.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using the appropriate BIT macro makes the code better readable. Suggested-by: Conor Dooley Signed-off-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 729f7a218093..08f7445985dc 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -289,10 +289,10 @@ static u32 __init_or_module cpufeature_probe(unsigned= int stage) u32 cpu_req_feature =3D 0; =20 if (cpufeature_probe_svpbmt(stage)) - cpu_req_feature |=3D (1U << CPUFEATURE_SVPBMT); + cpu_req_feature |=3D BIT(CPUFEATURE_SVPBMT); =20 if (cpufeature_probe_zicbom(stage)) - cpu_req_feature |=3D (1U << CPUFEATURE_ZICBOM); + cpu_req_feature |=3D BIT(CPUFEATURE_ZICBOM); =20 return cpu_req_feature; } --=20 2.35.1 From nobody Mon Apr 6 17:06:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 239BBECAAD5 for ; Mon, 5 Sep 2022 11:11:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238245AbiIELK6 (ORCPT ); Mon, 5 Sep 2022 07:10:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236681AbiIELKq (ORCPT ); Mon, 5 Sep 2022 07:10:46 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57B8D5A2F8 for ; Mon, 5 Sep 2022 04:10:44 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oV9zy-0005hc-Ea; Mon, 05 Sep 2022 13:10:38 +0200 From: Heiko Stuebner To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: guoren@kernel.org, apatel@ventanamicro.com, atishp@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner , Conor Dooley , Andrew Jones Subject: [PATCH v2 5/5] riscv: check for kernel config option in t-head memory types errata Date: Mon, 5 Sep 2022 13:10:27 +0200 Message-Id: <20220905111027.2463297-6-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220905111027.2463297-1-heiko@sntech.de> References: <20220905111027.2463297-1-heiko@sntech.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The t-head variant of page-based memory types should also check first for the enabled kernel config option. Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head") Signed-off-by: Heiko Stuebner Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones Reviewed-by: Guo Ren --- arch/riscv/errata/thead/errata.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index a6f4bd8ccf3f..902e12452821 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -17,6 +17,9 @@ static bool errata_probe_pbmt(unsigned int stage, unsigned long arch_id, unsigned long impid) { + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)) + return false; + if (arch_id !=3D 0 || impid !=3D 0) return false; =20 --=20 2.35.1