From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF488ECAAD5 for ; Mon, 5 Sep 2022 10:04:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236358AbiIEKEs (ORCPT ); Mon, 5 Sep 2022 06:04:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236697AbiIEKEf (ORCPT ); Mon, 5 Sep 2022 06:04:35 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 278FBA46E; Mon, 5 Sep 2022 03:04:31 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BF3096601EB2; Mon, 5 Sep 2022 11:04:28 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372269; bh=0o/8cVorzOsad5b/Haf5ctcd6DYaAoupPjEfo3dU2RU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OGVQ3Ml3T4lAOa68aT4JDgIxSTwC1eI44hZrH7/OCGO2HSKIX7OELWDA7NH9ftF6i GWFr/Cx6ryk1u40MQLuHoayS3N60MUUnXLZOsflnLq1jt5MNjx2YUJD9RAbfEeIMaB gJojvM24V98KSbpCqjYtsHWEkf/mdkoirvJZX5SXb9OsheLdZxqSZzpArgyBtZqdM2 Kzvw+2VnGTCzRHTt1ZHXTSpdFE5jpW38cpR4za3fCvSTyJVcliIwTrHaaMwkqNSGLT HcLghPpEVG1xg9WbqKLEgtJEruFi/0StTBo3TBnhWvf9cczzUF73OCTZgFb38JMvMG cjWbIGaJyKXXw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 01/10] arm64: dts: mt8183: Fix Mali GPU clock Date: Mon, 5 Sep 2022 12:04:07 +0200 Message-Id: <20220905100416.42421-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The actual clock feeding into the Mali GPU on the MT8183 is from the clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN block, which itself is simply a pass-through placeholder for the MFGPLL in the APMIXEDSYS block. Fix the hardware description with the correct clock reference. Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index a70b669c49ba..402136bfd535 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1678,7 +1678,7 @@ gpu: gpu@13040000 { ; interrupt-names =3D "job", "mmu", "gpu"; =20 - clocks =3D <&topckgen CLK_TOP_MFGPLL_CK>; + clocks =3D <&mfgcfg CLK_MFG_BG3D>; =20 power-domains =3D <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F8C9C6FA92 for ; Mon, 5 Sep 2022 10:04:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236681AbiIEKEi (ORCPT ); Mon, 5 Sep 2022 06:04:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236756AbiIEKEf (ORCPT ); Mon, 5 Sep 2022 06:04:35 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27B85AE67; Mon, 5 Sep 2022 03:04:32 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E31566601EB9; Mon, 5 Sep 2022 11:04:29 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372270; bh=7wZZwX2byJ4bhuDUY3CPvHNsdJ6p7fqNLcyFmuOhg2o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ELergRBx8+RjDDAewBaOrNDUgYy8kTWLlARjWjWu9MXGIfroupTcA6RqUMft7bD6h BKckz5H0mz3pXYY7HNAnupWDCdg6UdBtaKuNYshFbEKtSXf1bVNdP4rngSaKAon/+J Eh4ym355pzWyT6z6U8gVuLs3allJ+HL5Yo12b+B4IkIA9gEXe4o4HomNWxsvSCCCR4 KfiAtRbF9HudKuOU8n84hLgqHSJ9aqW0P7WMLvhnlvUFaBXliWfuZe/f2uDOwsn3ic TAhEFV6DNMxt120k1nHysYP+un8rgj6y5L4WWvMAtU33OwsP8+sZ2Fi1EvWVgmE2t+ Di/hPXhV+GQBQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 02/10] clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent Date: Mon, 5 Sep 2022 12:04:08 +0200 Message-Id: <20220905100416.42421-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its rate change requests to its parent, so that DVFS for the GPU can work properly. Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8183-mfgcfg.c index d774edaf760b..230299728859 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -18,9 +18,9 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_MFG(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \ - &mtk_clk_gate_ops_setclr) +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT) =20 static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0) --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 277E6C6FA89 for ; Mon, 5 Sep 2022 10:04:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235938AbiIEKEw (ORCPT ); Mon, 5 Sep 2022 06:04:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237224AbiIEKEf (ORCPT ); Mon, 5 Sep 2022 06:04:35 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E8419583; Mon, 5 Sep 2022 03:04:33 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 169C46600387; Mon, 5 Sep 2022 11:04:31 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372272; bh=qaQvontPdR6dYG14J9SYCmNFY7aA784tPs6Sq54Bz+Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ah4ybDU0pMH+CCQ0RDiNV8OVk4YDr3ek39igjKegO+0goNMBEMoj2p7PBmSt6XIeP xxbw87Jgex6YLF3NOX56omlGRbSJdaffixuK+rNdHwI0V0popNnz6+S2izO7nZVuiI iIl2ZmdP3KUHLM5UdY31Jf5pt40bLvAOqx9sZ53exgHI/Ssxv18eF5ZYiXgjI03RaM W2dDXAyWOGD/DhA/Q/PUSwzLQmkdc2EOY49IE0OjhusXxbGobHTODR38daOh9gq6Y6 KncwraZP559/O5sI1XnvoentchuL2M1Npalt+1Iq4w+0RdTzWPRQAcspdxXdwIHtTL 6sjK9iu8V558w== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 03/10] clk: mediatek: mux: add clk notifier functions Date: Mon, 5 Sep 2022 12:04:09 +0200 Message-Id: <20220905100416.42421-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai With device frequency scaling, the mux clock that (indirectly) feeds the device selects between a dedicated PLL, and some other stable clocks. When a clk rate change is requested, the (normally) upstream PLL is reconfigured. It's possible for the clock output of the PLL to become unstable during this process. To avoid causing the device to glitch, the mux should temporarily be switched over to another "stable" clock during the PLL rate change. This is done with clk notifiers. This patch adds common functions for notifiers to temporarily and transparently reparent mux clocks. This was loosely based on commit 8adfb08605a9 ("clk: sunxi-ng: mux: Add clk notifier functions"). Signed-off-by: Chen-Yu Tsai [Angelo: Changed mtk_mux_nb to hold a pointer to clk_ops instead of mtk_mux] Co-Developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen --- drivers/clk/mediatek/clk-mux.c | 38 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mux.h | 15 ++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index cd5f9fd8cb98..4421e4859257 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -4,6 +4,7 @@ * Author: Owen Chen */ =20 +#include #include #include #include @@ -259,4 +260,41 @@ void mtk_clk_unregister_muxes(const struct mtk_mux *mu= xes, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_muxes); =20 +/* + * This clock notifier is called when the frequency of the parent + * PLL clock is to be changed. The idea is to switch the parent to a + * stable clock, such as the main oscillator, while the PLL frequency + * stabilizes. + */ +static int mtk_clk_mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *_data) +{ + struct clk_notifier_data *data =3D _data; + struct clk_hw *hw =3D __clk_get_hw(data->clk); + struct mtk_mux_nb *mux_nb =3D to_mtk_mux_nb(nb); + int ret =3D 0; + + switch (event) { + case PRE_RATE_CHANGE: + mux_nb->original_index =3D mux_nb->ops->get_parent(hw); + ret =3D mux_nb->ops->set_parent(hw, mux_nb->bypass_index); + break; + case POST_RATE_CHANGE: + case ABORT_RATE_CHANGE: + ret =3D mux_nb->ops->set_parent(hw, mux_nb->original_index); + break; + } + + return notifier_from_errno(ret); +} + +int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk, + struct mtk_mux_nb *mux_nb) +{ + mux_nb->nb.notifier_call =3D mtk_clk_mux_notifier_cb; + + return devm_clk_notifier_register(dev, clk, &mux_nb->nb); +} +EXPORT_SYMBOL_GPL(devm_mtk_clk_mux_notifier_register); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 6539c58f5d7d..83ff420f4ebe 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -7,12 +7,14 @@ #ifndef __DRV_CLK_MTK_MUX_H #define __DRV_CLK_MTK_MUX_H =20 +#include #include #include =20 struct clk; struct clk_hw_onecell_data; struct clk_ops; +struct device; struct device_node; =20 struct mtk_mux { @@ -89,4 +91,17 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num, struct clk_hw_onecell_data *clk_data); =20 +struct mtk_mux_nb { + struct notifier_block nb; + const struct clk_ops *ops; + + u8 bypass_index; /* Which parent to temporarily use */ + u8 original_index; /* Set by notifier callback */ +}; + +#define to_mtk_mux_nb(_nb) container_of(_nb, struct mtk_mux_nb, nb) + +int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk, + struct mtk_mux_nb *mux_nb); + #endif /* __DRV_CLK_MTK_MUX_H */ --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 105DEECAAD5 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372273; bh=l1SF2PmZfdVIE4WIRvO2pwfEBey+ctqacrXwPbyX+3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UUAbSkuNJLKlEk1wjkd0ZYIzaeBbPS69TkLOnDUqYI3jRTlK4uI/OuzCBO3KnDkyI tT24WHtYchXsVLL2LCzbrixgB5VvLmZAjjMqIdfHPgbESRRUc4OW9B7ViqEGgBbY0o de0ZXOQMHKLcKlARfjlQJYk58G7snzbdnFscheKWUUsapCKgkHK5rbi491Y+tYwPV7 +XEmbCjDQgqlIp5El/kgEMv8FqRQIXS67ixOAb/nPS0yLPFsRvqVzVp1rVCyY1SJOv kdKqoJEq/afeB3usAWsal96U/fmkJ4hFrlGfVhgZuvuvIGa6frHbXFuAnQNmP+A99g ISaGgMPPH67ZA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 04/10] clk: mediatek: mt8183: Add clk mux notifier for MFG mux Date: Mon, 5 Sep 2022 12:04:10 +0200 Message-Id: <20220905100416.42421-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai When the MFG PLL clock, which is upstream of the MFG clock, is changed, the downstream clock and consumers need to be switched away from the PLL over to a stable clock to avoid glitches. This is done through the use of the newly added clk mux notifier. The notifier is set on the mux itself instead of the upstream PLL, but in practice this works, as the rate change notifitcations are propogated throughout the sub-tree hanging off the PLL. Just before rate changes, the MFG mux is temporarily and transparently switched to the 26 MHz main crystal. After the rate change, the mux is switched back. Signed-off-by: Chen-Yu Tsai [Angelo: Rebased to assign clk_ops in mtk_mux_nb] Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen --- drivers/clk/mediatek/clk-mt8183.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 8512101e1189..1860a35a723a 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1198,10 +1198,33 @@ static void clk_mt8183_top_init_early(struct device= _node *node) CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", clk_mt8183_top_init_early); =20 +/* Register mux notifier for MFG mux */ +static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) +{ + struct mtk_mux_nb *mfg_mux_nb; + int i; + + mfg_mux_nb =3D devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(top_muxes); i++) + if (top_muxes[i].id =3D=3D CLK_TOP_MUX_MFG) + break; + if (i =3D=3D ARRAY_SIZE(top_muxes)) + return -EINVAL; + + mfg_mux_nb->ops =3D top_muxes[i].ops; + mfg_mux_nb->bypass_index =3D 0; /* Bypass to 26M crystal */ + + return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); +} + static int clk_mt8183_top_probe(struct platform_device *pdev) { void __iomem *base; struct device_node *node =3D pdev->dev.of_node; + int ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -1227,6 +1250,11 @@ static int clk_mt8183_top_probe(struct platform_devi= ce *pdev) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); =20 + ret =3D clk_mt8183_reg_mfg_mux_notifier(&pdev->dev, + top_clk_data->hws[CLK_TOP_MUX_MFG]->clk); + if (ret) + return ret; + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); } --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BF5CECAAD5 for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1662372274; bh=U0W/o4wRU8Wehp4YXbC2Ill8pHldHdAIiV0c7iykL4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iWqUzhFhTutF6s3qrLWbCYqEQAUXxMIbn0f5K5q8d6uGygu70gYRtAecLWvcufMik 2OkCYNM7mTenStc5me/nDSNAHEYDwaQT8rkLR95LUPJXlb6VaI3GIAHsQcyIpqr4Kp BTuXFyS0tu73/wGMkqtN2i3OIip9BJJNKQBzym67KrEZt0BOIO3P4DPWrJLfGBINVS 1XMVkFJ4juEHRK1jQmXU7gJ/tTmnX1G0k6TjjAs7ukQeBFwcEd5flabLXZEOvGhfVz OBoDiUtEouqBIdrmjwdBkeK2DOAKa+KsaDFOl1GFXvCP2KAhwzkc6lBXAbmZY613wh SnBX19VBBT4OQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 05/10] clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes Date: Mon, 5 Sep 2022 12:04:11 +0200 Message-Id: <20220905100416.42421-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The MFG_BG3D is a gate to enable/disable clock output to the GPU, but the actual output is decided by multiple muxes; in particular: mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and "fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the 26MHz clock and various system PLLs. This also implies that "top_mfg_core_tmp" is a parent of the "mfg_ck_fast_ref" mux (and not vice-versa), so reparent the MFG_BG3D gate to the latter and add the CLK_SET_RATE_PARENT flag to it: this way we ensure propagating rate changes that are requested on MFG_BG3D along its entire clock tree. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8195-mfg.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/c= lk-mt8195-mfg.c index 9411c556a5a9..c94cb71bd9b9 100644 --- a/drivers/clk/mediatek/clk-mt8195-mfg.c +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -17,10 +17,12 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { }; =20 #define GATE_MFG(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \ + _shift, &mtk_clk_gate_ops_setclr, \ + CLK_SET_RATE_PARENT) =20 static const struct mtk_gate mfg_clks[] =3D { - GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg_core_tmp", 0), + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_ck_fast_ref", 0), }; =20 static const struct mtk_clk_desc mfg_desc =3D { --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41C0AECAAD3 for ; Mon, 5 Sep 2022 10:05:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232053AbiIEKFK (ORCPT ); Mon, 5 Sep 2022 06:05:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237386AbiIEKEh (ORCPT ); Mon, 5 Sep 2022 06:04:37 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FB86E0D8; Mon, 5 Sep 2022 03:04:36 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8DB4F6601EE6; Mon, 5 Sep 2022 11:04:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372275; bh=tqzHv7pN26chTkKpPZzEDlhEkywicueCNMzL2GoOwi4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cdjEPflv+e4Pn37eX86oqL0q9VuzNmZNqy+NX/3NmYhdBJ0C/F0vlXmw8ez5BX6Jz snijNvittcaiTL/lTmKaGQ6puw3u4Zo7RUrJv7Ctv9//z9z6eEHxzUncnMSRRK9R6T 9zfiZ6vtTn3UWChG7DlF+HxegwsPd1MB08RmF2NkN4by7SRq/B9OMrewIiEmSiZiYx iHOdmufIzEhXDXEt5k0+6Ok1GOlIH9HcE+u4WmXTbfNgyc/gyD8Qb2/crYKY41DmqY A2kOoHVUGPxSxoJqPHyco2JeHwgPgPhKZchbtWbjpudXe4wE6W5rLX79EPBX3c2nPM NfS5DBl4vmwBg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 06/10] clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux Date: Mon, 5 Sep 2022 12:04:12 +0200 Message-Id: <20220905100416.42421-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This clock was being registered as clk-composite through the helpers for the same in the MediaTek clock APIs but, in reality, this isn't a composite clock. Appropriately register this clock with devm_clk_hw_register_mux(). No functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8195-topckgen.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index ec70e1f65eaf..e1c3ab4e146b 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1149,11 +1149,6 @@ static const struct mtk_mux top_mtk_muxes[] =3D { */ }; =20 -static struct mtk_composite top_muxes[] =3D { - /* CLK_MISC_CFG_3 */ - MUX(CLK_TOP_MFG_CK_FAST_REF, "mfg_ck_fast_ref", mfg_fast_parents, 0x0250,= 8, 1), -}; - static const struct mtk_composite top_adj_divs[] =3D { DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, = 0x0328, 8, 0), DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, = 0x0328, 8, 8), @@ -1226,6 +1221,7 @@ static int clk_mt8195_topck_probe(struct platform_dev= ice *pdev) { struct clk_hw_onecell_data *top_clk_data; struct device_node *node =3D pdev->dev.of_node; + struct clk_hw *hw; int r; void __iomem *base; =20 @@ -1253,15 +1249,17 @@ static int clk_mt8195_topck_probe(struct platform_d= evice *pdev) if (r) goto unregister_factors; =20 - r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8195_clk_lock, top_clk_data); - if (r) + hw =3D devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_p= arents, + ARRAY_SIZE(mfg_fast_parents), CLK_SET_RATE_PARENT, + (base + 0x250), 8, 1, 0, &mt8195_clk_lock); + if (IS_ERR(hw)) goto unregister_muxes; + top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] =3D hw; =20 r =3D mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),= base, &mt8195_clk_lock, top_clk_data); if (r) - goto unregister_composite_muxes; + goto unregister_muxes; =20 r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_cl= k_data); if (r) @@ -1279,8 +1277,6 @@ static int clk_mt8195_topck_probe(struct platform_dev= ice *pdev) mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); unregister_composite_divs: mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top= _clk_data); -unregister_composite_muxes: - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_d= ata); unregister_muxes: mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_cl= k_data); unregister_factors: @@ -1300,7 +1296,6 @@ static int clk_mt8195_topck_remove(struct platform_de= vice *pdev) of_clk_del_provider(node); mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top= _clk_data); - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_d= ata); mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_cl= k_data); mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),= top_clk_data); --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84CD2ECAAD3 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372276; bh=jffXD3T2MOBqqGwvO+kvgVzF9lzP8ZPWA3RUmt8BGfY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NKj4IwwP1ArxiD/Yn9oQYg4/iqAs/lypWASlzcKvephHVC2zKUiLfhBIF7KcxGgcW EhYhy3I/uZzl9gI4YNxMTRGMt7RcIUY3PEUVg1gObWdYkJ4FBj2tz7MQZ2LE81NvT1 yRPjYLdUu88Erff+QYeez/IZJt9Z/40nf0QuhgWs1YbDGhoDpPE3ey7R4HWc2Apj9U gSnVJ2XsTkvkz5Mk/Aj4EwV/W5YFG9VlHZNcMfdRkwl2l6sh91HMIH3MleYly625YY sXfcl7qOEoB/a33DA9EQcTgfS0sBbajzzV5x/C9R92o7+7MuDNXnHpFEtzPNg04XLq Wwv7yxF0QkDfw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 07/10] clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier Date: Mon, 5 Sep 2022 12:04:13 +0200 Message-Id: <20220905100416.42421-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Following the changes done to MT8183, register a similar notifier for MT8195 as well, allowing safe clockrate updates for the MFGPLL. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen --- drivers/clk/mediatek/clk-mt8195-topckgen.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index e1c3ab4e146b..4dde23bece66 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1217,6 +1217,21 @@ static const struct of_device_id of_match_clk_mt8195= _topck[] =3D { {} }; =20 +/* Register mux notifier for MFG mux */ +static int clk_mt8195_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) +{ + struct mtk_mux_nb *mfg_mux_nb; + + mfg_mux_nb =3D devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + mfg_mux_nb->ops =3D &clk_mux_ops; + mfg_mux_nb->bypass_index =3D 0; /* Bypass to TOP_MFG_CORE_TMP */ + + return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); +} + static int clk_mt8195_topck_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *top_clk_data; @@ -1256,6 +1271,11 @@ static int clk_mt8195_topck_probe(struct platform_de= vice *pdev) goto unregister_muxes; top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] =3D hw; =20 + r =3D clk_mt8195_reg_mfg_mux_notifier(&pdev->dev, + top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk); + if (r) + goto unregister_muxes; + r =3D mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),= base, &mt8195_clk_lock, top_clk_data); if (r) --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3001ECAAD3 for ; Mon, 5 Sep 2022 10:05:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235598AbiIEKFV (ORCPT ); Mon, 5 Sep 2022 06:05:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236540AbiIEKEk (ORCPT ); Mon, 5 Sep 2022 06:04:40 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF8DD1055E; Mon, 5 Sep 2022 03:04:38 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D38E26601EEF; Mon, 5 Sep 2022 11:04:36 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372277; bh=lcdJy/SnpyOyR+kPA1esQ+M7lPo2TogPW/5ufGPolmg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XRbb5ODci4V8X2YnR/SXcuVsOlfNvwwz/zzXY4wFJDVk0IjIVuW/IWHfRc0PP/rZY RkheMSUtw0zzstDi+hJBtbGQdkRtFeet6AOsQZspVZz7x0RwDIW/suUY6ukc3UU7Rw yuYtLuQgyblc/cqF3FPWKXUILB4mKVPtdY+HNsNiDRsqtwXix2uE6COvecSZ4PfAvW WSFh14zzOusfzXPQu3OkDPMOdR5LvZU8H0loxAVSY04X4P4I3y2Zfs+RhOpgj2tOpV 6EXaHaMEtNi88Jh0srV3v3ls58I7qypPjdDpnZxBEElNRPXIiKuKYT00fXZFV1J3VU 1ZRTqPk0U217Q== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents Date: Mon, 5 Sep 2022 12:04:14 +0200 Message-Id: <20220905100416.42421-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These PLLs are conflicting with GPU rates that can be generated by the GPU-dedicated MFGPLL and would require a special clock handler to be used, for very little and ignorable power consumption benefits. Also, we're in any case unable to set the rate of these PLLs to something else that is sensible for this task, so simply drop them: this will make the GPU to be clocked exclusively from MFGPLL for "fast" rates, while still achieving the right "safe" rate during PLL frequency locking. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index 4dde23bece66..6ff610c101ae 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -301,8 +301,6 @@ static const char * const ipu_if_parents[] =3D { static const char * const mfg_parents[] =3D { "clk26m", "mainpll_d5_d2", - "univpll_d6", - "univpll_d7" }; =20 static const char * const camtg_parents[] =3D { --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F3A1ECAAD5 for ; Mon, 5 Sep 2022 10:05:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237075AbiIEKF0 (ORCPT ); Mon, 5 Sep 2022 06:05:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237460AbiIEKEl (ORCPT ); Mon, 5 Sep 2022 06:04:41 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2268511A32; Mon, 5 Sep 2022 03:04:40 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 051916601F31; Mon, 5 Sep 2022 11:04:37 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372279; bh=HrCKKc/4oHF8ameggu4aG6O2V2G7VX/dsz8S56XbbxA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KcF6CebA9m1M0yB5Gh3ymTfDLM3L0SKuavBBxR9Fgg6EXH7J74i3Ahmrwghuhbmgq k+qo/KvEIwX/9iOCDBwzUUUrHpkTnylY73luFG9QnQtT+L1lLVfhNFcsGkxopc6FU9 zu+Goz/InJSVjQMJiIJUlsTlViWCn1yzJNUoX73L3MHETu/0lNcNuDetWm8t5Rf/u/ bzGBPct1YRhwUAuwc1Se0hME85PZ7cp3o5+uYVzpi+69QTOoXs/SADU6aDWreDsjB5 JCi7qsq1TQNsMUifFTJMBH7u4xT7P8ZMID5YTue1HIyePHEU4MpqBmAuCXuHqyX96X 4kXHo2QeF24EQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 09/10] clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent Date: Mon, 5 Sep 2022 12:04:15 +0200 Message-Id: <20220905100416.42421-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Following what was done on MT8183 and MT8195, also propagate the rate changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192-mfg.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/c= lk-mt8192-mfg.c index 3bbc7469f0e4..8ea5acdf832c 100644 --- a/drivers/clk/mediatek/clk-mt8192-mfg.c +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c @@ -18,8 +18,10 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_MFG(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \ + _shift, &mtk_clk_gate_ops_setclr, \ + CLK_SET_RATE_PARENT) =20 static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0), --=20 2.37.2 From nobody Sat Sep 21 15:37:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BA87ECAAD5 for ; Mon, 5 Sep 2022 10:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237646AbiIEKFa (ORCPT ); Mon, 5 Sep 2022 06:05:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237188AbiIEKEt (ORCPT ); Mon, 5 Sep 2022 06:04:49 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64E4212D3A; Mon, 5 Sep 2022 03:04:41 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2A6836601F3A; Mon, 5 Sep 2022 11:04:39 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662372280; bh=6GKwElOpPO/EzvphH5H6i47s+zy8VO878SMP2y1sjwE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RuL182S0xoyK8tsGbzDbCL5ATeQHaM/fnHLfZfRK6jsNEq8D0ezrBJAJ3xQrPTQhv lrF2A5jv5mrX/dzmjY6D/AeiWIukHVruY18FGOkk5WN6MZU2Vt2nhqT9m48+0JuRsm uiAbCA9Tx4ENtOqkUEthQoIiuScY5h3FzeOAiIMRXD2g09QnrTVC+bRPRxOFz/Bhn2 H8KOnqW1pHWMN+YkhoSKQiSoXZ0jSk5oMNwmIRS/2wXQXJEVHxsBwljhbgegL+EieV XCkYN9Je6UZLlLEY3H9MMdMbetbREgalVV1ajxkn25NHK2hJpl/X4ogtAWZlK+Mvlh +tW7+4th8Ew/A== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: mturquette@baylibre.com, sboyd@kernel.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Subject: [PATCH 10/10] clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel Date: Mon, 5 Sep 2022 12:04:16 +0200 Message-Id: <20220905100416.42421-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Following the changes that were done for mt8183, add a clock notifier for the GPU PLL selector mux: this allows safe clock rate changes by temporarily reparenting the GPU to a safe clock (clk26m) while the MFGPLL is reprogrammed and stabilizes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index ebbd2798d9a3..187dbffeb987 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1224,6 +1224,28 @@ static void clk_mt8192_top_init_early(struct device_= node *node) CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen", clk_mt8192_top_init_early); =20 +/* Register mux notifier for MFG mux */ +static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) +{ + struct mtk_mux_nb *mfg_mux_nb; + int i; + + mfg_mux_nb =3D devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(top_mtk_muxes); i++) + if (top_mtk_muxes[i].id =3D=3D CLK_TOP_MFG_PLL_SEL) + break; + if (i =3D=3D ARRAY_SIZE(top_mtk_muxes)) + return -EINVAL; + + mfg_mux_nb->ops =3D top_mtk_muxes[i].ops; + mfg_mux_nb->bypass_index =3D 0; /* Bypass to 26M crystal */ + + return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); +} + static int clk_mt8192_top_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; @@ -1247,6 +1269,12 @@ static int clk_mt8192_top_probe(struct platform_devi= ce *pdev) if (r) return r; =20 + r =3D clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, + top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); + if (r) + return r; + + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); } --=20 2.37.2