From nobody Sun Sep 22 04:40:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A6AAECAAD5 for ; Sat, 3 Sep 2022 09:34:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232291AbiICJeq (ORCPT ); Sat, 3 Sep 2022 05:34:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232842AbiICJei (ORCPT ); Sat, 3 Sep 2022 05:34:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC00120BC7; Sat, 3 Sep 2022 02:34:35 -0700 (PDT) X-UUID: 4dbaf151ab7d4977bbf073698e0ae4ef-20220903 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=A8yIwoxK4eYldHiTtkcfKhmHsWy3i5NwjecUCyK1Fsk=; b=Z/E52dhvG/c7f9Dp38wte/TbAFuThHbhJg5zI4UcTVOgmNmGc6yGkm+FlNfkXrS6bgvZPujSF1QRAf5pFM9KEcl38nb91zYEHtYzBSLk21PX0NZYZcCp4ayOQt+grh7VyAmDmKE/e9hf5jXp+7xPni4YSVs9fFf3qKiudalV9Zg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:cafabe31-0638-4207-8a16-906e61808388,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Relea se_Ham,ACTION:release,TS:70 X-CID-INFO: VERSION:1.1.10,REQID:cafabe31-0638-4207-8a16-906e61808388,OB:0,LOB :0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS 981B3D,ACTION:quarantine,TS:70 X-CID-META: VersionHash:84eae18,CLOUDID:b1677c56-e800-47dc-8adf-0c936acf4f1b,C OID:913e17828f96,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 4dbaf151ab7d4977bbf073698e0ae4ef-20220903 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1274869390; Sat, 03 Sep 2022 17:34:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 3 Sep 2022 17:34:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 3 Sep 2022 17:34:17 +0800 From: Lecopzer Chen To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 5/6] arm64: add hw_nmi_get_sample_period for preparation of lockup detector Date: Sat, 3 Sep 2022 17:34:14 +0800 Message-ID: <20220903093415.15850-6-lecopzer.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220903093415.15850-1-lecopzer.chen@mediatek.com> References: <20220903093415.15850-1-lecopzer.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set safe maximum CPU frequency to 5 GHz in case a particular platform doesn't implement cpufreq driver. Although, architecture doesn't put any restrictions on maximum frequency but 5 GHz seems to be safe maximum given the available Arm CPUs in the market which are clocked much less than 5 GHz. On the other hand, we can't make it much higher as it would lead to a large hard-lockup detection timeout on parts which are running slower (eg. 1GHz on Developerbox) and doesn't possess a cpufreq driver. [1]:http://lore.kernel.org/linux-arm-kernel/1610712101-14929-1-git-send-ema= il-sumit.garg@linaro.org Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Co-developed-by: Pingfan Liu Signed-off-by: Pingfan Liu Signed-off-by: Lecopzer Chen --- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/watchdog_hld.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm64/kernel/watchdog_hld.c diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 1add7b01efa7..122b50bfcc0e 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_MODULES) +=3D module.o obj-$(CONFIG_ARM64_MODULE_PLTS) +=3D module-plts.o obj-$(CONFIG_PERF_EVENTS) +=3D perf_regs.o perf_callchain.o obj-$(CONFIG_HW_PERF_EVENTS) +=3D perf_event.o +obj-$(CONFIG_HARDLOCKUP_DETECTOR_PERF) +=3D watchdog_hld.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) +=3D hw_breakpoint.o obj-$(CONFIG_CPU_PM) +=3D sleep.o suspend.o obj-$(CONFIG_CPU_IDLE) +=3D cpuidle.o diff --git a/arch/arm64/kernel/watchdog_hld.c b/arch/arm64/kernel/watchdog_= hld.c new file mode 100644 index 000000000000..de43318e4dd6 --- /dev/null +++ b/arch/arm64/kernel/watchdog_hld.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +/* + * Safe maximum CPU frequency in case a particular platform doesn't implem= ent + * cpufreq driver. Although, architecture doesn't put any restrictions on + * maximum frequency but 5 GHz seems to be safe maximum given the available + * Arm CPUs in the market which are clocked much less than 5 GHz. On the o= ther + * hand, we can't make it much higher as it would lead to a large hard-loc= kup + * detection timeout on parts which are running slower (eg. 1GHz on + * Developerbox) and doesn't possess a cpufreq driver. + */ +#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz +u64 hw_nmi_get_sample_period(int watchdog_thresh) +{ + unsigned int cpu =3D smp_processor_id(); + unsigned long max_cpu_freq; + + max_cpu_freq =3D cpufreq_get_hw_max_freq(cpu) * 1000UL; + if (!max_cpu_freq) + max_cpu_freq =3D SAFE_MAX_CPU_FREQ; + + return (u64)max_cpu_freq * watchdog_thresh; +} + --=20 2.34.1