From nobody Sun Sep 22 02:07:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59183ECAAD4 for ; Sat, 3 Sep 2022 09:34:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233018AbiICJel (ORCPT ); Sat, 3 Sep 2022 05:34:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232816AbiICJei (ORCPT ); Sat, 3 Sep 2022 05:34:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB305205D9; Sat, 3 Sep 2022 02:34:35 -0700 (PDT) X-UUID: 051434d8480e4aaeabacde571b5bdad5-20220903 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=R0yWopENN2DUpjXIzG6EDQabPLHkMoYr8rLHotCp2qM=; b=siJYmYgXXKjX/cuo11eNI1wsUz9+8vxFwe8rgxiFPQX241QEo9/Bv2C0KdyROHzxuqwGtWGwZmTt/Om9aWN3ZLarT/r6A0fvia7dlSLOt61B842yt5Bc/GXQQII15/KSQSVbI3EsapUi9tzf6DZAUwe1UtgkB8v0fOicAF04mcM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:a23515e7-2859-4cee-a194-4df719e60e5d,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_ Ham,ACTION:release,TS:0 X-CID-META: VersionHash:84eae18,CLOUDID:af677c56-e800-47dc-8adf-0c936acf4f1b,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 051434d8480e4aaeabacde571b5bdad5-20220903 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1828987830; Sat, 03 Sep 2022 17:34:18 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Sat, 3 Sep 2022 17:34:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 3 Sep 2022 17:34:17 +0800 From: Lecopzer Chen To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 1/6] kernel/watchdog: remove WATCHDOG_DEFAULT Date: Sat, 3 Sep 2022 17:34:10 +0800 Message-ID: <20220903093415.15850-2-lecopzer.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220903093415.15850-1-lecopzer.chen@mediatek.com> References: <20220903093415.15850-1-lecopzer.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No reference to WATCHDOG_DEFAULT, remove it. Signed-off-by: Pingfan Liu Signed-off-by: Lecopzer Chen Reviewed-by: Petr Mladek --- kernel/watchdog.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/kernel/watchdog.c b/kernel/watchdog.c index 8e61f21e7e33..582d572e1379 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -30,10 +30,8 @@ static DEFINE_MUTEX(watchdog_mutex); =20 #if defined(CONFIG_HARDLOCKUP_DETECTOR) || defined(CONFIG_HAVE_NMI_WATCHDO= G) -# define WATCHDOG_DEFAULT (SOFT_WATCHDOG_ENABLED | NMI_WATCHDOG_ENABLED) # define NMI_WATCHDOG_DEFAULT 1 #else -# define WATCHDOG_DEFAULT (SOFT_WATCHDOG_ENABLED) # define NMI_WATCHDOG_DEFAULT 0 #endif =20 --=20 2.34.1 From nobody Sun Sep 22 02:07:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACFF3ECAAD4 for ; Sat, 3 Sep 2022 09:34:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233119AbiICJeu (ORCPT ); Sat, 3 Sep 2022 05:34:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232903AbiICJei (ORCPT ); Sat, 3 Sep 2022 05:34:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA281205C9; Sat, 3 Sep 2022 02:34:35 -0700 (PDT) X-UUID: 3c6e36f3270842309824ba0ea68c950b-20220903 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Fk6YQJx40kje2/K3Geo0aBF/K64gPIAL1oQ6u/E9DXA=; b=KPEwW4I9+7qBsRvJs3Va+2T49HO5mQmWAhQM8Qw1oAjhKX11qvBZFpJCHeOckxkuz4pNppVAm93+O7spny7UukznhUCP7/gN/E/bWCYOXTtzZXTwN+QtALTjsiz/sPbRpUemYmi2qMtWBIEPXp4/U97o2GsyphEfJRm/u4VMYg8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:2c84e72e-317e-4595-b7ed-e9e50611b8bc,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Releas e_Ham,ACTION:release,TS:-25 X-CID-META: VersionHash:84eae18,CLOUDID:b2677c56-e800-47dc-8adf-0c936acf4f1b,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 3c6e36f3270842309824ba0ea68c950b-20220903 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 48071102; Sat, 03 Sep 2022 17:34:18 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Sat, 3 Sep 2022 17:34:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 3 Sep 2022 17:34:17 +0800 From: Lecopzer Chen To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 2/6] kernel/watchdog: change watchdog_nmi_enable() to void Date: Sat, 3 Sep 2022 17:34:11 +0800 Message-ID: <20220903093415.15850-3-lecopzer.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220903093415.15850-1-lecopzer.chen@mediatek.com> References: <20220903093415.15850-1-lecopzer.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nobody cares about the return value of watchdog_nmi_enable(), changing its prototype to void. Signed-off-by: Pingfan Liu Signed-off-by: Lecopzer Chen Reviewed-by: Petr Mladek --- arch/sparc/kernel/nmi.c | 8 +++----- include/linux/nmi.h | 2 +- kernel/watchdog.c | 3 +-- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/sparc/kernel/nmi.c b/arch/sparc/kernel/nmi.c index 060fff95a305..5dcf31f7e81f 100644 --- a/arch/sparc/kernel/nmi.c +++ b/arch/sparc/kernel/nmi.c @@ -282,11 +282,11 @@ __setup("nmi_watchdog=3D", setup_nmi_watchdog); * sparc specific NMI watchdog enable function. * Enables watchdog if it is not enabled already. */ -int watchdog_nmi_enable(unsigned int cpu) +void watchdog_nmi_enable(unsigned int cpu) { if (atomic_read(&nmi_active) =3D=3D -1) { pr_warn("NMI watchdog cannot be enabled or disabled\n"); - return -1; + return; } =20 /* @@ -295,11 +295,9 @@ int watchdog_nmi_enable(unsigned int cpu) * process first. */ if (!nmi_init_done) - return 0; + return; =20 smp_call_function_single(cpu, start_nmi_watchdog, NULL, 1); - - return 0; } /* * sparc specific NMI watchdog disable function. diff --git a/include/linux/nmi.h b/include/linux/nmi.h index f700ff2df074..81217ebbc4bd 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -119,7 +119,7 @@ static inline int hardlockup_detector_perf_init(void) {= return 0; } void watchdog_nmi_stop(void); void watchdog_nmi_start(void); int watchdog_nmi_probe(void); -int watchdog_nmi_enable(unsigned int cpu); +void watchdog_nmi_enable(unsigned int cpu); void watchdog_nmi_disable(unsigned int cpu); =20 void lockup_detector_reconfigure(void); diff --git a/kernel/watchdog.c b/kernel/watchdog.c index 582d572e1379..c705a18b26bf 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -93,10 +93,9 @@ __setup("nmi_watchdog=3D", hardlockup_panic_setup); * softlockup watchdog start and stop. The arch must select the * SOFTLOCKUP_DETECTOR Kconfig. */ -int __weak watchdog_nmi_enable(unsigned int cpu) +void __weak watchdog_nmi_enable(unsigned int cpu) { hardlockup_detector_perf_enable(); - return 0; } =20 void __weak watchdog_nmi_disable(unsigned int cpu) --=20 2.34.1 From nobody Sun Sep 22 02:07:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7277BECAAD5 for ; Sat, 3 Sep 2022 09:34:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232470AbiICJei (ORCPT ); Sat, 3 Sep 2022 05:34:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231535AbiICJea (ORCPT ); Sat, 3 Sep 2022 05:34:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEDC8DF9; Sat, 3 Sep 2022 02:34:24 -0700 (PDT) X-UUID: b80dc9603d70496ca9d518010329f5df-20220903 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dccgenCLdaldLGNe2nW0rKf95nJyRR69M0nwfddNDug=; b=HJ9It8VPnfLqwxBnGc71fIZTmyT0Nd3VRv3JmVYC6B5+20MBYv9bKdvEJj64EsOF9VlA/qrKRlQe3Kr849no+MCr0mJM0sQjVE5Puoc5ITTQVQwBGFLCh2vPsHNac6BgBDoaPV/uS0xep/4ji5rl4Nx+++BAO8ImRnNj9tkXh0s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:6d4da491-4928-46a9-b5c4-67201287da1c,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Relea se_Ham,ACTION:release,TS:70 X-CID-INFO: VERSION:1.1.10,REQID:6d4da491-4928-46a9-b5c4-67201287da1c,OB:0,LOB :0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS 981B3D,ACTION:quarantine,TS:70 X-CID-META: VersionHash:84eae18,CLOUDID:714b86d0-20bd-4e5e-ace8-00692b7ab380,C OID:171e9c4a6f6e,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: b80dc9603d70496ca9d518010329f5df-20220903 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1384698886; Sat, 03 Sep 2022 17:34:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 3 Sep 2022 17:34:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 3 Sep 2022 17:34:17 +0800 From: Lecopzer Chen To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 3/6] kernel/watchdog_hld: Ensure CPU-bound context when creating hardlockup detector event Date: Sat, 3 Sep 2022 17:34:12 +0800 Message-ID: <20220903093415.15850-4-lecopzer.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220903093415.15850-1-lecopzer.chen@mediatek.com> References: <20220903093415.15850-1-lecopzer.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Pingfan Liu hardlockup_detector_event_create() should create perf_event on the current CPU. Preemption could not get disabled because perf_event_create_kernel_counter() allocates memory. Instead, the CPU locality is achieved by processing the code in a per-CPU bound kthread. Add a check to prevent mistakes when calling the code in another code path. Signed-off-by: Pingfan Liu Co-developed-by: Lecopzer Chen Signed-off-by: Lecopzer Chen Reviewed-by: Petr Mladek --- kernel/watchdog_hld.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/kernel/watchdog_hld.c b/kernel/watchdog_hld.c index 247bf0b1582c..96b717205952 100644 --- a/kernel/watchdog_hld.c +++ b/kernel/watchdog_hld.c @@ -165,10 +165,16 @@ static void watchdog_overflow_callback(struct perf_ev= ent *event, =20 static int hardlockup_detector_event_create(void) { - unsigned int cpu =3D smp_processor_id(); + unsigned int cpu; struct perf_event_attr *wd_attr; struct perf_event *evt; =20 + /* + * Preemption is not disabled because memory will be allocated. + * Ensure CPU-locality by calling this in per-CPU kthread. + */ + WARN_ON(!is_percpu_thread()); + cpu =3D raw_smp_processor_id(); wd_attr =3D &wd_hw_attr; wd_attr->sample_period =3D hw_nmi_get_sample_period(watchdog_thresh); =20 --=20 2.34.1 From nobody Sun Sep 22 02:07:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6F48ECAAD4 for ; Sat, 3 Sep 2022 09:34:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233213AbiICJe4 (ORCPT ); Sat, 3 Sep 2022 05:34:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232860AbiICJei (ORCPT ); Sat, 3 Sep 2022 05:34:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7725E20F45; Sat, 3 Sep 2022 02:34:36 -0700 (PDT) X-UUID: e159e1125547489db4b8ed5e3b46692a-20220903 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MKjPOQSfw4i+nosmT0Yk7Xpa23Skr63LcOCzDbNQ9cM=; b=NA53436TGFpAN18RC/kl8XW8TIL/JiQpRpBB/rmy4RENqPAKKOzOx34PJ77dmYv+fJLMmSR8AdcA1thykSGUHjnSBH6Zx+xkuupMoX+cA6FpXKYo+/HReB1I/kht3ZS4la+ewiHv2B7T2zvKT3cOprlFLI7CYaLWh1E3KXlka3s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:e78fed9e-e994-4927-bb47-c635915d72e0,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Releas e_Ham,ACTION:release,TS:-25 X-CID-META: VersionHash:84eae18,CLOUDID:d36f0521-1c20-48a5-82a0-25f9c331906d,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: e159e1125547489db4b8ed5e3b46692a-20220903 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1095855068; Sat, 03 Sep 2022 17:34:18 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Sat, 3 Sep 2022 17:34:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 3 Sep 2022 17:34:17 +0800 From: Lecopzer Chen To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 4/6] kernel/watchdog: Adapt the watchdog_hld interface for async model Date: Sat, 3 Sep 2022 17:34:13 +0800 Message-ID: <20220903093415.15850-5-lecopzer.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220903093415.15850-1-lecopzer.chen@mediatek.com> References: <20220903093415.15850-1-lecopzer.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When lockup_detector_init()->watchdog_nmi_probe(), PMU may be not ready yet. E.g. on arm64, PMU is not ready until device_initcall(armv8_pmu_driver_init). And it is deeply integrated with the driver model and cpuhp. Hence it is hard to push this initialization before smp_init(). But it is easy to take an opposite approach and try to initialize the watchdog once again later. The delayed probe is called using workqueues. It need to allocate memory and must be proceed in a normal context. The delayed probe is able to use if watchdog_nmi_probe() returns non-zero which means the return code returned when PMU is not ready yet. Provide an API - retry_lockup_detector_init() for anyone who needs to delayed init lockup detector if they had ever failed at lockup_detector_init(). The original assumption is: nobody should use delayed probe after lockup_detector_check() which has __init attribute. That is, anyone uses this API must call between lockup_detector_init() and lockup_detector_check(), and the caller must have __init attribute Reviewed-by: Petr Mladek Co-developed-by: Pingfan Liu Signed-off-by: Pingfan Liu Signed-off-by: Lecopzer Chen Suggested-by: Petr Mladek Reported-by: kernel test robot --- include/linux/nmi.h | 2 ++ kernel/watchdog.c | 67 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index 81217ebbc4bd..7f128e3aae38 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -118,6 +118,8 @@ static inline int hardlockup_detector_perf_init(void) {= return 0; } =20 void watchdog_nmi_stop(void); void watchdog_nmi_start(void); + +void retry_lockup_detector_init(void); int watchdog_nmi_probe(void); void watchdog_nmi_enable(unsigned int cpu); void watchdog_nmi_disable(unsigned int cpu); diff --git a/kernel/watchdog.c b/kernel/watchdog.c index c705a18b26bf..0b650d726e50 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -103,7 +103,13 @@ void __weak watchdog_nmi_disable(unsigned int cpu) hardlockup_detector_perf_disable(); } =20 -/* Return 0, if a NMI watchdog is available. Error code otherwise */ +/* + * Arch specific API. + * + * Return 0 when NMI watchdog is available, negative value otherwise. + * Note that the negative value means that a delayed probe might + * succeed later. + */ int __weak __init watchdog_nmi_probe(void) { return hardlockup_detector_perf_init(); @@ -850,6 +856,62 @@ static void __init watchdog_sysctl_init(void) #define watchdog_sysctl_init() do { } while (0) #endif /* CONFIG_SYSCTL */ =20 +static void __init lockup_detector_delay_init(struct work_struct *work); +static bool allow_lockup_detector_init_retry __initdata; + +static struct work_struct detector_work __initdata =3D + __WORK_INITIALIZER(detector_work, lockup_detector_delay_init); + +static void __init lockup_detector_delay_init(struct work_struct *work) +{ + int ret; + + ret =3D watchdog_nmi_probe(); + if (ret) { + pr_info("Delayed init of the lockup detector failed: %d\n", ret); + pr_info("Perf NMI watchdog permanently disabled\n"); + return; + } + + allow_lockup_detector_init_retry =3D false; + + nmi_watchdog_available =3D true; + lockup_detector_setup(); +} + +/* + * retry_lockup_detector_init - retry init lockup detector if possible. + * + * Retry hardlockup detector init. It is useful when it requires some + * functionality that has to be initialized later on a particular + * platform. + */ +void __init retry_lockup_detector_init(void) +{ + /* Must be called before late init calls */ + if (!allow_lockup_detector_init_retry) + return; + + schedule_work(&detector_work); +} + +/* + * Ensure that optional delayed hardlockup init is proceed before + * the init code and memory is freed. + */ +static int __init lockup_detector_check(void) +{ + /* Prevent any later retry. */ + allow_lockup_detector_init_retry =3D false; + + /* Make sure no work is pending. */ + flush_work(&detector_work); + + return 0; + +} +late_initcall_sync(lockup_detector_check); + void __init lockup_detector_init(void) { if (tick_nohz_full_enabled()) @@ -860,6 +922,9 @@ void __init lockup_detector_init(void) =20 if (!watchdog_nmi_probe()) nmi_watchdog_available =3D true; + else + allow_lockup_detector_init_retry =3D true; + lockup_detector_setup(); watchdog_sysctl_init(); } --=20 2.34.1 From nobody Sun Sep 22 02:07:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A6AAECAAD5 for ; Sat, 3 Sep 2022 09:34:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232291AbiICJeq (ORCPT ); Sat, 3 Sep 2022 05:34:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232842AbiICJei (ORCPT ); Sat, 3 Sep 2022 05:34:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC00120BC7; Sat, 3 Sep 2022 02:34:35 -0700 (PDT) X-UUID: 4dbaf151ab7d4977bbf073698e0ae4ef-20220903 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=A8yIwoxK4eYldHiTtkcfKhmHsWy3i5NwjecUCyK1Fsk=; b=Z/E52dhvG/c7f9Dp38wte/TbAFuThHbhJg5zI4UcTVOgmNmGc6yGkm+FlNfkXrS6bgvZPujSF1QRAf5pFM9KEcl38nb91zYEHtYzBSLk21PX0NZYZcCp4ayOQt+grh7VyAmDmKE/e9hf5jXp+7xPni4YSVs9fFf3qKiudalV9Zg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:cafabe31-0638-4207-8a16-906e61808388,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Relea se_Ham,ACTION:release,TS:70 X-CID-INFO: VERSION:1.1.10,REQID:cafabe31-0638-4207-8a16-906e61808388,OB:0,LOB :0,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS 981B3D,ACTION:quarantine,TS:70 X-CID-META: VersionHash:84eae18,CLOUDID:b1677c56-e800-47dc-8adf-0c936acf4f1b,C OID:913e17828f96,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 4dbaf151ab7d4977bbf073698e0ae4ef-20220903 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1274869390; Sat, 03 Sep 2022 17:34:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 3 Sep 2022 17:34:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 3 Sep 2022 17:34:17 +0800 From: Lecopzer Chen To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 5/6] arm64: add hw_nmi_get_sample_period for preparation of lockup detector Date: Sat, 3 Sep 2022 17:34:14 +0800 Message-ID: <20220903093415.15850-6-lecopzer.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220903093415.15850-1-lecopzer.chen@mediatek.com> References: <20220903093415.15850-1-lecopzer.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set safe maximum CPU frequency to 5 GHz in case a particular platform doesn't implement cpufreq driver. Although, architecture doesn't put any restrictions on maximum frequency but 5 GHz seems to be safe maximum given the available Arm CPUs in the market which are clocked much less than 5 GHz. On the other hand, we can't make it much higher as it would lead to a large hard-lockup detection timeout on parts which are running slower (eg. 1GHz on Developerbox) and doesn't possess a cpufreq driver. [1]:http://lore.kernel.org/linux-arm-kernel/1610712101-14929-1-git-send-ema= il-sumit.garg@linaro.org Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Co-developed-by: Pingfan Liu Signed-off-by: Pingfan Liu Signed-off-by: Lecopzer Chen --- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/watchdog_hld.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm64/kernel/watchdog_hld.c diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 1add7b01efa7..122b50bfcc0e 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_MODULES) +=3D module.o obj-$(CONFIG_ARM64_MODULE_PLTS) +=3D module-plts.o obj-$(CONFIG_PERF_EVENTS) +=3D perf_regs.o perf_callchain.o obj-$(CONFIG_HW_PERF_EVENTS) +=3D perf_event.o +obj-$(CONFIG_HARDLOCKUP_DETECTOR_PERF) +=3D watchdog_hld.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) +=3D hw_breakpoint.o obj-$(CONFIG_CPU_PM) +=3D sleep.o suspend.o obj-$(CONFIG_CPU_IDLE) +=3D cpuidle.o diff --git a/arch/arm64/kernel/watchdog_hld.c b/arch/arm64/kernel/watchdog_= hld.c new file mode 100644 index 000000000000..de43318e4dd6 --- /dev/null +++ b/arch/arm64/kernel/watchdog_hld.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +/* + * Safe maximum CPU frequency in case a particular platform doesn't implem= ent + * cpufreq driver. Although, architecture doesn't put any restrictions on + * maximum frequency but 5 GHz seems to be safe maximum given the available + * Arm CPUs in the market which are clocked much less than 5 GHz. On the o= ther + * hand, we can't make it much higher as it would lead to a large hard-loc= kup + * detection timeout on parts which are running slower (eg. 1GHz on + * Developerbox) and doesn't possess a cpufreq driver. + */ +#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz +u64 hw_nmi_get_sample_period(int watchdog_thresh) +{ + unsigned int cpu =3D smp_processor_id(); + unsigned long max_cpu_freq; + + max_cpu_freq =3D cpufreq_get_hw_max_freq(cpu) * 1000UL; + if (!max_cpu_freq) + max_cpu_freq =3D SAFE_MAX_CPU_FREQ; + + return (u64)max_cpu_freq * watchdog_thresh; +} + --=20 2.34.1 From nobody Sun Sep 22 02:07:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7C05ECAAD4 for ; Sat, 3 Sep 2022 09:34:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232785AbiICJed (ORCPT ); Sat, 3 Sep 2022 05:34:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231408AbiICJea (ORCPT ); Sat, 3 Sep 2022 05:34:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6786D25D0; Sat, 3 Sep 2022 02:34:25 -0700 (PDT) X-UUID: 527f4726e6cc4af1b545b6da5cdf0756-20220903 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=bO4QOQ/e9i8ms/DUZLFaUf9p8kBsjcVNJksHRMkiffg=; b=YXhKkCQxAjfo0TpKzEsVkn0IuimgDG6QyuZfoSXjRz7kFhRejHd9YmumVnkDFhXmoYKYqcuTDe/SK3++Qil3lPE2mFGYCcb/EjrX9P4Y3kPJiJejuFNufCwz3Fc08JQjwCbGUSZJBgeQrsqteuq8mFVJg4dtRuxANudOvo4wrf4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:16be7aa9-9e7e-4c10-968c-cc224b3069d2,OB:0,L OB:10,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Rele ase_Ham,ACTION:release,TS:70 X-CID-INFO: VERSION:1.1.10,REQID:16be7aa9-9e7e-4c10-968c-cc224b3069d2,OB:0,LOB :10,IP:0,URL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_G S981B3D,ACTION:quarantine,TS:70 X-CID-META: VersionHash:84eae18,CLOUDID:ba677c56-e800-47dc-8adf-0c936acf4f1b,C OID:c8f675e5ed70,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 527f4726e6cc4af1b545b6da5cdf0756-20220903 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1605873364; Sat, 03 Sep 2022 17:34:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Sat, 3 Sep 2022 17:34:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Sat, 3 Sep 2022 17:34:18 +0800 From: Lecopzer Chen To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 6/6] arm64: Enable perf events based hard lockup detector Date: Sat, 3 Sep 2022 17:34:15 +0800 Message-ID: <20220903093415.15850-7-lecopzer.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220903093415.15850-1-lecopzer.chen@mediatek.com> References: <20220903093415.15850-1-lecopzer.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the recent feature added to enable perf events to use pseudo NMIs as interrupts on platforms which support GICv3 or later, its now been possible to enable hard lockup detector (or NMI watchdog) on arm64 platforms. So enable corresponding support. One thing to note here is that normally lockup detector is initialized just after the early initcalls but PMU on arm64 comes up much later as device_initcall(). To cope with that, overriding watchdog_nmi_probe() to let the watchdog framework know PMU not ready, and inform the framework to re-initialize lockup detection once PMU has been initialized. [1]: http://lore.kernel.org/linux-arm-kernel/1610712101-14929-1-git-send-em= ail-sumit.garg@linaro.org Co-developed-by: Sumit Garg Signed-off-by: Sumit Garg Co-developed-by: Pingfan Liu Signed-off-by: Pingfan Liu Signed-off-by: Lecopzer Chen Reported-by: kernel test robot --- arch/arm64/Kconfig | 2 ++ arch/arm64/kernel/perf_event.c | 12 ++++++++++-- arch/arm64/kernel/watchdog_hld.c | 14 ++++++++++++++ drivers/perf/arm_pmu.c | 5 +++++ include/linux/perf/arm_pmu.h | 2 ++ 5 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9fb9fff08c94..9ec7d3d7a0ac 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -189,6 +189,7 @@ config ARM64 select HAVE_FUNCTION_ERROR_INJECTION select HAVE_FUNCTION_GRAPH_TRACER select HAVE_GCC_PLUGINS + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_N= MI select HAVE_HW_BREAKPOINT if PERF_EVENTS select HAVE_IOREMAP_PROT select HAVE_IRQ_TIME_ACCOUNTING @@ -196,6 +197,7 @@ config ARM64 select HAVE_NMI select HAVE_PATA_PLATFORM select HAVE_PERF_EVENTS + select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_PREEMPT_DYNAMIC_KEY diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index cb69ff1e6138..d9eec8911bf0 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 /* ARMv8 Cortex-A53 specific event types. */ #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 @@ -1390,10 +1391,17 @@ static struct platform_driver armv8_pmu_driver =3D { =20 static int __init armv8_pmu_driver_init(void) { + int ret; + if (acpi_disabled) - return platform_driver_register(&armv8_pmu_driver); + ret =3D platform_driver_register(&armv8_pmu_driver); else - return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); + ret =3D arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); + + if (!ret) + retry_lockup_detector_init(); + + return ret; } device_initcall(armv8_pmu_driver_init) =20 diff --git a/arch/arm64/kernel/watchdog_hld.c b/arch/arm64/kernel/watchdog_= hld.c index de43318e4dd6..c9c6ec889c15 100644 --- a/arch/arm64/kernel/watchdog_hld.c +++ b/arch/arm64/kernel/watchdog_hld.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include +#include =20 /* * Safe maximum CPU frequency in case a particular platform doesn't implem= ent @@ -23,3 +25,15 @@ u64 hw_nmi_get_sample_period(int watchdog_thresh) return (u64)max_cpu_freq * watchdog_thresh; } =20 +int __init watchdog_nmi_probe(void) +{ + /* + * hardlockup_detector_perf_init() will success even if Pseudo-NMI turns = off, + * however, the pmu interrupts will act like a normal interrupt instead of + * NMI and the hardlockup detector would be broken. + */ + if (!arm_pmu_irq_is_nmi()) + return -ENODEV; + + return hardlockup_detector_perf_init(); +} diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 59d3980b8ca2..ceee2c55d436 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -697,6 +697,11 @@ static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int= cpu) return per_cpu(hw_events->irq, cpu); } =20 +bool arm_pmu_irq_is_nmi(void) +{ + return has_nmi; +} + /* * PMU hardware loses all context when a CPU goes offline. * When a CPU is hotplugged back in, since some hardware registers are diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 0407a38b470a..29c56c92bab7 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -171,6 +171,8 @@ void kvm_host_pmu_init(struct arm_pmu *pmu); #define kvm_host_pmu_init(x) do { } while(0) #endif =20 +bool arm_pmu_irq_is_nmi(void); + /* Internal functions only for core arm_pmu code */ struct arm_pmu *armpmu_alloc(void); struct arm_pmu *armpmu_alloc_atomic(void); --=20 2.34.1