From nobody Mon Apr 6 20:11:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 770C7C38145 for ; Sat, 3 Sep 2022 00:23:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231462AbiICAXc (ORCPT ); Fri, 2 Sep 2022 20:23:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231344AbiICAXO (ORCPT ); Fri, 2 Sep 2022 20:23:14 -0400 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18EF8F72C1 for ; Fri, 2 Sep 2022 17:23:10 -0700 (PDT) Received: by mail-pf1-x449.google.com with SMTP id y21-20020a056a001c9500b0053817f57e8dso1721859pfw.6 for ; Fri, 02 Sep 2022 17:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date; bh=Kx3IG3ZoWEJ93nwNVzD3nD++UrihjFhzPKMLEK+k0c8=; b=Eq+2HWdocGwiCPEnjoFBfKuQEtWfIrv4jJlrD4dm47o7bKopijIRIw7Er0dRFK+k+H Tltwof+sBHYKD1XGoToZbji8bukdmJrsQoJnlW4oWBjWfa+nd4ot+i19xSSkW7LERWhg axaIL/DFSVEcT/HN+cMGqF49hivO9/yQ2nEHn68lCGGPvqd7ouHsxqP0HOV2600KzrXr 7A7l0HQqEn79+I3iAE2usc49JMVhMxIgJDGhlz82NYPbYc3lhzHf/1+36E3EqXmPFajZ YILJlUtsy0Lf29YiEB4dBIQPDIVMPfE4obNWjhpf0/i5L8haQqsZpzvY9diZVdDURHY/ knvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date; bh=Kx3IG3ZoWEJ93nwNVzD3nD++UrihjFhzPKMLEK+k0c8=; b=SibuBCBv8/N5xNGXMojQrB7RRSFq6e/yvJ6HvEp7fuTt5JkTGr3kmN36ns7u2Gy7df 8Yqm2XR1o59zUcdWXA+wGFl6kz4tazDdmInujbPXAbw0zUkojzVA8JDADgTn6PfBeWCQ y1tbJoINSoILmhaqgmj1ZRFGoCHpaqERIs9Pb6Vx+2vIh62O7lJyUFKY3Hu0E+pOaqoM 0uLSpx00Ks/awa9YeiOADk7TBXXTS+XKNkQIyCJvpSjliP1zzPwFuHhym70MXwTbT9vm wKMgKD00Wg7gNFMgPQg5M0Ls8qUJUyFA8a5Jzdy/8FqgTO+/ja4wDFtNgbNAR8W12TS5 TS4w== X-Gm-Message-State: ACgBeo2HN8Lrkmr8kJFX4Tp11rrQbVaAs95pSSD5HqY7Wp5v7Y8iF7rH GhfK8IjI9ILO8vGdqDO+tbq2socYjqc= X-Google-Smtp-Source: AA6agR4Ts92+AkwUcUZPtJoBrs0hDIJelMYlLMh2y78qNty8SD+rW2ZEqPyeaDMqHyQlHe3PXzHGrUD0UNw= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:8503:b0:173:368b:dce3 with SMTP id bj3-20020a170902850300b00173368bdce3mr38018382plb.104.1662164589610; Fri, 02 Sep 2022 17:23:09 -0700 (PDT) Reply-To: Sean Christopherson Date: Sat, 3 Sep 2022 00:22:37 +0000 In-Reply-To: <20220903002254.2411750-1-seanjc@google.com> Mime-Version: 1.0 References: <20220903002254.2411750-1-seanjc@google.com> X-Mailer: git-send-email 2.37.2.789.g6183377224-goog Message-ID: <20220903002254.2411750-7-seanjc@google.com> Subject: [PATCH v2 06/23] KVM: SVM: Replace "avic_mode" enum with "x2avic_enabled" boolean From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Suravee Suthikulpanit , Maxim Levitsky , Li RongQing Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the "avic_mode" enum with a single bool to track whether or not x2AVIC is enabled. KVM already has "apicv_enabled" that tracks if any flavor of AVIC is enabled, i.e. AVIC_MODE_NONE and AVIC_MODE_X1 are redundant and unnecessary noise. No functional change intended. Signed-off-by: Sean Christopherson Reviewed-by: Maxim Levitsky --- arch/x86/kvm/svm/avic.c | 46 +++++++++++++++++++---------------------- arch/x86/kvm/svm/svm.c | 2 +- arch/x86/kvm/svm/svm.h | 9 +------- 3 files changed, 23 insertions(+), 34 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index de7fcb3a544b..3022a135c060 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -53,7 +53,7 @@ static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HAS= H_BITS); static u32 next_vm_id =3D 0; static bool next_vm_id_wrapped =3D 0; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); -enum avic_modes avic_mode; +bool x2avic_enabled; =20 /* * This is a wrapper of struct amd_iommu_ir_data. @@ -79,8 +79,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) * (prevents mapping it into the guest) if any vCPU has x2APIC enabled, * thus enabling AVIC activates only the doorbell mechanism. */ - if (apic_x2apic_mode(svm->vcpu.arch.apic) && - avic_mode =3D=3D AVIC_MODE_X2) { + if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |=3D X2APIC_MODE_MASK; vmcb->control.avic_physical_id |=3D X2AVIC_MAX_PHYSICAL_ID; /* Disabling MSR intercept for x2APIC registers */ @@ -247,8 +246,8 @@ static u64 *avic_get_physical_id_entry(struct kvm_vcpu = *vcpu, u64 *avic_physical_id_table; struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); =20 - if ((avic_mode =3D=3D AVIC_MODE_X1 && index > AVIC_MAX_PHYSICAL_ID) || - (avic_mode =3D=3D AVIC_MODE_X2 && index > X2AVIC_MAX_PHYSICAL_ID)) + if ((!x2avic_enabled && index > AVIC_MAX_PHYSICAL_ID) || + (index > X2AVIC_MAX_PHYSICAL_ID)) return NULL; =20 avic_physical_id_table =3D page_address(kvm_svm->avic_physical_id_table_p= age); @@ -295,8 +294,8 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) int id =3D vcpu->vcpu_id; struct vcpu_svm *svm =3D to_svm(vcpu); =20 - if ((avic_mode =3D=3D AVIC_MODE_X1 && id > AVIC_MAX_PHYSICAL_ID) || - (avic_mode =3D=3D AVIC_MODE_X2 && id > X2AVIC_MAX_PHYSICAL_ID)) + if ((!x2avic_enabled && id > AVIC_MAX_PHYSICAL_ID) || + (id > X2AVIC_MAX_PHYSICAL_ID)) return -EINVAL; =20 if (!vcpu->arch.apic->regs) @@ -1094,10 +1093,7 @@ void avic_refresh_virtual_apic_mode(struct kvm_vcpu = *vcpu) struct vcpu_svm *svm =3D to_svm(vcpu); struct vmcb *vmcb =3D svm->vmcb01.ptr; =20 - if (!lapic_in_kernel(vcpu) || avic_mode =3D=3D AVIC_MODE_NONE) - return; - - if (!enable_apicv) + if (!lapic_in_kernel(vcpu) || !enable_apicv) return; =20 if (kvm_vcpu_apicv_active(vcpu)) { @@ -1173,32 +1169,32 @@ bool avic_hardware_setup(struct kvm_x86_ops *x86_op= s) if (!npt_enabled) return false; =20 + /* AVIC is a prerequisite for x2AVIC. */ + if (!boot_cpu_has(X86_FEATURE_AVIC) && !force_avic) { + if (boot_cpu_has(X86_FEATURE_X2AVIC)) { + pr_warn(FW_BUG "Cannot support x2AVIC due to AVIC is disabled"); + pr_warn(FW_BUG "Try enable AVIC using force_avic option"); + } + return false; + } + if (boot_cpu_has(X86_FEATURE_AVIC)) { - avic_mode =3D AVIC_MODE_X1; pr_info("AVIC enabled\n"); } else if (force_avic) { /* * Some older systems does not advertise AVIC support. * See Revision Guide for specific AMD processor for more detail. */ - avic_mode =3D AVIC_MODE_X1; pr_warn("AVIC is not supported in CPUID but force enabled"); pr_warn("Your system might crash and burn"); } =20 /* AVIC is a prerequisite for x2AVIC. */ - if (boot_cpu_has(X86_FEATURE_X2AVIC)) { - if (avic_mode =3D=3D AVIC_MODE_X1) { - avic_mode =3D AVIC_MODE_X2; - pr_info("x2AVIC enabled\n"); - } else { - pr_warn(FW_BUG "Cannot support x2AVIC due to AVIC is disabled"); - pr_warn(FW_BUG "Try enable AVIC using force_avic option"); - } - } + x2avic_enabled =3D boot_cpu_has(X86_FEATURE_X2AVIC); + if (x2avic_enabled) + pr_info("x2AVIC enabled\n"); =20 - if (avic_mode !=3D AVIC_MODE_NONE) - amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); + amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); =20 - return !!avic_mode; + return true; } diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 2aa5069bafb2..709f0b3e7a48 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -821,7 +821,7 @@ void svm_set_x2apic_msr_interception(struct vcpu_svm *s= vm, bool intercept) if (intercept =3D=3D svm->x2avic_msrs_intercepted) return; =20 - if (avic_mode !=3D AVIC_MODE_X2 || + if (!x2avic_enabled || !apic_x2apic_mode(svm->vcpu.arch.apic)) return; =20 diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 7a95f50e80e7..29c334a932c3 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -35,14 +35,7 @@ extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; extern int vgif; extern bool intercept_smi; - -enum avic_modes { - AVIC_MODE_NONE =3D 0, - AVIC_MODE_X1, - AVIC_MODE_X2, -}; - -extern enum avic_modes avic_mode; +extern bool x2avic_enabled; =20 /* * Clean bits in VMCB. --=20 2.37.2.789.g6183377224-goog