From nobody Thu Dec 18 08:37:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56CA7C54EE9 for ; Fri, 2 Sep 2022 14:07:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238821AbiIBOH3 (ORCPT ); Fri, 2 Sep 2022 10:07:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238388AbiIBOHK (ORCPT ); Fri, 2 Sep 2022 10:07:10 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E6E6201B8; Fri, 2 Sep 2022 06:35:02 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 532CEB82AA1; Fri, 2 Sep 2022 12:38:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91D9CC433C1; Fri, 2 Sep 2022 12:38:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1662122315; bh=C0kRf5bfCnAeS9Hjj1AXvIeKcZDY5VMANtibcHCCYZQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JCOw1pAMEnG/Nb0wKOg+H7CkFVyh130rp/HWJ5hw2dv7hEsxewZ2xBkDqc82jojQz MyKtgK+/M4BoutZCuWaT8C9cBNcZjxfl4jCeshiiM3K3sbMq5asA9Uc2VqAi0q0MVq /oqjh6n9anvhuQO8ZbEZ7h+aljfwiGpFGqrocb0k= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Aric Cyr , Brian Chang , Ilya Bakoulin , Daniel Wheeler , Alex Deucher , Sasha Levin Subject: [PATCH 5.19 55/72] drm/amd/display: Fix pixel clock programming Date: Fri, 2 Sep 2022 14:19:31 +0200 Message-Id: <20220902121406.569076375@linuxfoundation.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220902121404.772492078@linuxfoundation.org> References: <20220902121404.772492078@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ilya Bakoulin [ Upstream commit 04fb918bf421b299feaee1006e82921d7d381f18 ] [Why] Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned between different HDMI lanes when using YCbCr420 10-bit pixel format. BIOS functions for transmitter/encoder control take pixel clock in kHz increments, whereas the function for setting the pixel clock is in 100Hz increments. Setting pixel clock to a value that is not on a kHz boundary will cause the issue. [How] Round pixel clock down to nearest kHz in 10/12-bpc cases. Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/driver= s/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 845aa8a1027d8..c4040adb88b03 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -545,9 +545,11 @@ static void dce112_get_pix_clk_dividers_helper ( switch (pix_clk_params->color_depth) { case COLOR_DEPTH_101010: actual_pixel_clock_100hz =3D (actual_pixel_clock_100hz * 5) >> 2; + actual_pixel_clock_100hz -=3D actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_121212: actual_pixel_clock_100hz =3D (actual_pixel_clock_100hz * 6) >> 2; + actual_pixel_clock_100hz -=3D actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_161616: actual_pixel_clock_100hz =3D actual_pixel_clock_100hz * 2; --=20 2.35.1