From nobody Thu Dec 18 08:36:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8FD6C38145 for ; Fri, 2 Sep 2022 12:55:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238171AbiIBMzl (ORCPT ); Fri, 2 Sep 2022 08:55:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238096AbiIBMxr (ORCPT ); Fri, 2 Sep 2022 08:53:47 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5D23186C8; Fri, 2 Sep 2022 05:38:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EB85662119; Fri, 2 Sep 2022 12:35:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06163C433D6; Fri, 2 Sep 2022 12:35:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1662122142; bh=cYJwQ0rMnudUe3akeqw33dycPQO7EW+u8IdVBhMnKpA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ivK0/j47KAj/T0VZIQ+ObgNoFa9i9mXtidbid7KxGZy6eFE11Wr6yPIOY37Eweqj5 PcoXNyIN+xOpNh+csEvyzTzFwHWe/7HSrS/8xnM9QRrLuMmBkHsxXFvQ0WqoqqRLdp NYayqFZ/HXx5g0wXYJWmeKWk//3ErPG5YuONodMA= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, James Morse , Will Deacon , Lucas Wei Subject: [PATCH 5.19 06/72] arm64: errata: Add Cortex-A510 to the repeat tlbi list Date: Fri, 2 Sep 2022 14:18:42 +0200 Message-Id: <20220902121404.999570603@linuxfoundation.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220902121404.772492078@linuxfoundation.org> References: <20220902121404.772492078@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: James Morse commit 39fdb65f52e9a53d32a6ba719f96669fd300ae78 upstream. Cortex-A510 is affected by an erratum where in rare circumstances the CPUs may not handle a race between a break-before-make sequence on one CPU, and another CPU accessing the same page. This could allow a store to a page that has been unmapped. Work around this by adding the affected CPUs to the list that needs TLB sequences to be done twice. Signed-off-by: James Morse Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com Signed-off-by: Will Deacon Cc: Lucas Wei Signed-off-by: Greg Kroah-Hartman --- Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 17 +++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 8 +++++++- 3 files changed, 26 insertions(+), 1 deletion(-) --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -106,6 +106,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_20770= 57 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_24410= 09 | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_21198= 58 | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_20542= 23 | --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -838,6 +838,23 @@ config ARM64_ERRATUM_2224489 =20 If unsure, say Y. =20 +config ARM64_ERRATUM_2441009 + bool "Cortex-A510: Completion of affected memory accesses might not be gu= aranteed by completion of a TLBI" + default y + select ARM64_WORKAROUND_REPEAT_TLBI + help + This option adds a workaround for ARM Cortex-A510 erratum #2441009. + + Under very rare circumstances, affected Cortex-A510 CPUs + may not handle a race between a break-before-make sequence on one + CPU, and another CPU accessing the same page. This could allow a + store to a page that has been unmapped. + + Work around this by adding the affected CPUs to the list that needs + TLB sequences to be done twice. + + If unsure, say Y. + config ARM64_ERRATUM_2064142 bool "Cortex-A510: 2064142: workaround TRBE register writes while disable= d" depends on CORESIGHT_TRBE --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -214,6 +214,12 @@ static const struct arm64_cpu_capabiliti ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), }, #endif +#ifdef CONFIG_ARM64_ERRATUM_2441009 + { + /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */ + ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), + }, +#endif {}, }; #endif @@ -490,7 +496,7 @@ const struct arm64_cpu_capabilities arm6 #endif #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI { - .desc =3D "Qualcomm erratum 1009, or ARM erratum 1286807", + .desc =3D "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009", .capability =3D ARM64_WORKAROUND_REPEAT_TLBI, .type =3D ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches =3D cpucap_multi_entry_cap_matches,