From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66D3FECAAD1 for ; Thu, 1 Sep 2022 13:37:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233033AbiIANhh (ORCPT ); Thu, 1 Sep 2022 09:37:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233964AbiIANg4 (ORCPT ); Thu, 1 Sep 2022 09:36:56 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E03F855B9; Thu, 1 Sep 2022 06:35:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039302; x=1693575302; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jmjzFPLTzirPRRdjytSXcGvB/NkyTEAOoOOffWQqE6s=; b=dnAiDCdz2SLKWPz3/aspuclRAYTgzygiEqDgcDIqP+HfQg6UxY540rZb yMrgjEw7yGNnOImCdAvdXuSue6qY6etsC9OWJSgMy5HBtIoCYdfg/PDz6 LifPbqtveTI/Sngwik+suJg9u1ShENOboWfuM/N3znG3hH7YpNmv5uuSj yuPcukxfbSUpk3jyVogAdtG9ssoz+eVRAoMn4cWRai7yLIfAJWUTojQoN 9KmCX+3P7EcOaf4h5GuHp0kt79QDRC+RJ5Uyp/+tLRVtczwSli/ApBIYs I93dQet7skGaLXjZgqIoClD8w67Pba6y0qtXUDHGKnGFS8OmED5O0PYUm w==; X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="175197577" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:34:52 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:34:48 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:34:45 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , , Krzysztof Kozlowski Subject: [PATCH v3 1/9] dt-bindings: riscv: microchip: document icicle reference design Date: Thu, 1 Sep 2022 14:33:56 +0100 Message-ID: <20220901133403.3392291-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The icicle kit reference design's v2022.09 release,made some changes to the memory map - including adding the ability to read the fabric clock controllers via the system controller bus & making the PCI controller work with upstream Linux. While the PCI was not working in the v2022.03 design, so nothing is broken there in terms of backwards compatibility, the fabric clocks used in the v2022.03 design were chosen by the individual run of the synthesis tool. In the v2022.09 reference design, the clocks are fixed to use the "north west" fabric Clock Conditioning Circuitry. Make use of a new compatible to denote that this is not backwards compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/microchip.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 1aa7336a9672..485981fbfb4b 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -17,12 +17,18 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - microchip,mpfs-icicle-kit - - microchip,mpfs-icicle-reference-rtlv2203 - - sundance,polarberry - - const: microchip,mpfs + oneOf: + - items: + - enum: + - microchip,mpfs-icicle-reference-rtlv2203 + - microchip,mpfs-icicle-reference-rtlv2209 + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs + + - items: + - enum: + - sundance,polarberry + - const: microchip,mpfs =20 additionalProperties: true =20 --=20 2.36.1 From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1958FECAAD1 for ; Thu, 1 Sep 2022 13:37:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234292AbiIANhr (ORCPT ); Thu, 1 Sep 2022 09:37:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234020AbiIANg5 (ORCPT ); Thu, 1 Sep 2022 09:36:57 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 906A8A45F; Thu, 1 Sep 2022 06:35:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039304; x=1693575304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TeMAuptxTZZXiK5k0POB/q784cUgxKduZsMG1KWinnw=; b=rGJSkn9YfdmlvzVQ7VzhsNDaeX/jf1OU2RaXSE31WlBw6k2v9KT/2sg/ TYdgcxVC/Mc6hW294bV8rV/QRjSYs7rSxpB3dRUxsT10RLRKj3Y5d1f6r XGHHAhxpEW/DslsDRNiYJUTC2FMrUCrxIy/sn4vJlbvP4D3Bat0OJwF2V SbC8zPho/7F8NRizybgg452o59RwvA7g52gqTHphZG86qs52oiIH/VPwR ke56V0Luhxd5Bv7dKrSYss0rBIvcEdiRiTxxD+NuHJR7irb+dHkeQAe1O bAwbtwajCSOC7gzb4cRkE2p9NUsdG7vOTzB8vDbEVVq9/zx/CI3mUeuoC Q==; X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="175197596" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:34:54 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:34:51 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:34:48 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v3 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp Date: Thu, 1 Sep 2022 14:33:57 +0100 Message-ID: <20220901133403.3392291-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform. Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-s= om-mpfs025t-pcie-serdes Signed-off-by: Conor Dooley Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 485981fbfb4b..630f82c85a0c 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,6 +27,7 @@ properties: =20 - items: - enum: + - aries,m100pfsevp - sundance,polarberry - const: microchip,mpfs =20 --=20 2.36.1 From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50DECECAAD1 for ; Thu, 1 Sep 2022 13:37:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233014AbiIANhw (ORCPT ); Thu, 1 Sep 2022 09:37:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234026AbiIANg5 (ORCPT ); Thu, 1 Sep 2022 09:36:57 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4997419023; Thu, 1 Sep 2022 06:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039304; x=1693575304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VqcEjdujxakv3noDHpoHtBuaB79FIa784j+2h1ikqjc=; b=BmmcXWZjWioUwkmMuHuNKBb5Bi4qU98/Ann4Td/O4zwABatdc7V0+1ne PozXt7oXt91ZYXgAltk5C/nPlrszwFhqTZmlTmpwxMlrwBIlF07XHJr3V Rsy46vxM5DvthOctmFF1WaJkqHSJYrNQNo/hmaYvhOLfjjpOqvCF4Vzam xj7nTTBuCBKWOXGdfWox8Jt9tQLWG5wLwQ7ZiSVAitAf6wedHLkpTX0SH jx7VqgZ0r0hKTawVHZPY+T3IDzpPQDOEaS+JMVr4rxikqD6+MH6yIVKd0 xmuXKXGxwMoMtBN0kaBTc1neTLG+YQyVV8BvLdZuKUzZekfFz4t/kR0eJ w==; X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="175197600" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:34:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:34:54 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:34:51 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , , Krzysztof Kozlowski Subject: [PATCH v3 3/9] dt-bindings: riscv: microchip: document the sev kit Date: Thu, 1 Sep 2022 14:33:58 +0100 Message-ID: <20220901133403.3392291-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shravan Chippa Update devicetree bindings document with PolarFire SoC Video Kit, known by its "sev-kit" product code. Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77= E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Shravan Chippa Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 630f82c85a0c..ab0a64cd5386 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - aries,m100pfsevp + - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs =20 --=20 2.36.1 From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC11EECAAD3 for ; Thu, 1 Sep 2022 13:37:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233953AbiIANho (ORCPT ); Thu, 1 Sep 2022 09:37:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233982AbiIANg5 (ORCPT ); Thu, 1 Sep 2022 09:36:57 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C66719018; Thu, 1 Sep 2022 06:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039304; x=1693575304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hyLDKbNNI38wXrC5Tei7bV2mB9uLlpphPD5ViUjlS80=; b=RtwBnjnTn8GNVToisMrB8u0yIuD1JxcgglKmBmkPfAZdu4UxonmAfKrM UrCrYyXo40yLi5AHTlj3GcrwDQdrqdJbCvcLJsXeyAxBfJlABIvkhfoik Q6/1vafdVkMStddY1S2vS8lxbCD+ptz+EPbZA5zwjjGF3fautF8kx4iLr H0bm7BYYHWp1CYjXAkAjrzAnuy9jjfVlQy8HJrKqBZi3hUfLMtLgpQDO+ QHhhG49ZHfBsd/kwGGlnobE3YpIyOniVcxIAojav0ljH7qZjk5Ud5CgSu qGHXM6APYEBK3rplbtiPt8YdJWFPSlAmvg7bDmNY6a6Vq+0Hh+Gf4SHlN g==; X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="171970587" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:35:03 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:34:57 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:34:55 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v3 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit Date: Thu, 1 Sep 2022 14:33:59 +0100 Message-ID: <20220901133403.3392291-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The recently removed, accidentally included, "matr0" property was used in place of a dma-ranges property. The PCI controller is non-functional with mainline Linux in the v2022.02 or later reference designs and has not worked without configuration of address-translation since v2021.08. Add the address translation that will be used by the v2022.09 reference design & update the compatible used by the dts. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 7 ++++++- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..c0fb9dd7b2c8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,7 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { - compatible =3D "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpf= s"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; @@ -37,3 +38,7 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; }; + +&pcie { + dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index f3f87ed2007f..5e2b8aa2ff64 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -11,7 +11,8 @@ =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; - compatible =3D "microchip,mpfs-icicle-kit", "microchip,mpfs"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 aliases { ethernet0 =3D &mac1; --=20 2.36.1 From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E3ECECAAD3 for ; Thu, 1 Sep 2022 13:38:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233069AbiIANh7 (ORCPT ); Thu, 1 Sep 2022 09:37:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233410AbiIANg5 (ORCPT ); Thu, 1 Sep 2022 09:36:57 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49A8C19032; Thu, 1 Sep 2022 06:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039304; x=1693575304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uHxdMeV9cT2StB4AnfzN0Ak927pm3jnkLPLYp0ihHAo=; b=VPFS6fQ8gukELIlWyCmSjXmLnZ8qQvJYGJmWR1TJxpRZf5zKR1HiAzD2 VtIPxUz24ykzL7oVxPua0NWRrJw7LmARkZ4m80bYGgYRxKbh4/NzhXDTq f5R1b2wNEmTr9IooTWs+c9tUfVFCspb9zDMYmOZFsTCpN8I1fbmtMwqq4 whSH5oax1LFpeUqVEMgR8tMg2U3sEuEy4RMKj146NU7TwZPpH84oluAJP bxK3/oLAlcZgkU8OFhDTw7/VK+Ja8zSCegzqSUeWVkrDCkRDBDYON7zcx e8FQuwvXZoyOmeh+89/n3BRKWv8X49ygwHwKHkxpfhzUpbRtyvhUILlaj g==; X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="111754604" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:35:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:35:01 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:34:58 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v3 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Date: Thu, 1 Sep 2022 14:34:00 +0100 Message-ID: <20220901133403.3392291-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In today's edition of moving things around: The PCIe root port on PolarFire SoC is more part of the FPGA than of the Core Complex. It is located on the other side of the chip and, apart from its interrupts, most of its configuration is determined by the FPGA bitstream rather. This includes: - address translation in both directions - the addresses at which the config and data regions appear to the core complex - the clocks used by the AXI bus - the plic interrupt used Moving the PCIe node to the -fabric.dtsi makes it clearer than a singular configuration for root port is not correct & allows the base SoC dtsi to be more easily included. Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 32 +++++++++++++++++-- .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 ----------------- 3 files changed, 58 insertions(+), 32 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index c0fb9dd7b2c8..a21440c8ee03 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -37,8 +37,34 @@ fabric_clk1: fabric-clk1 { #clock-cells =3D <0>; clock-frequency =3D <125000000>; }; -}; =20 -&pcie { - dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 49380c428ec9..67303bc0e451 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -13,4 +13,33 @@ fabric_clk1: fabric-clk1 { #clock-cells =3D <0>; clock-frequency =3D <125000000>; }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 74493344ea41..b1b7964608e3 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -464,35 +464,6 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - pcie: pcie@2000000000 { - compatible =3D "microchip,pcie-host-1.0"; - #address-cells =3D <0x3>; - #interrupt-cells =3D <0x1>; - #size-cells =3D <0x2>; - device_type =3D "pci"; - reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names =3D "cfg", "apb"; - bus-range =3D <0x0 0x7f>; - interrupt-parent =3D <&plic>; - interrupts =3D <119>; - interrupt-map =3D <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask =3D <0 0 0 7>; - clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names =3D "fic0", "fic1", "fic3"; - ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent =3D <&pcie>; - msi-controller; - status =3D "disabled"; - pcie_intc: interrupt-controller { - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - interrupt-controller; - }; - }; - mbox: mailbox@37020000 { compatible =3D "microchip,mpfs-mailbox"; reg =3D <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; --=20 2.36.1 From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C896C0502C for ; Thu, 1 Sep 2022 13:38:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233353AbiIANiI (ORCPT ); Thu, 1 Sep 2022 09:38:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232699AbiIANg5 (ORCPT ); Thu, 1 Sep 2022 09:36:57 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE4441EAC3; Thu, 1 Sep 2022 06:35:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039305; x=1693575305; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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Thu, 1 Sep 2022 06:35:01 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v3 6/9] riscv: dts: microchip: icicle: update pci address properties Date: Thu, 1 Sep 2022 14:34:01 +0100 Message-ID: <20220901133403.3392291-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index a21440c8ee03..32d51c4a5b0c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { + compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", "microchip,mpfs"; =20 @@ -38,13 +39,13 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; =20 - pcie: pcie@2000000000 { + pcie: pcie@3000000000 { compatible =3D "microchip,pcie-host-1.0"; #address-cells =3D <0x3>; #interrupt-cells =3D <0x1>; #size-cells =3D <0x2>; device_type =3D "pci"; - reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg =3D <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; reg-names =3D "cfg", "apb"; bus-range =3D <0x0 0x7f>; interrupt-parent =3D <&plic>; @@ -54,9 +55,9 @@ pcie: pcie@2000000000 { <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask =3D <0 0 0 7>; - clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names =3D "fic0", "fic1", "fic3"; - ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + clocks =3D <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; msi-parent =3D <&pcie>; msi-controller; --=20 2.36.1 From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C79BECAAD3 for ; Thu, 1 Sep 2022 13:38:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233233AbiIANiP (ORCPT ); Thu, 1 Sep 2022 09:38:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234319AbiIANhE (ORCPT ); Thu, 1 Sep 2022 09:37:04 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBC232A711; Thu, 1 Sep 2022 06:35:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039315; x=1693575315; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rZMihXhOLlKxYs0tCwQAUj7e9S0faqqljRoP4WeBM6o=; b=PVNMjdYFLLN+uzYPkizEFXD2YjRg5t3IoZhZIwxYtSC+d2U0K0NOJkBW 2XaCLYO9Qksqo80GIANSUEElKHRCh2Q8eopX4SkSRTrw1i9jLiDewabrd j+GzeiXEHNBpPAhK+o6a2I/SEvAVRsqrjXzyZtzP+HlPxjhYSonf/efZi 5pPPIKkCdAP9wZWeRT1O4O7IoE/6SWJW3s1Q92J33/cELg8IX2O9u988N s4uh2T1bYb9RTzX+tZ+LAKqpQthk6WXNpByttexn2qoLBH7tUTzQdHczT HgQ2NNoVEyfDmkL0fQIAj8PLWfNAqKT5Pk/yt+LevwBQw5+sSomOylpEe w==; X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="178641861" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:35:13 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:35:07 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:35:04 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v3 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Date: Thu, 1 Sep 2022 14:34:02 +0100 Message-ID: <20220901133403.3392291-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When users try to add onto the reference design, they find that the current addresses that peripherals connected to Fabric InterConnect (FIC) 3 use are restrictive. For the v2022.09 reference design, the peripherals have been shifted down, leaving more contiguous address space for their custom IP/peripherals. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 32d51c4a5b0c..98f04be0dc6b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -6,18 +6,18 @@ / { compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", "microchip,mpfs"; =20 - core_pwm0: pwm@41000000 { + core_pwm0: pwm@40000000 { compatible =3D "microchip,corepwm-rtl-v4"; - reg =3D <0x0 0x41000000 0x0 0xF0>; + reg =3D <0x0 0x40000000 0x0 0xF0>; microchip,sync-update-mask =3D /bits/ 32 <0>; #pwm-cells =3D <2>; clocks =3D <&fabric_clk3>; status =3D "disabled"; }; =20 - i2c2: i2c@44000000 { + i2c2: i2c@40000200 { compatible =3D "microchip,corei2c-rtl-v7"; - reg =3D <0x0 0x44000000 0x0 0x1000>; + reg =3D <0x0 0x40000200 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; clocks =3D <&fabric_clk3>; --=20 2.36.1 From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3072AECAAD1 for ; Thu, 1 Sep 2022 13:38:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233926AbiIANiX (ORCPT ); Thu, 1 Sep 2022 09:38:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233262AbiIANhG (ORCPT ); Thu, 1 Sep 2022 09:37:06 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00CE93C8E0; Thu, 1 Sep 2022 06:35:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039319; x=1693575319; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JmSuLtaQ7npJNIq92yZ3LYXqo64TxloECUbCfR2Jr/8=; b=GfWTUY9Foz7SEo+kDZ4DOCTKYO3/wUi+XYXAGSvPoOtw8swjscqmlivd iKcsQjtaUglpHGAKedzdaIh4vKss4wjg1hjYWJA+KcvxcBUPm98FJR37I HbVG0/QwpKW53yXqsRwMzpZyABt8MtQqgJgXq6oOzFRi0xe9fgj2WTjDg 2m6f8noJxsdRavy0XBRd0ZvpWEbm/OHq1BaHTRIVGXilIUIFcpO1OQz1X otWQxsy9UY91mqcb72Vz5QKOnKaa/44Xu2WmJCDmDygJny6naaRi4znIN m3M2r2QQMwNgQOjIg+hhLW2yytK+fpY067801Bpucl7CjQ2s4BdD/EcCc Q==; X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="171970625" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:35:18 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:35:11 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:35:07 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v3 8/9] riscv: dts: microchip: add sevkit device tree Date: Thu, 1 Sep 2022 14:34:03 +0100 Message-ID: <20220901133403.3392291-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vattipalli Praveen Add a basic dts for the Microchip Smart Embedded Vision dev kit. The SEV kit is an upcoming first party board, featuring an MPFS250T and: - Dual Sony Camera Sensors (IMX334) - IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi - Bluetooth 5 Low Energy - 4 GB DDR4 x64 - 2 GB LPDDR4 x32 - 1 GB SPI Flash - 8 GB eMMC flash & SD card slot (multiplexed) - HDMI2.0 Video Input/Output - MIPI DSI Output - MIPI CSI-2 Input Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77= E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Vattipalli Praveen Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 ++++++ .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index 39aae7b04f1c..f18477b2e86d 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi b/arch/= riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi new file mode 100644 index 000000000000..8545baf4d129 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/bo= ot/dts/microchip/mpfs-sev-kit.dts new file mode 100644 index 000000000000..013cb666c72d --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-sev-kit-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "Microchip PolarFire-SoC SEV Kit"; + compatible =3D "microchip,mpfs-sev-kit", "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + fabricbuf0ddrc: buffer@80000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x80000000 0x0 0x2000000>; + }; + + fabricbuf1ddrnc: buffer@c4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0xc4000000 0x0 0x4000000>; + }; + + fabricbuf2ddrncwcb: buffer@d4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0xd4000000 0x0 0x4000000>; + }; + }; + + ddrc_cache: memory@1000000000 { + device_type =3D "memory"; + reg =3D <0x10 0x0 0x0 0x76000000>; + }; +}; + +&i2c0 { + status =3D "okay"; +}; + +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status =3D "okay"; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; + phy1: ethernet-phy@9 { + reg =3D <9>; + }; + phy0: ethernet-phy@8 { + reg =3D <8>; + }; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy1>; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + status =3D "okay"; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "otg"; +}; --=20 2.36.1 From nobody Thu Apr 9 14:33:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9FEFECAAD3 for ; Thu, 1 Sep 2022 13:38:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233378AbiIANia (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="111754634" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:35:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:35:14 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:35:11 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v3 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Date: Thu, 1 Sep 2022 14:34:04 +0100 Message-ID: <20220901133403.3392291-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220901133403.3392291-1-conor.dooley@microchip.com> References: <20220901133403.3392291-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device trees for both configs used by the Aries Embedded M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM, featuring: - 2GB DDR4 SDRAM dedicated to the HMS - 512MB DDR4 SDRAM dedicated to the FPGA - 32 MB SPI NOR Flash - 4 GByte eMMC and a carrier board with: - 2x Gigabit Ethernet - USB - 2x UART - 2x CAN - TFT connector - HSMC extension connector - 3x PMOD extension connectors - microSD-card slot Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-s= om-mpfs025t-pcie-serdes Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchi= p-soc-fpga-m100pfsevp-riscv-hsmc-pmod Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFS= EVP-Schematics.pdf Co-developed-by: Wolfgang Grandegger Signed-off-by: Wolfgang Grandegger Signed-off-by: Conor Dooley --- Note to self: The amount of DDR at 0x10... is probably a fraction of what is actually the= re. arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++ .../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++ 3 files changed, 225 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index f18477b2e86d..7427a20934f3 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/= riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi new file mode 100644 index 000000000000..7b9ee13b6a3a --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv= /boot/dts/microchip/mpfs-m100pfsevp.dts new file mode 100644 index 000000000000..184cb36a175e --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-m100pfs-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model =3D "Aries Embedded M100PFEVPS"; + compatible =3D "aries,m100pfsevp", "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac0; + ethernet1 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + gpio0 =3D &gpio0; + gpio1 =3D &gpio2; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + }; + ddrc_cache_hi: memory@1040000000 { + device_type =3D "memory"; + reg =3D <0x10 0x40000000 0x0 0x40000000>; + }; +}; + +&can0 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +&gpio0 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>; + ngpios =3D <14>; + status =3D "okay"; + + pmic-irq-hog { + gpio-hog; + gpios =3D <13 0>; + input; + }; + + /* Set to low for eMMC, high for SD-card */ + mmc-sel-hog { + gpio-hog; + gpios =3D <12 0>; + output-high; + }; +}; + +&gpio2 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>, <27>, <28>, + <29>, <30>, <31>, <32>, + <33>, <34>, <35>, <36>, + <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>; + status =3D "okay"; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy1>; + phy1: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + max-frequency =3D <50000000>; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + disable-wp; + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&pcie { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "host"; +}; --=20 2.36.1