From nobody Thu Apr 9 14:47:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D900AECAAD1 for ; Thu, 1 Sep 2022 13:31:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233950AbiIANb5 (ORCPT ); Thu, 1 Sep 2022 09:31:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233971AbiIANba (ORCPT ); Thu, 1 Sep 2022 09:31:30 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 12E24DFFF; Thu, 1 Sep 2022 06:27:37 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8F611ED1; Thu, 1 Sep 2022 06:27:35 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.16.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BB8FC3F7B4; Thu, 1 Sep 2022 06:27:55 -0700 (PDT) From: James Clark To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, broonie@kernel.org, acme@kernel.org, leo.yan@linaro.org, john.garry@huawei.com, catalin.marinas@arm.com, will@kernel.org, James Clark , Jonathan Corbet , Mark Rutland , linux-doc@vger.kernel.org Subject: [PATCH v3 1/2] perf: arm64: Add SVE vector granule register to user regs Date: Thu, 1 Sep 2022 14:26:57 +0100 Message-Id: <20220901132658.1024635-2-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220901132658.1024635-1-james.clark@arm.com> References: <20220901132658.1024635-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Dwarf based unwinding in a function that pushes SVE registers onto the stack requires the unwinder to know the length of the SVE register to calculate the stack offsets correctly. This was added to the Arm specific Dwarf spec as the VG pseudo register[1]. Add the vector length at position 46 if it's requested by userspace and SVE is supported. If it's not supported then fail to open the event. The vector length must be on each sample because it can be changed at runtime via a prctl or ptrace call. Also by adding it as a register rather than a separate attribute, minimal changes will be required in an unwinder that already indexes into the register list. [1]: https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.r= st Reviewed-by: Mark Brown Signed-off-by: James Clark --- arch/arm64/include/uapi/asm/perf_regs.h | 7 ++++++ arch/arm64/kernel/perf_regs.c | 30 +++++++++++++++++++++++-- drivers/perf/arm_pmu.c | 2 +- 3 files changed, 36 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/uapi/asm/perf_regs.h b/arch/arm64/include/u= api/asm/perf_regs.h index d54daafa89e3..0d4b40c78e47 100644 --- a/arch/arm64/include/uapi/asm/perf_regs.h +++ b/arch/arm64/include/uapi/asm/perf_regs.h @@ -37,5 +37,12 @@ enum perf_event_arm_regs { PERF_REG_ARM64_SP, PERF_REG_ARM64_PC, PERF_REG_ARM64_MAX, + + /* Extended/pseudo registers */ + PERF_REG_ARM64_VG =3D 46, // SVE Vector Granule + PERF_REG_ARM64_EXTENDED_MAX }; + +#define PERF_REG_EXTENDED_MASK (1ULL << PERF_REG_ARM64_VG) + #endif /* _ASM_ARM64_PERF_REGS_H */ diff --git a/arch/arm64/kernel/perf_regs.c b/arch/arm64/kernel/perf_regs.c index f6f58e6265df..b4eece3eb17d 100644 --- a/arch/arm64/kernel/perf_regs.c +++ b/arch/arm64/kernel/perf_regs.c @@ -9,9 +9,27 @@ #include #include =20 +static u64 perf_ext_regs_value(int idx) +{ + switch (idx) { + case PERF_REG_ARM64_VG: + if (WARN_ON_ONCE(!system_supports_sve())) + return 0; + + /* + * Vector granule is current length in bits of SVE registers + * divided by 64. + */ + return (task_get_sve_vl(current) * 8) / 64; + default: + WARN_ON_ONCE(true); + return 0; + } +} + u64 perf_reg_value(struct pt_regs *regs, int idx) { - if (WARN_ON_ONCE((u32)idx >=3D PERF_REG_ARM64_MAX)) + if (WARN_ON_ONCE((u32)idx >=3D PERF_REG_ARM64_EXTENDED_MAX)) return 0; =20 /* @@ -51,6 +69,9 @@ u64 perf_reg_value(struct pt_regs *regs, int idx) if ((u32)idx =3D=3D PERF_REG_ARM64_PC) return regs->pc; =20 + if ((u32)idx >=3D PERF_REG_ARM64_MAX) + return perf_ext_regs_value(idx); + return regs->regs[idx]; } =20 @@ -58,7 +79,12 @@ u64 perf_reg_value(struct pt_regs *regs, int idx) =20 int perf_reg_validate(u64 mask) { - if (!mask || mask & REG_RESERVED) + u64 reserved_mask =3D REG_RESERVED; + + if (system_supports_sve()) + reserved_mask &=3D ~(1ULL << PERF_REG_ARM64_VG); + + if (!mask || mask & reserved_mask) return -EINVAL; =20 return 0; diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 59d3980b8ca2..3f07df5a7e95 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -894,7 +894,7 @@ static struct arm_pmu *__armpmu_alloc(gfp_t flags) * pmu::filter_match callback and pmu::event_init group * validation). */ - .capabilities =3D PERF_PMU_CAP_HETEROGENEOUS_CPUS, + .capabilities =3D PERF_PMU_CAP_HETEROGENEOUS_CPUS | PERF_PMU_CAP_EXTENDE= D_REGS, }; =20 pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =3D --=20 2.28.0 From nobody Thu Apr 9 14:47:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91FDAECAAD1 for ; Thu, 1 Sep 2022 13:32:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233706AbiIANcK (ORCPT ); Thu, 1 Sep 2022 09:32:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234403AbiIANbm (ORCPT ); Thu, 1 Sep 2022 09:31:42 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A21969C512; Thu, 1 Sep 2022 06:27:38 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4438D1042; Thu, 1 Sep 2022 06:27:38 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.16.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7085E3F7B4; Thu, 1 Sep 2022 06:27:58 -0700 (PDT) From: James Clark To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, broonie@kernel.org, acme@kernel.org, leo.yan@linaro.org, john.garry@huawei.com, catalin.marinas@arm.com, will@kernel.org, James Clark , Jonathan Corbet , Mark Rutland , linux-doc@vger.kernel.org Subject: [PATCH v3 2/2] arm64/sve: Add Perf extensions documentation Date: Thu, 1 Sep 2022 14:26:58 +0100 Message-Id: <20220901132658.1024635-3-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220901132658.1024635-1-james.clark@arm.com> References: <20220901132658.1024635-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document that the VG register is available in Perf samples Signed-off-by: James Clark Reviewed-by: Mark Brown --- Documentation/arm64/sve.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst index 93c2c2990584..8955bf1bf757 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arm64/sve.rst @@ -452,6 +452,24 @@ The regset data starts with struct user_sve_header, co= ntaining: * Modifying the system default vector length does not affect the vector le= ngth of any existing process or thread that does not make an execve() call. =20 +10. Perf extensions +-------------------------------- + +* The arm64 specific DWARF standard [5] added the VG (Vector Granule) regi= ster + at index 46. This register is used for DWARF unwinding when variable len= gth + SVE registers are pushed onto the stack. + +* Its value is equivalent to the current SVE vector length (VL) in bits di= vided + by 64. + +* The value is included in Perf samples in the regs[46] field if + PERF_SAMPLE_REGS_USER is set and the sample_regs_user mask has bit 46 se= t. + +* The value is the current value at the time the sample was taken, and it = can + change over time. + +* If the system doesn't support SVE when perf_event_open is called with th= ese + settings, the event will fail to open. =20 Appendix A. SVE programmer's model (informative) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -593,3 +611,5 @@ References http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055c/IHI0055C_bet= a_aapcs64.pdf http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/inde= x.html Procedure Call Standard for the ARM 64-bit Architecture (AArch64) + +[5] https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.r= st --=20 2.28.0