From nobody Wed Feb 11 05:07:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CE98ECAAD1 for ; Wed, 31 Aug 2022 18:09:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232324AbiHaSJf (ORCPT ); Wed, 31 Aug 2022 14:09:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232477AbiHaSIp (ORCPT ); Wed, 31 Aug 2022 14:08:45 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FCF9E1AA9; Wed, 31 Aug 2022 11:08:42 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 6CE99CE1EA8; Wed, 31 Aug 2022 18:08:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0A15C433D7; Wed, 31 Aug 2022 18:08:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661969318; bh=X2tPBwFu7XVmB6phIN9skedNXoCQvadtocOI5Ou7AtQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=si7DSIRhdsRxBzfyCLDLcXGbY1zTdbsvSoQNoYlvoMOxZV8UzkgMKlyg+KlNF8K6N znqPMfNc9gFbGi8sCI/zLztp3m7txw6R3E9ls0XQ6+Ifz5vj0aSW27KuWYW1mazaaV TOUvOm9jJzeE6j90fHZTZtVe/YVHbcOai80JCMc1bQIdjzzl3TnBcKO8I58+LQO5Pe ES5Pa5R1TA3akb7Qt3xtzvG3Cu7gGpv+XGulOubH6iNkKTCGdwzRerFQB4Lcmcnjxy V+K7uuoLvu4anO3dJU+cIL79zUJJ3SW0FKetDPROyhjZ1Icd9562xCLQrzqNetnRFB zqNaBhb+kRMLw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Sebastian Andrzej Siewior , Thomas Gleixner , Steven Rostedt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 1/5] RISC-V: KVM: Record number of signal exits as a vCPU stat Date: Thu, 1 Sep 2022 01:59:16 +0800 Message-Id: <20220831175920.2806-2-jszhang@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org> References: <20220831175920.2806-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Record a statistic indicating the number of times a vCPU has exited due to a pending signal. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/kvm_host.h | 1 + arch/riscv/kvm/vcpu.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 60c517e4d576..dbbf43d52623 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -67,6 +67,7 @@ struct kvm_vcpu_stat { u64 mmio_exit_kernel; u64 csr_exit_user; u64 csr_exit_kernel; + u64 signal_exits; u64 exits; }; =20 diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index d0f08d5b4282..3da459fedc28 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -28,6 +28,7 @@ const struct _kvm_stats_desc kvm_vcpu_stats_desc[] =3D { STATS_DESC_COUNTER(VCPU, mmio_exit_kernel), STATS_DESC_COUNTER(VCPU, csr_exit_user), STATS_DESC_COUNTER(VCPU, csr_exit_kernel), + STATS_DESC_COUNTER(VCPU, signal_exits), STATS_DESC_COUNTER(VCPU, exits) }; =20 @@ -973,6 +974,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) if (signal_pending(current)) { ret =3D -EINTR; run->exit_reason =3D KVM_EXIT_INTR; + ++vcpu->stat.signal_exits; } =20 /* --=20 2.34.1 From nobody Wed Feb 11 05:07:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D619DECAAD3 for ; Wed, 31 Aug 2022 18:09:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232370AbiHaSJj (ORCPT ); Wed, 31 Aug 2022 14:09:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232479AbiHaSIq (ORCPT ); Wed, 31 Aug 2022 14:08:46 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE01EE68A4; Wed, 31 Aug 2022 11:08:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 38E7DB82221; Wed, 31 Aug 2022 18:08:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA6F7C433D6; Wed, 31 Aug 2022 18:08:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661969321; bh=gEVSZo6IZOnVd4BVQuHJHN2F00a6Y7EMFpgV8m6o8aI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XEyi+M9675/fqQ6aKfd9KGILK7DLDHCOgs9bTXSikr3xdjgLsrV5fGBAvEZgvVW3S VlOQL2ce8OkX6h04S0yF7a8Ca/yw4bnv6RRQbc1qr0lB4SmNGmKBB8Lpf663SMZSMT dSaj/d/XuWy9RfQAC5vhG3rQ1B9AeYKvQTHDBKVomodgjc+KGG6eaaXkkrsVYjuFxF tUl8ECG68p+LifunrHPRwB7djV9kHCgtm1fId/qgAe89+d1Bn/8crYTOu3c//e0Q36 8ocBeeB453p3xTGU9VkyE5TLW8YOIFERaAJ2rSrbUjTWkJr1JbjM0ET8x8aPIe0x7m An5qEgUXOjrvg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Sebastian Andrzej Siewior , Thomas Gleixner , Steven Rostedt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 2/5] RISC-V: KVM: Use generic guest entry infrastructure Date: Thu, 1 Sep 2022 01:59:17 +0800 Message-Id: <20220831175920.2806-3-jszhang@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org> References: <20220831175920.2806-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use generic guest entry infrastructure to properly handle TIF_NOTIFY_RESUME. Signed-off-by: Jisheng Zhang --- arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/vcpu.c | 18 ++++++------------ 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index f5a342fa1b1d..f36a737d5f96 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -24,6 +24,7 @@ config KVM select PREEMPT_NOTIFIERS select KVM_MMIO select KVM_GENERIC_DIRTYLOG_READ_PROTECT + select KVM_XFER_TO_GUEST_WORK select HAVE_KVM_VCPU_ASYNC_IOCTL select HAVE_KVM_EVENTFD select SRCU diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 3da459fedc28..e3e6b8608288 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -959,7 +960,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) run->exit_reason =3D KVM_EXIT_UNKNOWN; while (ret > 0) { /* Check conditions before entering the guest */ - cond_resched(); + ret =3D xfer_to_guest_mode_handle_work(vcpu); + if (!ret) + ret =3D 1; =20 kvm_riscv_gstage_vmid_update(vcpu); =20 @@ -967,16 +970,6 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) =20 local_irq_disable(); =20 - /* - * Exit if we have a signal pending so that we can deliver - * the signal to user space. - */ - if (signal_pending(current)) { - ret =3D -EINTR; - run->exit_reason =3D KVM_EXIT_INTR; - ++vcpu->stat.signal_exits; - } - /* * Ensure we set mode to IN_GUEST_MODE after we disable * interrupts and before the final VCPU requests check. @@ -999,7 +992,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) =20 if (ret <=3D 0 || kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) || - kvm_request_pending(vcpu)) { + kvm_request_pending(vcpu) || + xfer_to_guest_mode_work_pending()) { vcpu->mode =3D OUTSIDE_GUEST_MODE; local_irq_enable(); kvm_vcpu_srcu_read_lock(vcpu); --=20 2.34.1 From nobody Wed Feb 11 05:07:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B48FECAAD3 for ; Wed, 31 Aug 2022 18:09:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232506AbiHaSJn (ORCPT ); Wed, 31 Aug 2022 14:09:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232481AbiHaSIq (ORCPT ); Wed, 31 Aug 2022 14:08:46 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8567E3983; Wed, 31 Aug 2022 11:08:44 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5460661C19; Wed, 31 Aug 2022 18:08:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 65BF0C433D7; Wed, 31 Aug 2022 18:08:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661969323; bh=RRltkuwJX7LP5kK/3k3rhHeIM5Hot3r7Dzu5sm7vQRo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kjEWyJtWNJyqF1sWOIQ+uxemOhBF9KufKpx8qD5bN+fkZAdqi4a7jrAo/HlErp4DX 4JrXURA91d8hkInkWBE1es3vrtKJEag1lSCmaRnzz/itVcR4MM49ZWA6Sbm0vfsvkl LOHM5808le50a4zKPFn3IrO63brm4V6tnNWJi2O6bhA0pc5h0MhAMnuebmuyonXou+ EVydrw1bfEdiLIKpA4cWmrqlj1kMnVUEf1psTVIEu7NzLvcHfSjXgazSbSDtAH45c1 A0YVzkG7josdrwFMYuKygXDRDEu9f0kfHCgrnCQ2M2/cymSWDY1wcmJYpoREFT34mN xw6vWRBUCvd3A== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Sebastian Andrzej Siewior , Thomas Gleixner , Steven Rostedt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 3/5] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK Date: Thu, 1 Sep 2022 01:59:18 +0800 Message-Id: <20220831175920.2806-4-jszhang@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org> References: <20220831175920.2806-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move POSIX CPU timer expiry and signal delivery into task context to allow PREEMPT_RT setups to coexist with KVM. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 79e52441e18b..7a8134fd7ec9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -104,6 +104,7 @@ config RISCV select HAVE_PERF_EVENTS select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP + select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_FUNCTION_ARG_ACCESS_API select HAVE_STACKPROTECTOR --=20 2.34.1 From nobody Wed Feb 11 05:07:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31072ECAAD3 for ; Wed, 31 Aug 2022 18:09:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232208AbiHaSJt (ORCPT ); Wed, 31 Aug 2022 14:09:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232226AbiHaSIx (ORCPT ); Wed, 31 Aug 2022 14:08:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2307E830A; Wed, 31 Aug 2022 11:08:48 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1166861AE4; Wed, 31 Aug 2022 18:08:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2864CC433B5; Wed, 31 Aug 2022 18:08:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661969326; bh=W2lzpMW/5Jj6EKuKqKd66scyLcYDzCh41GWmaDJ9tOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XE6JJDjFOWnsRMBMoKofgGkso8i/urjEvAUXpgznJfh64blVPBOYTJUWvgERljgGj TGPbyTL+ziZ2WVT3KokJtVD1T716DYeOtWWtYc0u1OnMiAYdRJoVwdjs/ffjj+Ob+u zKXDlhjM8Lat3rnmgHq6e2wUyOS7m67v2Pr1U9qC9f56dIVvg2R0ZyHLlIvyDoguc4 lVygxngvjtC1lKlLdY2UKk9E6qXUNypGNmGFTfWRrt46yYXVdEFYxr0db5rAknGC2w 7XlwC/0MY9nM+e8uFbogsST5RFmgPjJQ57ANWx7/Z4BG8MThBxwl6+bRpHg1Rp/NC4 7K/+rQ+lk/tPQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Sebastian Andrzej Siewior , Thomas Gleixner , Steven Rostedt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 4/5] riscv: add lazy preempt support Date: Thu, 1 Sep 2022 01:59:19 +0800 Message-Id: <20220831175920.2806-5-jszhang@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org> References: <20220831175920.2806-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement the lazy preempt for riscv. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/thread_info.h | 7 +++++-- arch/riscv/kernel/asm-offsets.c | 1 + arch/riscv/kernel/entry.S | 9 +++++++-- 4 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7a8134fd7ec9..9f2f1936b1b5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -105,6 +105,7 @@ config RISCV select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_POSIX_CPU_TIMERS_TASK_WORK + select HAVE_PREEMPT_LAZY select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_FUNCTION_ARG_ACCESS_API select HAVE_STACKPROTECTOR diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/= thread_info.h index 78933ac04995..471915b179a2 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -56,6 +56,7 @@ struct thread_info { unsigned long flags; /* low level flags */ int preempt_count; /* 0=3D>preemptible, <0=3D>BUG */ + int preempt_lazy_count; /* 0=3D>preemptible, <0=3D>BUG */ /* * These stack pointers are overwritten on every system call or * exception. SP is also saved to the stack it can be recovered when @@ -90,7 +91,7 @@ struct thread_info { #define TIF_NOTIFY_RESUME 1 /* callback before returning to user */ #define TIF_SIGPENDING 2 /* signal pending */ #define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_RESTORE_SIGMASK 4 /* restore signal mask in do_signal() */ +#define TIF_NEED_RESCHED_LAZY 4 /* lazy rescheduling */ #define TIF_MEMDIE 5 /* is terminating due to OOM killer */ #define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentat= ion */ #define TIF_SYSCALL_AUDIT 7 /* syscall auditing */ @@ -98,6 +99,7 @@ struct thread_info { #define TIF_NOTIFY_SIGNAL 9 /* signal notifications exist */ #define TIF_UPROBE 10 /* uprobe breakpoint or singlestep */ #define TIF_32BIT 11 /* compat-mode 32bit process */ +#define TIF_RESTORE_SIGMASK 12 /* restore signal mask in do_signal() */ =20 #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) @@ -108,10 +110,11 @@ struct thread_info { #define _TIF_SECCOMP (1 << TIF_SECCOMP) #define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) #define _TIF_UPROBE (1 << TIF_UPROBE) +#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY) =20 #define _TIF_WORK_MASK \ (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED | \ - _TIF_NOTIFY_SIGNAL | _TIF_UPROBE) + _TIF_NEED_RESCHED_LAZY | _TIF_NOTIFY_SIGNAL | _TIF_UPROBE) =20 #define _TIF_SYSCALL_WORK \ (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_SYSCALL_AUDIT | \ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index df9444397908..e38e33822f72 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -35,6 +35,7 @@ void asm_offsets(void) OFFSET(TASK_THREAD_S11, task_struct, thread.s[11]); OFFSET(TASK_TI_FLAGS, task_struct, thread_info.flags); OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); + OFFSET(TASK_TI_PREEMPT_LAZY_COUNT, task_struct, thread_info.preempt_lazy_= count); OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp); OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp); =20 diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index b9eda3fcbd6d..595100a4c2c7 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -361,9 +361,14 @@ restore_all: resume_kernel: REG_L s0, TASK_TI_PREEMPT_COUNT(tp) bnez s0, restore_all - REG_L s0, TASK_TI_FLAGS(tp) - andi s0, s0, _TIF_NEED_RESCHED + REG_L s1, TASK_TI_FLAGS(tp) + andi s0, s1, _TIF_NEED_RESCHED + bnez s0, 1f + REG_L s0, TASK_TI_PREEMPT_LAZY_COUNT(tp) + bnez s0, restore_all + andi s0, s1, _TIF_NEED_RESCHED_LAZY beqz s0, restore_all +1: call preempt_schedule_irq j restore_all #endif --=20 2.34.1 From nobody Wed Feb 11 05:07:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D247CECAAD3 for ; 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s=k20201202; t=1661969329; bh=xbjqcsHpZLXZwlNWH/Cbgm5wue/oCBT8GsMoqoWOFtA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W+7gVi8yFm3V3RD6T/WGbR/vDUeIq5UBo0A6wNESq7DWzBVB49wILZoyuSgVzOCC2 rnTa20DoLo7rRkJf7myG6HugA48VHkmLvis6NZ1Du7QSESk/umgnpvf2vXrs7hpfcP XziZDBydnKYKqmsb4lkoXqCo2YzHqfT3Vg0KKLdvBdR5n7ok1oBC20OV/2Jy0Nx5Xf GwT4E8whMUzEmE0dNxJVmU4FC5YW2MbREEBOpLoURCWb9WNrb4TYuXnisoNDUiVuJk gFIP+/fH7hTgzzjajJqKIIqqNdpoYbqnV6RrydBHArpNf5A7DA3vEeTsrx1Cfv5TuP g0duUCmddN/GQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Sebastian Andrzej Siewior , Thomas Gleixner , Steven Rostedt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 5/5] riscv: Allow to enable RT Date: Thu, 1 Sep 2022 01:59:20 +0800 Message-Id: <20220831175920.2806-6-jszhang@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org> References: <20220831175920.2806-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allow to select RT. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9f2f1936b1b5..69cdcb3cf251 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,6 +39,7 @@ config RISCV select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU select ARCH_SUPPORTS_HUGETLBFS if MMU select ARCH_SUPPORTS_PAGE_TABLE_CHECK if MMU + select ARCH_SUPPORTS_RT select ARCH_USE_MEMTEST select ARCH_USE_QUEUED_RWLOCKS select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU --=20 2.34.1