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[31.30.173.67]) by smtp.gmail.com with ESMTPSA id u18-20020a05600c19d200b003a5a5069107sm2618214wmq.24.2022.08.31.10.25.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 10:25:03 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH v2 1/4] riscv: Add X register names to gpr-nums Date: Wed, 31 Aug 2022 19:24:57 +0200 Message-Id: <20220831172500.752195-2-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220831172500.752195-1-ajones@ventanamicro.com> References: <20220831172500.752195-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When encoding instructions it's sometimes necessary to set a register field to a precise number. This is easiest to do using the x naming. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/gpr-num.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/gpr-num.h b/arch/riscv/include/asm/gpr-= num.h index dfee2829fc7c..efeb5edf8a3a 100644 --- a/arch/riscv/include/asm/gpr-num.h +++ b/arch/riscv/include/asm/gpr-num.h @@ -3,6 +3,11 @@ #define __ASM_GPR_NUM_H =20 #ifdef __ASSEMBLY__ + + .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24= ,25,26,27,28,29,30,31 + .equ .L__gpr_num_x\num, \num + .endr + .equ .L__gpr_num_zero, 0 .equ .L__gpr_num_ra, 1 .equ .L__gpr_num_sp, 2 @@ -39,6 +44,9 @@ #else /* __ASSEMBLY__ */ =20 #define __DEFINE_ASM_GPR_NUMS \ +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,2= 4,25,26,27,28,29,30,31\n" \ +" .equ .L__gpr_num_x\\num, \\num\n" \ +" .endr\n" \ " .equ .L__gpr_num_zero, 0\n" \ " .equ .L__gpr_num_ra, 1\n" \ " .equ .L__gpr_num_sp, 2\n" \ --=20 2.37.2 From nobody Wed Apr 8 10:33:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BD47C3DA6B for ; Wed, 31 Aug 2022 17:25:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231896AbiHaRZa (ORCPT ); Wed, 31 Aug 2022 13:25:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229842AbiHaRZL (ORCPT ); Wed, 31 Aug 2022 13:25:11 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A910B1DE for ; Wed, 31 Aug 2022 10:25:07 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id az24-20020a05600c601800b003a842e4983cso5892666wmb.0 for ; Wed, 31 Aug 2022 10:25:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=5h3L3YOiG9CNXYHQtw/et5Sc+1r6Zl/xaASBla9taYA=; b=G5vxTVeX8UktfzniDjTnkLblMXMKWgBYh+R/zA8MObo5kCtHE/4HRGHqvkVm3dHKIn Su2cvs50mNGPLJI790jlw1So7LyZSsduFO1NSGToSMmBvB5ocNz2Ox5thy9u2n1xK65e DMewhEiPnTmFiGgwHol01Lc/Pi/tFjdFNeximileSt63NdPSFbfx3L218VWWD6NkQkXg cmMZ66qsLRAc6JeYpVXYLdeg8a4BjRWRYCyRLxKEIUwjNZjmKEM+ZAOVL0GHRLJrA8vK D5LM1fvMywqOpH19URp0URi/B9NDOa2UzrJyHUyu98dzsr7lbej+ThgqjmEQCuDFKa0q 1tLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=5h3L3YOiG9CNXYHQtw/et5Sc+1r6Zl/xaASBla9taYA=; b=ZMsqPFFRki/c/W5QHNBH17GgMlw8HmWHUJl9bU7d3K21qivEziUB4QXxF93x0n8ELc TwkCV5e1iRd4NBt0xXxAVYFiNkDRLC9LCkXs6g880AxT0LjYdBeTLhDklFGT97Iajru6 4pCkCsuBrg0dKvg3oHdUg8XJpgY6egXuTKlqFE/Y60K0Puy/7H4hkSx6o02E4nBVQj4Y 5AT0UVvAzv7L8unxkowJTK5LIZW1vvb3sYfUuaJej3ADcfW0Zvo2QCTpgdZGduYtZlNA yNuhn2lMmT0g+EaOQahPJ9woy55abVxvVq0gHLqGkEEwqkrzWDhPD4rwM9Mb3Zmx0kCM o2vA== X-Gm-Message-State: ACgBeo1SVVNaDy/kINylhPZlhDH3d0RP+o1uN6DMQ27gW7bIq8mzEt0v FGlmyaWUUS3sEyWzSVOXn+8MNQ== X-Google-Smtp-Source: AA6agR7lpMuqSCKxNT4vSMdBVaSEyRIEQ+Pl2du5hdijO1YQun6REosptUuvlx9D3nXsoLSdQpx6uQ== X-Received: by 2002:a1c:4b01:0:b0:3a5:94e8:948e with SMTP id y1-20020a1c4b01000000b003a594e8948emr2653368wma.197.1661966705440; Wed, 31 Aug 2022 10:25:05 -0700 (PDT) Received: from localhost (cst2-173-67.cust.vodafone.cz. [31.30.173.67]) by smtp.gmail.com with ESMTPSA id k34-20020a05600c1ca200b003a62400724bsm3419320wms.0.2022.08.31.10.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 10:25:04 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH v2 2/4] riscv: Introduce support for defining instructions Date: Wed, 31 Aug 2022 19:24:58 +0200 Message-Id: <20220831172500.752195-3-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220831172500.752195-1-ajones@ventanamicro.com> References: <20220831172500.752195-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When compiling with toolchains that haven't yet been taught about new instructions we need to encode them ourselves. Create a new file where support for instruction definitions will evolve. We initiate the file with a macro called INSN_R(), which implements the R-type instruction encoding. INSN_R() will use the assembler's .insn directive when available, which should give the assembler a chance to do some validation. When .insn is not available we fall back to manual encoding. Not only should using instruction encoding macros improve readability and maintainability of code over the alternative of inserting instructions directly (e.g. '.word 0xc0de'), but we should also gain potential for more optimized code after compilation because the compiler will have control over the input and output registers used. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/Kconfig | 3 ++ arch/riscv/include/asm/insn-def.h | 86 +++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 arch/riscv/include/asm/insn-def.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ed66c31e4655..f8f3b316b838 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -227,6 +227,9 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SETUP_DMA_OPS select DMA_DIRECT_REMAP =20 +config AS_HAS_INSN + def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$= (comma) zero) + source "arch/riscv/Kconfig.socs" source "arch/riscv/Kconfig.erratas" =20 diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/ins= n-def.h new file mode 100644 index 000000000000..2dcd1d4781bf --- /dev/null +++ b/arch/riscv/include/asm/insn-def.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_INSN_DEF_H +#define __ASM_INSN_DEF_H + +#include + +#define INSN_R_FUNC7_SHIFT 25 +#define INSN_R_RS2_SHIFT 20 +#define INSN_R_RS1_SHIFT 15 +#define INSN_R_FUNC3_SHIFT 12 +#define INSN_R_RD_SHIFT 7 +#define INSN_R_OPCODE_SHIFT 0 + +#ifdef __ASSEMBLY__ + +#ifdef CONFIG_AS_HAS_INSN + + .macro insn_r, opcode, func3, func7, rd, rs1, rs2 + .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2 + .endm + +#else + +#include + + .macro insn_r, opcode, func3, func7, rd, rs1, rs2 + .4byte ((\opcode << INSN_R_OPCODE_SHIFT) | \ + (\func3 << INSN_R_FUNC3_SHIFT) | \ + (\func7 << INSN_R_FUNC7_SHIFT) | \ + (.L__gpr_num_\rd << INSN_R_RD_SHIFT) | \ + (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) | \ + (.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT)) + .endm + +#endif + +#define INSN_R(...) insn_r __VA_ARGS__ + +#else /* ! __ASSEMBLY__ */ + +#ifdef CONFIG_AS_HAS_INSN + +#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \ + ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" + +#else + +#include +#include + +#define DEFINE_INSN_R \ + __DEFINE_ASM_GPR_NUMS \ +" .macro insn_r, opcode, func3, func7, rd, rs1, rs2\n" \ +" .4byte ((\\opcode << " __stringify(INSN_R_OPCODE_SHIFT) ") |" \ +" (\\func3 << " __stringify(INSN_R_FUNC3_SHIFT) ") |" \ +" (\\func7 << " __stringify(INSN_R_FUNC7_SHIFT) ") |" \ +" (.L__gpr_num_\\rd << " __stringify(INSN_R_RD_SHIFT) ") |" \ +" (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |" \ +" (.L__gpr_num_\\rs2 << " __stringify(INSN_R_RS2_SHIFT) "))\n" \ +" .endm\n" + +#define UNDEFINE_INSN_R \ +" .purgem insn_r\n" + +#define INSN_R(opcode, func3, func7, rd, rs1, rs2) \ + DEFINE_INSN_R \ + "insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \ + UNDEFINE_INSN_R + +#endif + +#endif /* ! __ASSEMBLY__ */ + +#define OPCODE(v) __ASM_STR(v) +#define FUNC3(v) __ASM_STR(v) +#define FUNC7(v) __ASM_STR(v) +#define RD(v) __ASM_STR(v) +#define RS1(v) __ASM_STR(v) +#define RS2(v) __ASM_STR(v) +#define __REG(v) __ASM_STR(x ## v) +#define __RD(v) __REG(v) +#define __RS1(v) __REG(v) +#define __RS2(v) __REG(v) + +#endif /* __ASM_INSN_DEF_H */ --=20 2.37.2 From nobody Wed Apr 8 10:33:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1301CECAAD1 for ; Wed, 31 Aug 2022 17:25:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232202AbiHaRZf (ORCPT ); Wed, 31 Aug 2022 13:25:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231936AbiHaRZL (ORCPT ); Wed, 31 Aug 2022 13:25:11 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC17E13D0D for ; Wed, 31 Aug 2022 10:25:08 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id ay39-20020a05600c1e2700b003a5503a80cfso8407988wmb.2 for ; Wed, 31 Aug 2022 10:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=fizBC8NpPcL0RO1q/LLq/Re49C8DURQi6bNhDvOLByc=; b=Thjp/7LoSdR+BA8d4yQIMpuR3obWObcLBIt6v4+66n8/RxuUlNGmfr8JsCtgZr3Qkf 6SwmSnpvcy5sXxN29DLz7+SYjrCRgF8X7up11Jis86GrFvuAe/fMDfgBCrxha2l3dsj1 U5auAhYkh7aZK6d6iRezooRAPPqNdUH6xaYsfCskyMW4OV4kkhiTwucnFEc/Aa2eFrlq mFjo1g4k5Dgk27rwbVrIGryJd7B3RNrvTw4LI05x7s6O37XTLXwlSo5C+NR1rOV5O406 WajxWdao5ciVkP/uSbxsp+5D/6TcoXgYBUJMx4CLVyJMh8eMQr9sIv5EItpjBTdZmddB 8VGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=fizBC8NpPcL0RO1q/LLq/Re49C8DURQi6bNhDvOLByc=; b=QZ+iebZxB/Sib0gAh0aQKW5MeC8z+UMzISBXacejnx5UKbVcHR5WiYeHtmu6AodGyM XfHi80mL397iCRbXcDSFVgv68W26qEGGdk0ykdL0zxc+zO9vimjm6mqNj4N2UMt4zaAw Gv7OR9C2DMbSieSh4+yjnbp1vJXjz3JBUc3Zn7sdHBlhsg1aE4NYb7xDOy4pxt5tU8SI tNHlTuJ65wMbvXE4InhqpPnDWXFLQuRX8+2y8fX/Jhl9fuXkKo/Hd245SOCk3WVE17gK ieXX/jAyrcIoO0pRjSPyP5OUjGXQipSZ7NHEl8a6mDhx1Cosjr4ANHS5E8sp91QBPTDq NdVw== X-Gm-Message-State: ACgBeo1H9WbVQ23tycTlADFLv2gUkuHG4AQp6JqyDJjrX+vG1kI0iF+A ItfyIpWpL+Kbog7dUdVEKFUTww== X-Google-Smtp-Source: AA6agR5wAvxqhLqol7jiXr6Zv4bFSqdk46xUnBeQG+Zqq51F5hJLLyZGiw6lcSeEZ7PZ2SDRjRt8hw== X-Received: by 2002:a05:600c:28cd:b0:3a5:4f45:b927 with SMTP id h13-20020a05600c28cd00b003a54f45b927mr2728838wmd.90.1661966707060; Wed, 31 Aug 2022 10:25:07 -0700 (PDT) Received: from localhost (cst2-173-67.cust.vodafone.cz. [31.30.173.67]) by smtp.gmail.com with ESMTPSA id a11-20020a5d456b000000b0021f15514e7fsm14899052wrc.0.2022.08.31.10.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 10:25:06 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH v2 3/4] riscv: KVM: Apply insn-def to hfence encodings Date: Wed, 31 Aug 2022 19:24:59 +0200 Message-Id: <20220831172500.752195-4-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220831172500.752195-1-ajones@ventanamicro.com> References: <20220831172500.752195-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce hfence instruction encodings and apply them to KVM's use. With the self-documenting nature of the instruction encoding macros, and a spec always within arm's reach, it's safe to remove the comments, so we do that too. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/insn-def.h | 10 +++ arch/riscv/kvm/tlb.c | 129 ++++-------------------------- 2 files changed, 27 insertions(+), 112 deletions(-) diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/ins= n-def.h index 2dcd1d4781bf..86c1f602413b 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -83,4 +83,14 @@ #define __RS1(v) __REG(v) #define __RS2(v) __REG(v) =20 +#define OPCODE_SYSTEM OPCODE(115) + +#define HFENCE_VVMA(vaddr, asid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17), \ + __RD(0), RS1(vaddr), RS2(asid)) + +#define HFENCE_GVMA(gaddr, vmid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \ + __RD(0), RS1(gaddr), RS2(vmid)) + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 1a76d0b1907d..1ce3394b3acf 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -12,22 +12,7 @@ #include #include #include - -/* - * Instruction encoding of hfence.gvma is: - * HFENCE.GVMA rs1, rs2 - * HFENCE.GVMA zero, rs2 - * HFENCE.GVMA rs1 - * HFENCE.GVMA - * - * rs1!=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.GVMA rs1, rs2 - * rs1=3D=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.GVMA zero, rs2 - * rs1!=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.GVMA rs1 - * rs1=3D=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.GVMA - * - * Instruction encoding of HFENCE.GVMA is: - * 0110001 rs2(5) rs1(5) 000 00000 1110011 - */ +#include =20 void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid, gpa_t gpa, gpa_t gpsz, @@ -40,32 +25,14 @@ void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long= vmid, return; } =20 - for (pos =3D gpa; pos < (gpa + gpsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GPA >> 2) - * rs2 =3D a1 (VMID) - * HFENCE.GVMA a0, a1 - * 0110001 01011 01010 000 00000 1110011 - */ - asm volatile ("srli a0, %0, 2\n" - "add a1, %1, zero\n" - ".word 0x62b50073\n" - :: "r" (pos), "r" (vmid) - : "a0", "a1", "memory"); - } + for (pos =3D gpa; pos < (gpa + gpsz); pos +=3D BIT(order)) + asm volatile (HFENCE_GVMA(%0, %1) + : : "r" (pos >> 2), "r" (vmid) : "memory"); } =20 void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid) { - /* - * rs1 =3D zero - * rs2 =3D a0 (VMID) - * HFENCE.GVMA zero, a0 - * 0110001 01010 00000 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x62a00073\n" - :: "r" (vmid) : "a0", "memory"); + asm volatile(HFENCE_GVMA(zero, %0) : : "r" (vmid) : "memory"); } =20 void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz, @@ -78,46 +45,16 @@ void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t g= psz, return; } =20 - for (pos =3D gpa; pos < (gpa + gpsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GPA >> 2) - * rs2 =3D zero - * HFENCE.GVMA a0 - * 0110001 00000 01010 000 00000 1110011 - */ - asm volatile ("srli a0, %0, 2\n" - ".word 0x62050073\n" - :: "r" (pos) : "a0", "memory"); - } + for (pos =3D gpa; pos < (gpa + gpsz); pos +=3D BIT(order)) + asm volatile(HFENCE_GVMA(%0, zero) + : : "r" (pos >> 2) : "memory"); } =20 void kvm_riscv_local_hfence_gvma_all(void) { - /* - * rs1 =3D zero - * rs2 =3D zero - * HFENCE.GVMA - * 0110001 00000 00000 000 00000 1110011 - */ - asm volatile (".word 0x62000073" ::: "memory"); + asm volatile(HFENCE_GVMA(zero, zero) : : : "memory"); } =20 -/* - * Instruction encoding of hfence.gvma is: - * HFENCE.VVMA rs1, rs2 - * HFENCE.VVMA zero, rs2 - * HFENCE.VVMA rs1 - * HFENCE.VVMA - * - * rs1!=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.VVMA rs1, rs2 - * rs1=3D=3Dzero and rs2!=3Dzero =3D=3D> HFENCE.VVMA zero, rs2 - * rs1!=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.VVMA rs1 - * rs1=3D=3Dzero and rs2=3D=3Dzero =3D=3D> HFENCE.VVMA - * - * Instruction encoding of HFENCE.VVMA is: - * 0010001 rs2(5) rs1(5) 000 00000 1110011 - */ - void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid, unsigned long asid, unsigned long gva, @@ -133,19 +70,9 @@ void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long= vmid, =20 hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 - for (pos =3D gva; pos < (gva + gvsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GVA) - * rs2 =3D a1 (ASID) - * HFENCE.VVMA a0, a1 - * 0010001 01011 01010 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - "add a1, %1, zero\n" - ".word 0x22b50073\n" - :: "r" (pos), "r" (asid) - : "a0", "a1", "memory"); - } + for (pos =3D gva; pos < (gva + gvsz); pos +=3D BIT(order)) + asm volatile(HFENCE_VVMA(%0, %1) + : : "r" (pos), "r" (asid) : "memory"); =20 csr_write(CSR_HGATP, hgatp); } @@ -157,15 +84,7 @@ void kvm_riscv_local_hfence_vvma_asid_all(unsigned long= vmid, =20 hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 - /* - * rs1 =3D zero - * rs2 =3D a0 (ASID) - * HFENCE.VVMA zero, a0 - * 0010001 01010 00000 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x22a00073\n" - :: "r" (asid) : "a0", "memory"); + asm volatile(HFENCE_VVMA(zero, %0) : : "r" (asid) : "memory"); =20 csr_write(CSR_HGATP, hgatp); } @@ -183,17 +102,9 @@ void kvm_riscv_local_hfence_vvma_gva(unsigned long vmi= d, =20 hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 - for (pos =3D gva; pos < (gva + gvsz); pos +=3D BIT(order)) { - /* - * rs1 =3D a0 (GVA) - * rs2 =3D zero - * HFENCE.VVMA a0 - * 0010001 00000 01010 000 00000 1110011 - */ - asm volatile ("add a0, %0, zero\n" - ".word 0x22050073\n" - :: "r" (pos) : "a0", "memory"); - } + for (pos =3D gva; pos < (gva + gvsz); pos +=3D BIT(order)) + asm volatile(HFENCE_VVMA(%0, zero) + : : "r" (pos) : "memory"); =20 csr_write(CSR_HGATP, hgatp); } @@ -204,13 +115,7 @@ void kvm_riscv_local_hfence_vvma_all(unsigned long vmi= d) =20 hgatp =3D csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT); =20 - /* - * rs1 =3D zero - * rs2 =3D zero - * HFENCE.VVMA - * 0010001 00000 00000 000 00000 1110011 - */ - asm volatile (".word 0x22000073" ::: "memory"); + asm volatile(HFENCE_VVMA(zero, zero) : : : "memory"); =20 csr_write(CSR_HGATP, hgatp); } --=20 2.37.2 From nobody Wed Apr 8 10:33:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA9BCECAAD1 for ; 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[31.30.173.67]) by smtp.gmail.com with ESMTPSA id ay21-20020a05600c1e1500b003a536d5aa2esm2838222wmb.11.2022.08.31.10.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 10:25:08 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, anup@brainfault.org, mchitale@ventanamicro.com, heiko@sntech.de Subject: [PATCH v2 4/4] riscv: KVM: Apply insn-def to hlv encodings Date: Wed, 31 Aug 2022 19:25:00 +0200 Message-Id: <20220831172500.752195-5-ajones@ventanamicro.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220831172500.752195-1-ajones@ventanamicro.com> References: <20220831172500.752195-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce hlv instruction encodings and apply them to KVM's use. We're careful not to introduce hlv.d to 32-bit builds. Indeed, we ensure the build fails if someone tries to use it. Signed-off-by: Andrew Jones Reviewed-by: Anup Patel --- arch/riscv/include/asm/insn-def.h | 17 +++++++++++++++++ arch/riscv/kvm/vcpu_exit.c | 29 +++++------------------------ 2 files changed, 22 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/ins= n-def.h index 86c1f602413b..8fe9036efb68 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -93,4 +93,21 @@ INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \ __RD(0), RS1(gaddr), RS2(vmid)) =20 +#define HLVX_HU(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(50), \ + RD(dest), RS1(addr), __RS2(3)) + +#define HLV_W(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(52), \ + RD(dest), RS1(addr), __RS2(0)) + +#ifdef CONFIG_64BIT +#define HLV_D(dest, addr) \ + INSN_R(OPCODE_SYSTEM, FUNC3(4), FUNC7(54), \ + RD(dest), RS1(addr), __RS2(0)) +#else +#define HLV_D(dest, addr) \ + __ASM_STR(.error "hlv.d requires 64-bit support") +#endif + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index d5c36386878a..da793f113a72 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 static int gstage_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run, struct kvm_cpu_trap *trap) @@ -82,22 +83,12 @@ unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcp= u *vcpu, ".option push\n" ".option norvc\n" "add %[ttmp], %[taddr], 0\n" - /* - * HLVX.HU %[val], (%[addr]) - * HLVX.HU t0, (t2) - * 0110010 00011 00111 100 00101 1110011 - */ - ".word 0x6433c2f3\n" + HLVX_HU(%[val], %[addr]) "andi %[tmp], %[val], 3\n" "addi %[tmp], %[tmp], -3\n" "bne %[tmp], zero, 2f\n" "addi %[addr], %[addr], 2\n" - /* - * HLVX.HU %[tmp], (%[addr]) - * HLVX.HU t1, (t2) - * 0110010 00011 00111 100 00110 1110011 - */ - ".word 0x6433c373\n" + HLVX_HU(%[tmp], %[addr]) "sll %[tmp], %[tmp], 16\n" "add %[val], %[val], %[tmp]\n" "2:\n" @@ -121,19 +112,9 @@ unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vc= pu *vcpu, ".option norvc\n" "add %[ttmp], %[taddr], 0\n" #ifdef CONFIG_64BIT - /* - * HLV.D %[val], (%[addr]) - * HLV.D t0, (t2) - * 0110110 00000 00111 100 00101 1110011 - */ - ".word 0x6c03c2f3\n" + HLV_D(%[val], %[addr]) #else - /* - * HLV.W %[val], (%[addr]) - * HLV.W t0, (t2) - * 0110100 00000 00111 100 00101 1110011 - */ - ".word 0x6803c2f3\n" + HLV_W(%[val], %[addr]) #endif ".option pop" : [val] "=3D&r" (val), --=20 2.37.2