From nobody Tue Apr 7 04:19:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9F74ECAAD4 for ; Wed, 31 Aug 2022 00:01:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230518AbiHaABD (ORCPT ); Tue, 30 Aug 2022 20:01:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229685AbiHaAA5 (ORCPT ); Tue, 30 Aug 2022 20:00:57 -0400 Received: from mail-pj1-x1049.google.com (mail-pj1-x1049.google.com [IPv6:2607:f8b0:4864:20::1049]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47125659F0 for ; Tue, 30 Aug 2022 17:00:56 -0700 (PDT) Received: by mail-pj1-x1049.google.com with SMTP id c17-20020a17090ad91100b001fdb29e1943so3109766pjv.0 for ; Tue, 30 Aug 2022 17:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc; bh=vo5HdwRPjV6Nw++vuMl/iEPDJH4m1OFL3i5pfdtXoVE=; b=Djuq1dwHroOnQMQJ3UVirD/6ihOvXXj1ckAIf1EOYJDaxNuanAHVo827cEL2o4/Nb8 mqplmhj7jxCZ0vMvojiQth3c7E0kBTGWG4K9/7bOE75vCjprxG7+fAHKLyfeF6YlULtm y/5+zEqsBTaZR/8IkBQnEBu5ZmBFi0fW41NOVgpdywtBHBpeFGx66WIrT78dlom7Hinp ElCeCcdjGisfx8p4V4EwNh/+m8Qf5Xpn4bBCagGSeZmw8Z9BIWBSolh20CvzNtQN94VC vXbCNoTAHTHmkN426naO9FoD6WCtxDaLTdneAAWLAxrOOIYcHYfwjBvWJ0tgS+txafWN jzFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc; bh=vo5HdwRPjV6Nw++vuMl/iEPDJH4m1OFL3i5pfdtXoVE=; b=7gE7WmmBzTNRaMZxAkDrh4q1HqcHmlrQ50eM/1N3rJpgDa3wt51TDSkhAIITb9m0Wa PSPwCUDjmDbOXXYHMUiugyBIjQuqAnr0sQPBuTVwrlj0z3cVZHIetIdjkrxweKrxfzxV nJSdaCiNZQNc6u2hlX+65fInJ9L3p5sR4SojuF+YfDQ/WujXcBXRlCRgfey/RlmqE4ON IMuQJYNVtwCielTh/ismqtAstm90xuymOddGBGvrgwzM3e97+Phgi4kSlgzCJF4Zyxqk WXsoX43yVJ4M+lxYrIq5Hu6SkT6M4Ujcz9GxAgijjJcOqc/nb/Bpggav0xXCnz0TtECG sjrw== X-Gm-Message-State: ACgBeo1sgbrk35M44CCYpKEetgMDBVvQsSwmMAzhjvOVD0KwfUAqmtie KE52ISRymKdQjpwg5ntmm/8rtA3p2Ug= X-Google-Smtp-Source: AA6agR5m+62T7xHSzPIU2GAafdzd2hDCL8JP1w40ZoO3eUABfskgZ+ViDXGRJuTI6f9RjxggnW67RBjMx4c= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:e884:b0:174:9834:53 with SMTP id w4-20020a170902e88400b0017498340053mr14868368plg.2.1661904055854; Tue, 30 Aug 2022 17:00:55 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 31 Aug 2022 00:00:49 +0000 In-Reply-To: <20220831000051.4015031-1-seanjc@google.com> Mime-Version: 1.0 References: <20220831000051.4015031-1-seanjc@google.com> X-Mailer: git-send-email 2.37.2.672.g94769d06f0-goog Message-ID: <20220831000051.4015031-2-seanjc@google.com> Subject: [PATCH v3 1/3] perf/x86/core: Remove unnecessary stubs provided for KVM-only helpers From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove CONFIG_PERF_EVENT=3Dn stubs for functions that are effectively KVM-only. KVM selects PERF_EVENT and will never consume the stubs. Dropping the unnecessary stubs will allow simplifying x86_perf_get_lbr() by getting rid of the impossible-to-hit error path (which KVM doesn't even check). Opportunstically reorganize the declarations to collapse multiple CONFIG_PERF_EVENTS #ifdefs. Signed-off-by: Sean Christopherson --- arch/x86/include/asm/perf_event.h | 53 ++++++++----------------------- 1 file changed, 13 insertions(+), 40 deletions(-) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index f6fc8dd51ef4..f839eb55f298 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -525,46 +525,18 @@ extern u64 perf_get_hw_event_config(int hw_event); extern void perf_check_microcode(void); extern void perf_clear_dirty_counters(void); extern int x86_perf_rdpmc_index(struct perf_event *event); -#else -static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *= cap) -{ - memset(cap, 0, sizeof(*cap)); -} =20 -static inline u64 perf_get_hw_event_config(int hw_event) -{ - return 0; -} - -static inline void perf_events_lapic_init(void) { } -static inline void perf_check_microcode(void) { } -#endif - -#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) +#ifdef CONFIG_CPU_SUP_INTEL extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *da= ta); extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr); -#else -struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data); -static inline int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) -{ - return -1; -} -#endif +extern void intel_pt_handle_vmx(int on); +#endif /* CONFIG_CPU_SUP_INTEL */ =20 -#ifdef CONFIG_CPU_SUP_INTEL - extern void intel_pt_handle_vmx(int on); -#else -static inline void intel_pt_handle_vmx(int on) -{ +#ifdef CONFIG_CPU_SUP_AMD +extern void amd_pmu_enable_virt(void); +extern void amd_pmu_disable_virt(void); =20 -} -#endif - -#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) - extern void amd_pmu_enable_virt(void); - extern void amd_pmu_disable_virt(void); - -#if defined(CONFIG_PERF_EVENTS_AMD_BRS) +#ifdef CONFIG_PERF_EVENTS_AMD_BRS =20 #define PERF_NEEDS_LOPWR_CB 1 =20 @@ -582,12 +554,13 @@ static inline void perf_lopwr_cb(bool lopwr_in) static_call_mod(perf_lopwr_cb)(lopwr_in); } =20 -#endif /* PERF_NEEDS_LOPWR_CB */ +#endif /* CONFIG_PERF_EVENTS_AMD_BRS */ +#endif /* CONFIG_CPU_SUP_AMD */ =20 -#else - static inline void amd_pmu_enable_virt(void) { } - static inline void amd_pmu_disable_virt(void) { } -#endif +#else /* !CONFIG_PERF_EVENTS */ +static inline void perf_events_lapic_init(void) { } +static inline void perf_check_microcode(void) { } +#endif /* CONFIG_PERF_EVENTS */ =20 #define arch_perf_out_copy_user copy_from_user_nmi =20 --=20 2.37.2.672.g94769d06f0-goog From nobody Tue Apr 7 04:19:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47B80ECAAD4 for ; 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Tue, 30 Aug 2022 17:00:57 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 31 Aug 2022 00:00:50 +0000 In-Reply-To: <20220831000051.4015031-1-seanjc@google.com> Mime-Version: 1.0 References: <20220831000051.4015031-1-seanjc@google.com> X-Mailer: git-send-email 2.37.2.672.g94769d06f0-goog Message-ID: <20220831000051.4015031-3-seanjc@google.com> Subject: [PATCH v3 2/3] perf/x86/core: Drop the unnecessary return value from x86_perf_get_lbr() From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the return value from x86_perf_get_lbr() now that there's no stub, i.e. now that success is guaranteed (which is a bit of a lie since success was always guaranteed, it's just more obvious now). Signed-off-by: Sean Christopherson --- arch/x86/events/intel/lbr.c | 6 +----- arch/x86/include/asm/perf_event.h | 2 +- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 4f70fb6c2c1e..b8ad31c52cf0 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1868,10 +1868,8 @@ void __init intel_pmu_arch_lbr_init(void) * x86_perf_get_lbr - get the LBR records information * * @lbr: the caller's memory to store the LBR records information - * - * Returns: 0 indicates the LBR info has been successfully obtained */ -int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) +void x86_perf_get_lbr(struct x86_pmu_lbr *lbr) { int lbr_fmt =3D x86_pmu.intel_cap.lbr_format; =20 @@ -1879,8 +1877,6 @@ int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) lbr->from =3D x86_pmu.lbr_from; lbr->to =3D x86_pmu.lbr_to; lbr->info =3D (lbr_fmt =3D=3D LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0; - - return 0; } EXPORT_SYMBOL_GPL(x86_perf_get_lbr); =20 diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index f839eb55f298..f6d9230cdfab 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -528,7 +528,7 @@ extern int x86_perf_rdpmc_index(struct perf_event *even= t); =20 #ifdef CONFIG_CPU_SUP_INTEL extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *da= ta); -extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr); +extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr); extern void intel_pt_handle_vmx(int on); #endif /* CONFIG_CPU_SUP_INTEL */ =20 --=20 2.37.2.672.g94769d06f0-goog From nobody Tue Apr 7 04:19:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62D84ECAAD4 for ; Wed, 31 Aug 2022 00:01:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231588AbiHaABN (ORCPT ); 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Tue, 30 Aug 2022 17:00:59 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 31 Aug 2022 00:00:51 +0000 In-Reply-To: <20220831000051.4015031-1-seanjc@google.com> Mime-Version: 1.0 References: <20220831000051.4015031-1-seanjc@google.com> X-Mailer: git-send-email 2.37.2.672.g94769d06f0-goog Message-ID: <20220831000051.4015031-4-seanjc@google.com> Subject: [PATCH v3 3/3] KVM: VMX: Advertise PMU LBRs if and only if perf supports LBRs From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Advertise LBR support to userspace via MSR_IA32_PERF_CAPABILITIES if and only if perf fully supports LBRs. Perf may disable LBRs (by zeroing the number of LBRs) even on platforms the allegedly support LBRs, e.g. if probing any LBR MSRs during setup fails. Fixes: be635e34c284 ("KVM: vmx/pmu: Expose LBR_FMT in the MSR_IA32_PERF_CAP= ABILITIES") Reported-by: Like Xu Signed-off-by: Sean Christopherson Reported-by: kernel test robot --- arch/x86/kvm/vmx/capabilities.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index c5e5dfef69c7..d2fdaf888d33 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -404,6 +404,7 @@ static inline bool vmx_pebs_supported(void) static inline u64 vmx_get_perf_capabilities(void) { u64 perf_cap =3D PMU_CAP_FW_WRITES; + struct x86_pmu_lbr lbr; u64 host_perf_cap =3D 0; =20 if (!enable_pmu) @@ -412,7 +413,9 @@ static inline u64 vmx_get_perf_capabilities(void) if (boot_cpu_has(X86_FEATURE_PDCM)) rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); =20 - perf_cap |=3D host_perf_cap & PMU_CAP_LBR_FMT; + x86_perf_get_lbr(&lbr); + if (lbr.nr) + perf_cap |=3D host_perf_cap & PMU_CAP_LBR_FMT; =20 if (vmx_pebs_supported()) { perf_cap |=3D host_perf_cap & PERF_CAP_PEBS_MASK; --=20 2.37.2.672.g94769d06f0-goog