From nobody Tue Apr 7 07:05:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 714D5ECAAA1 for ; Tue, 30 Aug 2022 23:57:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231167AbiH3X5C (ORCPT ); Tue, 30 Aug 2022 19:57:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231717AbiH3X4j (ORCPT ); Tue, 30 Aug 2022 19:56:39 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7AF271BF8 for ; Tue, 30 Aug 2022 16:55:54 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id q7-20020a63e947000000b004297f1e1f86so6197069pgj.12 for ; Tue, 30 Aug 2022 16:55:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc; bh=Djp3CXhw97imusM87qiMQnhEDBYlX/mb/nkPMjzyLGc=; b=RcXGoYFdqVscbUJ83ofAPJuLPdh5Y43S2GvyFTmMbuLk8YKjr2uRLfFJ2wKT+wkPFN /3YVCWJMNvTZG0O3MDKPGMXfDmWGDfL+USqDAMoh/Ppzu8Pu5SzZrX3kNOvJ1MapzB50 eqnAyUGDpVcf+046aPpiiOEB6kLPzaOVRXBeCSmFY5cYmod+Klcuye1PDX89IjPB7ToF XLxSesmFTk8WN6mlxXM1NTk0Atuu+3FCR72Owz3WpQ8SpOlewzb85nMOILh3BdEVgf9Z j5z1C5o6h0IBW0Q2MVenfN2MSgSrOq0JFszq/3JpLyBjrFpsi/muF3iNopOwN9gXEPQe hnOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc; bh=Djp3CXhw97imusM87qiMQnhEDBYlX/mb/nkPMjzyLGc=; b=67JTfEtzzOGAOr42JskWYs1PNKd2zT/TCh7Du6T+5Tfe0ocx8745ujMkmDL8/D/Akc IeGIvrLBUcvSCIorJfNiDPT1KnszlKvPyOoJPZJBjyj6c05sS0oSzvSIUR924VkoV6PE 7eavhaomjmJ7JuI/pAd83Wu7u0lY82CTWcpm3GAN6F1i24M3A+UFmir5o7Gzq9f+/y9t o9w+aDy0rgmFT/p2fWRcefY7qOX/Wms/N0p8OtBRRZ3bin1yRR+fmJBa/29TgvlS7YZv QTi1h6BrA8204bXG9qpcigSdj3UU3+eDuNIp182Xoqdx+0vPrTDvHHTxT+AbhlIZ0LWp fcKA== X-Gm-Message-State: ACgBeo1ds6qaXLstw3xUG88DvQCHg4X+htP7lV3eULzigQ5z4DNYKh7o QllN22cQSr16qpzUuWYmS2ZuMtiAuhY= X-Google-Smtp-Source: AA6agR5qvKfNO3A+YaO7bFe5xrcBFzFnWapEEKvmJAxGpy4+c5IU9DOBxOYlUNevzADEpUnEeymJXH35EoQ= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:e883:b0:175:22e8:f30a with SMTP id w3-20020a170902e88300b0017522e8f30amr4430989plg.127.1661903753536; Tue, 30 Aug 2022 16:55:53 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 30 Aug 2022 23:55:36 +0000 In-Reply-To: <20220830235537.4004585-1-seanjc@google.com> Mime-Version: 1.0 References: <20220830235537.4004585-1-seanjc@google.com> X-Mailer: git-send-email 2.37.2.672.g94769d06f0-goog Message-ID: <20220830235537.4004585-9-seanjc@google.com> Subject: [PATCH v4 8/9] KVM: x86/mmu: Add helper to convert SPTE value to its shadow page From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, David Matlack , Mingwei Zhang , Yan Zhao , Ben Gardon Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a helper to convert a SPTE to its shadow page to deduplicate a variety of flows and hopefully avoid future bugs, e.g. if KVM attempts to get the shadow page for a SPTE without dropping high bits. Opportunistically add a comment in mmu_free_root_page() documenting why it treats the root HPA as a SPTE. No functional change intended. Signed-off-by: Sean Christopherson --- arch/x86/kvm/mmu/mmu.c | 17 ++++++++++------- arch/x86/kvm/mmu/mmu_internal.h | 12 ------------ arch/x86/kvm/mmu/spte.h | 17 +++++++++++++++++ arch/x86/kvm/mmu/tdp_mmu.h | 2 ++ 4 files changed, 29 insertions(+), 19 deletions(-) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index de06c1f87635..4737da767a40 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -1808,7 +1808,7 @@ static int __mmu_unsync_walk(struct kvm_mmu_page *sp, continue; } =20 - child =3D to_shadow_page(ent & SPTE_BASE_ADDR_MASK); + child =3D spte_to_child_sp(ent); =20 if (child->unsync_children) { if (mmu_pages_add(pvec, child, i)) @@ -2367,7 +2367,7 @@ static void validate_direct_spte(struct kvm_vcpu *vcp= u, u64 *sptep, * so we should update the spte at this point to get * a new sp with the correct access. */ - child =3D to_shadow_page(*sptep & SPTE_BASE_ADDR_MASK); + child =3D spte_to_child_sp(*sptep); if (child->role.access =3D=3D direct_access) return; =20 @@ -2388,7 +2388,7 @@ static int mmu_page_zap_pte(struct kvm *kvm, struct k= vm_mmu_page *sp, if (is_last_spte(pte, sp->role.level)) { drop_spte(kvm, spte); } else { - child =3D to_shadow_page(pte & SPTE_BASE_ADDR_MASK); + child =3D spte_to_child_sp(pte); drop_parent_pte(child, spte); =20 /* @@ -2827,7 +2827,7 @@ static int mmu_set_spte(struct kvm_vcpu *vcpu, struct= kvm_memory_slot *slot, struct kvm_mmu_page *child; u64 pte =3D *sptep; =20 - child =3D to_shadow_page(pte & SPTE_BASE_ADDR_MASK); + child =3D spte_to_child_sp(pte); drop_parent_pte(child, sptep); flush =3D true; } else if (pfn !=3D spte_to_pfn(*sptep)) { @@ -3439,7 +3439,11 @@ static void mmu_free_root_page(struct kvm *kvm, hpa_= t *root_hpa, if (!VALID_PAGE(*root_hpa)) return; =20 - sp =3D to_shadow_page(*root_hpa & SPTE_BASE_ADDR_MASK); + /* + * The "root" may be a special root, e.g. a PAE entry, treat it as a + * SPTE to ensure any non-PA bits are dropped. + */ + sp =3D spte_to_child_sp(*root_hpa); if (WARN_ON(!sp)) return; =20 @@ -3924,8 +3928,7 @@ void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) hpa_t root =3D vcpu->arch.mmu->pae_root[i]; =20 if (IS_VALID_PAE_ROOT(root)) { - root &=3D SPTE_BASE_ADDR_MASK; - sp =3D to_shadow_page(root); + sp =3D spte_to_child_sp(root); mmu_sync_children(vcpu, sp, true); } } diff --git a/arch/x86/kvm/mmu/mmu_internal.h b/arch/x86/kvm/mmu/mmu_interna= l.h index 22152241bd29..dbaf6755c5a7 100644 --- a/arch/x86/kvm/mmu/mmu_internal.h +++ b/arch/x86/kvm/mmu/mmu_internal.h @@ -133,18 +133,6 @@ struct kvm_mmu_page { =20 extern struct kmem_cache *mmu_page_header_cache; =20 -static inline struct kvm_mmu_page *to_shadow_page(hpa_t shadow_page) -{ - struct page *page =3D pfn_to_page(shadow_page >> PAGE_SHIFT); - - return (struct kvm_mmu_page *)page_private(page); -} - -static inline struct kvm_mmu_page *sptep_to_sp(u64 *sptep) -{ - return to_shadow_page(__pa(sptep)); -} - static inline int kvm_mmu_role_as_id(union kvm_mmu_page_role role) { return role.smm ? 1 : 0; diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h index 7670c13ce251..7e5343339b90 100644 --- a/arch/x86/kvm/mmu/spte.h +++ b/arch/x86/kvm/mmu/spte.h @@ -219,6 +219,23 @@ static inline int spte_index(u64 *sptep) */ extern u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; =20 +static inline struct kvm_mmu_page *to_shadow_page(hpa_t shadow_page) +{ + struct page *page =3D pfn_to_page((shadow_page) >> PAGE_SHIFT); + + return (struct kvm_mmu_page *)page_private(page); +} + +static inline struct kvm_mmu_page *spte_to_child_sp(u64 spte) +{ + return to_shadow_page(spte & SPTE_BASE_ADDR_MASK); +} + +static inline struct kvm_mmu_page *sptep_to_sp(u64 *sptep) +{ + return to_shadow_page(__pa(sptep)); +} + static inline bool is_mmio_spte(u64 spte) { return (spte & shadow_mmio_mask) =3D=3D shadow_mmio_value && diff --git a/arch/x86/kvm/mmu/tdp_mmu.h b/arch/x86/kvm/mmu/tdp_mmu.h index c163f7cc23ca..d3714200b932 100644 --- a/arch/x86/kvm/mmu/tdp_mmu.h +++ b/arch/x86/kvm/mmu/tdp_mmu.h @@ -5,6 +5,8 @@ =20 #include =20 +#include "spte.h" + hpa_t kvm_tdp_mmu_get_vcpu_root_hpa(struct kvm_vcpu *vcpu); =20 __must_check static inline bool kvm_tdp_mmu_get_root(struct kvm_mmu_page *= root) --=20 2.37.2.672.g94769d06f0-goog