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([171.76.81.23]) by smtp.gmail.com with ESMTPSA id y27-20020a634b1b000000b0041cd5ddde6fsm592240pga.76.2022.08.29.21.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 21:47:33 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v2 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Date: Tue, 30 Aug 2022 10:16:39 +0530 Message-Id: <20220830044642.566769-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220830044642.566769-1-apatel@ventanamicro.com> References: <20220830044642.566769-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, all flavors of ioremap_xyz() function maps to the generic ioremap() which means any ioremap_xyz() call will always map the target memory as IO using _PAGE_IOREMAP page attributes. This breaks ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP page attributes. To address above (just like other architectures), we implement RISC-V specific ioremap_cache() and ioremap_wc() which maps memory using page attributes as defined by the Svpbmt specification. Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/include/asm/io.h | 10 ++++++++++ arch/riscv/include/asm/pgtable.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 69605a474270..07ac63999575 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -133,6 +133,16 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, c= ount) #endif =20 +#ifdef CONFIG_MMU +#define ioremap_wc(addr, size) \ + ioremap_prot((addr), (size), _PAGE_IOREMAP_WC) +#endif + #include =20 +#ifdef CONFIG_MMU +#define ioremap_cache(addr, size) \ + ioremap_prot((addr), (size), _PAGE_KERNEL) +#endif + #endif /* _ASM_RISCV_IO_H */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 7ec936910a96..346b7c1a3eeb 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -182,6 +182,8 @@ extern struct pt_alloc_ops pt_ops __initdata; #define PAGE_TABLE __pgprot(_PAGE_TABLE) =20 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) +#define _PAGE_IOREMAP_WC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | \ + _PAGE_NOCACHE) #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) =20 extern pgd_t swapper_pg_dir[]; --=20 2.34.1 From nobody Tue Apr 7 07:08:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCAB3ECAAD5 for ; Tue, 30 Aug 2022 04:47:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229951AbiH3Ert (ORCPT ); Tue, 30 Aug 2022 00:47:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229908AbiH3Erj (ORCPT ); Tue, 30 Aug 2022 00:47:39 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30E95ACA1C for ; Mon, 29 Aug 2022 21:47:38 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id t129so10217047pfb.6 for ; Mon, 29 Aug 2022 21:47:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vtPor/JINehJpJFz1SJxkilKXT4UTOKJym5PpR3Plyk=; b=KLp7YXcUffNSRJEbHo1U1gFf2nnUmwcycrLDg1hpm4yGoo8eT6ngd5n7pJlrXiBTfk j9mnZNlk/zsBbPEOgU3W+ROlFAHnTuHqXnzV/oofvNyRSPOyvcx91nVFrWKSVynCcPQO Yozf5ttY5wiN4KYbGgaGXYPQihD5M8YpjS8/gPwI8uEgq/W+mOeS+ezvte8NW6wcjCSF rCNcKS5RQDnSnMsHqNs5otYgdI2seYwWH7idJpYGeH1+Ka7AwhCj4uHSxf/VZ4qdRiOg QjG/bvyS1x4sWKWaVmNPZ4nPdw/DqZ2phPArkK5QGPNK2wavVtdSzz1cqCr6qgUPLu0s kCug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vtPor/JINehJpJFz1SJxkilKXT4UTOKJym5PpR3Plyk=; b=rJ2t28+OhVY5RXi/QGx7hlcr0zceMoryCzmvn51PaY81Qj60Lxw0dpKHsNFmDLFOIo swo0bnOO4yNNMKVoRNm2bhkjzS+LKTpbfHNSbV4bwtrHPyJjHgFRb3L/QarPY24EKMjB UMHVZ5Nc6/tTJ7EvCaFdSGF3dpLoHkOAFS1eq1ZzfwdHhS49gc02a1e6LQ8BQxD0kN6A 1jzF3JY6ReNf7s0qwd18RNadhFqA8QWoo7e12jMGTVLOyUgbEZjhngA9gBKb7JKzKKSG WLOZc8etklctArIuR4SUzj/tVwa4Lecmr3/NNtL4EqXEJ+VHgAwWhKo7Gco8a2+fd6gM WCNw== X-Gm-Message-State: ACgBeo2AE9P78pWgnf9mPQgazEiGP/LriWyqo6M1SE+ZvWg1zUmbl4Qv +xJtp6l74zaoQoot+VRjTNZTNKjdVV5z+A== X-Google-Smtp-Source: AA6agR4rh3ksVh2lnb3HasNfLMlOM72aYIH5s+vR9Vg3+NK7D0dv/gqNDtx+6K1K/D/vdy0w0onD2Q== X-Received: by 2002:a63:ad02:0:b0:41a:910f:5195 with SMTP id g2-20020a63ad02000000b0041a910f5195mr16829161pgf.472.1661834857629; Mon, 29 Aug 2022 21:47:37 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.81.23]) by smtp.gmail.com with ESMTPSA id y27-20020a634b1b000000b0041cd5ddde6fsm592240pga.76.2022.08.29.21.47.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 21:47:37 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v2 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c Date: Tue, 30 Aug 2022 10:16:40 +0530 Message-Id: <20220830044642.566769-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220830044642.566769-1-apatel@ventanamicro.com> References: <20220830044642.566769-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The riscv_cbom_block_size parsing from DT belongs to cacheflush.c which is home for all cache maintenance related stuff so let us move the riscv_init_cbom_blocksize() and riscv_cbom_block_size to cacheflush.c. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/include/asm/cacheflush.h | 2 ++ arch/riscv/mm/cacheflush.c | 39 +++++++++++++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 38 ---------------------------- 3 files changed, 41 insertions(+), 38 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/c= acheflush.h index a60acaecfeda..de55d6b8deeb 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -42,6 +42,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); =20 #endif /* CONFIG_SMP */ =20 +extern unsigned int riscv_cbom_block_size; + #ifdef CONFIG_RISCV_ISA_ZICBOM void riscv_init_cbom_blocksize(void); #else diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..336c5deea870 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -3,6 +3,8 @@ * Copyright (C) 2017 SiFive */ =20 +#include +#include #include =20 #ifdef CONFIG_SMP @@ -86,3 +88,40 @@ void flush_icache_pte(pte_t pte) flush_icache_all(); } #endif /* CONFIG_MMU */ + +unsigned int riscv_cbom_block_size =3D L1_CACHE_BYTES; + +#ifdef CONFIG_RISCV_ISA_ZICBOM +void riscv_init_cbom_blocksize(void) +{ + struct device_node *node; + int ret; + u32 val; + + for_each_of_cpu_node(node) { + unsigned long hartid; + int cbom_hartid; + + ret =3D riscv_of_processor_hartid(node, &hartid); + if (ret) + continue; + + if (hartid < 0) + continue; + + /* set block-size for cbom extension if available */ + ret =3D of_property_read_u32(node, "riscv,cbom-block-size", &val); + if (ret) + continue; + + if (!riscv_cbom_block_size) { + riscv_cbom_block_size =3D val; + cbom_hartid =3D hartid; + } else { + if (riscv_cbom_block_size !=3D val) + pr_warn("cbom-block-size mismatched between harts %d and %lu\n", + cbom_hartid, hartid); + } + } +} +#endif diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoheren= t.c index cd2225304c82..3f502a1a68b1 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -8,11 +8,8 @@ #include #include #include -#include -#include #include =20 -static unsigned int riscv_cbom_block_size =3D L1_CACHE_BYTES; static bool noncoherent_supported; =20 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, @@ -75,41 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base= , u64 size, dev->dma_coherent =3D coherent; } =20 -#ifdef CONFIG_RISCV_ISA_ZICBOM -void riscv_init_cbom_blocksize(void) -{ - struct device_node *node; - int ret; - u32 val; - - for_each_of_cpu_node(node) { - unsigned long hartid; - int cbom_hartid; - - ret =3D riscv_of_processor_hartid(node, &hartid); - if (ret) - continue; - - if (hartid < 0) - continue; - - /* set block-size for cbom extension if available */ - ret =3D of_property_read_u32(node, "riscv,cbom-block-size", &val); - if (ret) - continue; - - if (!riscv_cbom_block_size) { - riscv_cbom_block_size =3D val; - cbom_hartid =3D hartid; - } else { - if (riscv_cbom_block_size !=3D val) - pr_warn("cbom-block-size mismatched between harts %d and %lu\n", - cbom_hartid, hartid); - } - } -} -#endif - void riscv_noncoherent_supported(void) { noncoherent_supported =3D true; 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([171.76.81.23]) by smtp.gmail.com with ESMTPSA id y27-20020a634b1b000000b0041cd5ddde6fsm592240pga.76.2022.08.29.21.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 21:47:40 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v2 3/4] RISC-V: Implement arch specific PMEM APIs Date: Tue, 30 Aug 2022 10:16:41 +0530 Message-Id: <20220830044642.566769-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220830044642.566769-1-apatel@ventanamicro.com> References: <20220830044642.566769-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The NVDIMM PMEM driver expects arch specific APIs for cache maintenance and if arch does not provide these APIs then NVDIMM PMEM driver will always use MEMREMAP_WT to map persistent memory which in-turn maps as UC memory type defined by the RISC-V Svpbmt specification. Now that the Svpbmt and Zicbom support is available in RISC-V kernel, we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMM PMEM driver can use MEMREMAP_WB to map persistent memory. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/pmem.c | 21 +++++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/riscv/mm/pmem.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0ebd8da388d8..37d6370d29c3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -25,6 +25,7 @@ config RISCV select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_KCOV select ARCH_HAS_MMIOWB + select ARCH_HAS_PMEM_API select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index d76aabf4b94d..3b368e547f83 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -31,3 +31,4 @@ endif =20 obj-$(CONFIG_DEBUG_VIRTUAL) +=3D physaddr.o obj-$(CONFIG_RISCV_DMA_NONCOHERENT) +=3D dma-noncoherent.o +obj-$(CONFIG_ARCH_HAS_PMEM_API) +=3D pmem.o diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c new file mode 100644 index 000000000000..089df92ae876 --- /dev/null +++ b/arch/riscv/mm/pmem.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include + +#include + +void arch_wb_cache_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); + +void arch_invalidate_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_invalidate_pmem); --=20 2.34.1 From nobody Tue Apr 7 07:08:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8BB4ECAAD1 for ; Tue, 30 Aug 2022 04:47:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229978AbiH3Er4 (ORCPT ); Tue, 30 Aug 2022 00:47:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229830AbiH3Erq (ORCPT ); Tue, 30 Aug 2022 00:47:46 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0D40AC24D for ; Mon, 29 Aug 2022 21:47:45 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id f12so9809893plb.11 for ; Mon, 29 Aug 2022 21:47:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Z/mBY2jgNDkWQ3lEWcoeCOwOWescKqJwUlwqGO5KuJY=; b=lcMsqLdRZBsh1/gE+Om6+9NNv+3cxCzdFy+52mewdqx7Myu1GG270U5wm/uWxmaAuB bWUyMzYKZgd6KlAwoDeIWNg/ySRIt9WJLvEfij3ceJRNNf6FJDFc6jKyvi32loU214Kd IIp/l3Knw5x7Ah35ABT0IwTSW/liiduLwdAAXtja8YQkgP/Cf3cuYnSsJkC4cnA3ZNXT 7ddhs9HdHwOrX6T6yvjR7DbXmj74a7o3JiqyOxf/GBJinx6X49Hl3/sPm9ZtcqrOoAZQ +g/+qaQORJ5sxzPgivFlwGU5UnqGYennizwRUcSB+4xjsRr5yb9H/LGB/qd7HqiM4Gfj oLkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Z/mBY2jgNDkWQ3lEWcoeCOwOWescKqJwUlwqGO5KuJY=; b=RJMEeJI7w2K9FTNKSd2ebbA1AhcW/V8YNmOdZUkMeZo9HYwdxoZ1JL0RRF8YOB8TyY WB2sTIe+n+cX2PvCpP8yPa/TIwUZA/W0uaO9nXDV01S8QPSjqlBObl1A/CFxUQeIPa5G gnPhEZnVBd8j2QG5/N8+B1V2A2Leow6FUVJBwr7gAsdca0fXLv1luM7NOaKhVv1JitxA g1ix7Qw9n8oVfPoakN7N/PxOz41MKfF94gqnHfyTHaFEyF6XbwAx6RsLR+UrWsMJUTgk 4uC1bxir4odVRdvRHtWaeOf4sOltMkikhsu4ZebRCrqy+TP6fXWrBWfCjtQlokIJLhBH wd+A== X-Gm-Message-State: ACgBeo3yPiB0Da5/XfWy9y4jcaysx1MzxfEgIgFnfNUJA9QYjLZMeV9J +4fY/gC7ySLXAfD1QSoBtbKaxg== X-Google-Smtp-Source: AA6agR6XrkfmOxoBKob/nJpRXtmL+AzNaaiMBZH+BzRQYeIJ3CiaTKVwkXr2+cFUppJYxY/R+NLzhA== X-Received: by 2002:a17:90b:4a82:b0:1fd:9c58:daff with SMTP id lp2-20020a17090b4a8200b001fd9c58daffmr13582124pjb.48.1661834865182; Mon, 29 Aug 2022 21:47:45 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.81.23]) by smtp.gmail.com with ESMTPSA id y27-20020a634b1b000000b0041cd5ddde6fsm592240pga.76.2022.08.29.21.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 21:47:44 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v2 4/4] RISC-V: Enable PMEM drivers Date: Tue, 30 Aug 2022 10:16:42 +0530 Message-Id: <20220830044642.566769-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220830044642.566769-1-apatel@ventanamicro.com> References: <20220830044642.566769-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We now have PMEM arch support available in RISC-V kernel so let us enable relevant drivers in defconfig. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index aed332a9d4ea..010b673ebd11 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=3Dy CONFIG_RPMSG_CHAR=3Dy CONFIG_RPMSG_CTRL=3Dy CONFIG_RPMSG_VIRTIO=3Dy +CONFIG_LIBNVDIMM=3Dy CONFIG_EXT4_FS=3Dy CONFIG_EXT4_FS_POSIX_ACL=3Dy CONFIG_EXT4_FS_SECURITY=3Dy --=20 2.34.1