From nobody Thu Apr 9 12:30:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8751FECAAD2 for ; Mon, 29 Aug 2022 13:01:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230029AbiH2NBs (ORCPT ); Mon, 29 Aug 2022 09:01:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229990AbiH2NBV (ORCPT ); Mon, 29 Aug 2022 09:01:21 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2901D16588 for ; Mon, 29 Aug 2022 05:52:55 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id m2so7890039pls.4 for ; Mon, 29 Aug 2022 05:52:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=DF3EHZACZLIxZm103wJfkyVVUnHhmNz4e84k34pg8iM=; b=VwwMibK4e1SGhbD7sfBq/VulE9XYXIwXhHxCTuKnLGjjKcyYtOU26SdNAy0JJLC328 OGsC0x7AUiU+rPHANfFbPQKXIrm9BPUlPQ+KLS2hnv/uHnFjNLNVCsIub5rusNcz8PaS 9ITaJBrp3LWW015hTkbf7G50YoCWhaNeKGQBGEcfbfe2SFMHn7uBZldruUZyDK2yoP1S nc0+t/oV2jnDFCK1IxcUqlHXx/zeLtYruOq/1VDzU7WDFU8YGTmelwo+1naw5PvIe6rl FQVuklwhjiugna99cpvtoiVQ3B1TnpSKwhBq/moEV0G4cBA2/9uvoYyZtF0EdJ0uXt08 jqqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=DF3EHZACZLIxZm103wJfkyVVUnHhmNz4e84k34pg8iM=; b=jokRXuIr5yW84NUiCh+lESQDSGFwDk3MHnngZ2jbYQCE3W3mXlQS/Tg3gktguS2u3r qdAhLBbPrJqLeW/UR3+z6HCB4SegfPn/h95bC6lGIsC/5QaChraIanZeXWpF/EuE3S2r QaQGiZzlOx5lwqo2VNlahgEiCnMB39yWbGAOGAmyM5Ur26p2RacB4uapWbHnkn1ZVyWN kqNgN6vNO+FQVcxqmmZu7a2QixHoxd8PtiTfGA/vOHFuWG2V1drJwLPK4WUBgJa9eLWn LKKdInSNJtopIUtFFLc7VYPq/NFqiuNY1q78MSAGM7R+PK6SDR4aaJ1M3stbvsG03qHX to4A== X-Gm-Message-State: ACgBeo33WMqstaalrlutAT+Go3vXpwEuCFb2mM9FM8CAsqrE9p2MVLKO p72yfjJmpD8sL7+/y0QxhvRX5A== X-Google-Smtp-Source: AA6agR5aA3lQRu1vS8qwSp/nS3Li+E+T9vQqImCN0tFjn0Mho9TQuefM6AnU7y3mkyQDlJtkWx7W4g== X-Received: by 2002:a17:903:2310:b0:173:10e1:3a76 with SMTP id d16-20020a170903231000b0017310e13a76mr16520555plh.160.1661777574577; Mon, 29 Aug 2022 05:52:54 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.81.110]) by smtp.gmail.com with ESMTPSA id a6-20020a170902ecc600b0016ed5266a5csm7517607plh.170.2022.08.29.05.52.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 05:52:54 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH 1/4] RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt Date: Mon, 29 Aug 2022 18:22:23 +0530 Message-Id: <20220829125226.511564-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220829125226.511564-1-apatel@ventanamicro.com> References: <20220829125226.511564-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, all flavors of ioremap_xyz() function maps to the generic ioremap() which means any ioremap_xyz() call will always map the target memory as IO using _PAGE_IOREMAP page attributes. This breaks ioremap_cache() and ioremap_wc() on systems with Svpbmt because memory remapped using ioremap_cache() and ioremap_wc() will use _PAGE_IOREMAP page attributes. To address above (just like other architectures), we implement RISC-V specific ioremap_cache() and ioremap_wc() which maps memory using page attributes as defined by the Svpbmt specification. Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/include/asm/io.h | 10 ++++++++++ arch/riscv/include/asm/pgtable.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 69605a474270..07ac63999575 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -133,6 +133,16 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, c= ount) #endif =20 +#ifdef CONFIG_MMU +#define ioremap_wc(addr, size) \ + ioremap_prot((addr), (size), _PAGE_IOREMAP_WC) +#endif + #include =20 +#ifdef CONFIG_MMU +#define ioremap_cache(addr, size) \ + ioremap_prot((addr), (size), _PAGE_KERNEL) +#endif + #endif /* _ASM_RISCV_IO_H */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 7ec936910a96..346b7c1a3eeb 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -182,6 +182,8 @@ extern struct pt_alloc_ops pt_ops __initdata; #define PAGE_TABLE __pgprot(_PAGE_TABLE) =20 #define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) +#define _PAGE_IOREMAP_WC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | \ + _PAGE_NOCACHE) #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) =20 extern pgd_t swapper_pg_dir[]; --=20 2.34.1 From nobody Thu Apr 9 12:30:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24703ECAAD5 for ; Mon, 29 Aug 2022 13:01:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229922AbiH2NBx (ORCPT ); Mon, 29 Aug 2022 09:01:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229992AbiH2NBV (ORCPT ); Mon, 29 Aug 2022 09:01:21 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B63447B91 for ; Mon, 29 Aug 2022 05:52:59 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id m10-20020a17090a730a00b001fa986fd8eeso14586181pjk.0 for ; Mon, 29 Aug 2022 05:52:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=5ilaCtDntV5LvqrHcpDpXbfyMqkerLgg3poBAYZ46YQ=; b=Y5QcKGoYcZUCjnyFG9953lwHuj8t9eSGvfQexdUbQBs3F5Q74O7L0rLpj+Rk2NMLRB akZxLE23GhCaDZhrHVl4kvCKRrenMI/lG5N9iy1F5E1tHRv3GJsSzpnEOOs042Xuybrb pe7VGMP+ilvW34wpbW2Ocm3E8BupI9Rpo2t983yVIvRf3ARenyrZYqQ507gIEbhu8AJG 8uhZkR4PxP+N2CQ87mbzj6ax4HHh8AvTYKL7Ck06mcZsrDe+dU3nmz8sB+eZbD3D4Ivp HL9tOZqtrKj6JOn2joQwSLIbJtXPt9h0gUjBubttZ0XYW4NhHWzdx6R0CRKU1o7Gq/II nMLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=5ilaCtDntV5LvqrHcpDpXbfyMqkerLgg3poBAYZ46YQ=; b=iAFCRKOCbToA98e+Wmnk9X52F7BtwoqZLQSV+4LLsJ1GLFpmEUTY9Jop5oa3faFSnI 4FxqGO3bz85vl7UEw7vLqL/Nyl1JKcJXbWckbWBY8QImjxrGwmjxcHeXaQ9L8X6NiL8+ 4AZeFrr6rbHSKtO95oP4Xd8qKEeBHZnFNPu/DWBc8ES5lNyOhWOTULFKkV/5iI46d640 d5vv17Gy4IRusrUlGlxKUSxBYoLWUsssbThG0Gzuwf0VIZtmxg8LOIlt5uRD5/2ScPeB 1d9qSNMmtiSUTV8w0LYkREAY+EWzSypObRjOnxkNhXAnFqyXwVSlyJb9K0ItpC/pgZ7/ c5wg== X-Gm-Message-State: ACgBeo2ejfY/IzSaz4BG49/xbJ+6NlUweEMnzhDuF0FwOeVzYT5e8uVv uSOzUa9DoyFPU0+JGlAYkZM2tA== X-Google-Smtp-Source: AA6agR4OoFG/9b1mM+UxTLGwZsmbxe4eml0wufZpYjFVzAvxCeN1tO1qI+X9fHG9U5AkBhxKVgkPrA== X-Received: by 2002:a17:902:a704:b0:174:3ad5:30b8 with SMTP id w4-20020a170902a70400b001743ad530b8mr15331334plq.14.1661777578696; Mon, 29 Aug 2022 05:52:58 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.81.110]) by smtp.gmail.com with ESMTPSA id a6-20020a170902ecc600b0016ed5266a5csm7517607plh.170.2022.08.29.05.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 05:52:58 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH 2/4] RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c Date: Mon, 29 Aug 2022 18:22:24 +0530 Message-Id: <20220829125226.511564-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220829125226.511564-1-apatel@ventanamicro.com> References: <20220829125226.511564-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The riscv_cbom_block_size parsing from DT belongs to cacheflush.c which is home for all cache maintenance related stuff so let us move the riscv_init_cbom_blocksize() and riscv_cbom_block_size to cacheflush.c. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/include/asm/cacheflush.h | 2 ++ arch/riscv/mm/cacheflush.c | 37 +++++++++++++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 36 ---------------------------- 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/c= acheflush.h index a60acaecfeda..de55d6b8deeb 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -42,6 +42,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); =20 #endif /* CONFIG_SMP */ =20 +extern unsigned int riscv_cbom_block_size; + #ifdef CONFIG_RISCV_ISA_ZICBOM void riscv_init_cbom_blocksize(void); #else diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..26be957dcbf2 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -86,3 +86,40 @@ void flush_icache_pte(pte_t pte) flush_icache_all(); } #endif /* CONFIG_MMU */ + +unsigned int riscv_cbom_block_size =3D L1_CACHE_BYTES; + +#ifdef CONFIG_RISCV_ISA_ZICBOM +void riscv_init_cbom_blocksize(void) +{ + struct device_node *node; + int ret; + u32 val; + + for_each_of_cpu_node(node) { + unsigned long hartid; + int cbom_hartid; + + ret =3D riscv_of_processor_hartid(node, &hartid); + if (ret) + continue; + + if (hartid < 0) + continue; + + /* set block-size for cbom extension if available */ + ret =3D of_property_read_u32(node, "riscv,cbom-block-size", &val); + if (ret) + continue; + + if (!riscv_cbom_block_size) { + riscv_cbom_block_size =3D val; + cbom_hartid =3D hartid; + } else { + if (riscv_cbom_block_size !=3D val) + pr_warn("cbom-block-size mismatched between harts %d and %lu\n", + cbom_hartid, hartid); + } + } +} +#endif diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoheren= t.c index cd2225304c82..b09e4b431307 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -12,7 +12,6 @@ #include #include =20 -static unsigned int riscv_cbom_block_size =3D L1_CACHE_BYTES; static bool noncoherent_supported; =20 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, @@ -75,41 +74,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base= , u64 size, dev->dma_coherent =3D coherent; } =20 -#ifdef CONFIG_RISCV_ISA_ZICBOM -void riscv_init_cbom_blocksize(void) -{ - struct device_node *node; - int ret; - u32 val; - - for_each_of_cpu_node(node) { - unsigned long hartid; - int cbom_hartid; - - ret =3D riscv_of_processor_hartid(node, &hartid); - if (ret) - continue; - - if (hartid < 0) - continue; - - /* set block-size for cbom extension if available */ - ret =3D of_property_read_u32(node, "riscv,cbom-block-size", &val); - if (ret) - continue; - - if (!riscv_cbom_block_size) { - riscv_cbom_block_size =3D val; - cbom_hartid =3D hartid; - } else { - if (riscv_cbom_block_size !=3D val) - pr_warn("cbom-block-size mismatched between harts %d and %lu\n", - cbom_hartid, hartid); - } - } -} -#endif - void riscv_noncoherent_supported(void) { noncoherent_supported =3D true; --=20 2.34.1 From nobody Thu Apr 9 12:30:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B316EECAAD4 for ; Mon, 29 Aug 2022 13:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230132AbiH2NB4 (ORCPT ); Mon, 29 Aug 2022 09:01:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229764AbiH2NBV (ORCPT ); Mon, 29 Aug 2022 09:01:21 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 637EE2DC5 for ; Mon, 29 Aug 2022 05:53:03 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id mj6so2873552pjb.1 for ; Mon, 29 Aug 2022 05:53:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=XMoCsdNUCfWhBPID8WfmwBdQlNlnjab95bfwWj1Kd10=; b=DY53GI5TAnAd0CsPwNi0mXXEFLioz8RUCQWfclNsemmIEoXDit4q8fe226V5e9n66T ymNgRpgtzoZ67kEOIRa3hxXmfD+fTl7OEJKhylMwqu6tmaSUeKNIO/GDq6fOX4zn/AaT yNPIV4K2SYBVbgHjH1vpuoOquPUSxJp7gnQZWKEim5K7/8UBrQYuAp5Nzj7iCi4wENRe 9a1c5135iN0Crz5jFUAGAKPa5kPn75dCP06cCG7Si0znL0Tax5+WlC2U42B1RXs4Xm8u u0lM+CSOnLgcdAglCnrcAROqawX9s98jp/sQDsEbBA049PWUylpLPSHmeftcoAA4ttA3 C8JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=XMoCsdNUCfWhBPID8WfmwBdQlNlnjab95bfwWj1Kd10=; b=Cxaq2lD4W9KodZTr2Ce0U/2wUNhj6z3hfo3D59LJQm8ZGlxDpbglEYrQZmNcnkDxOo EJXcdKYk/leByYetSqX1dL+3qqPSNtMtT/FTR9uh5HCVvsCPs/Z0UAs88HZx9ryr4bcQ JuPUDT7/pmtR07jdqfyjvKEAuj57ckqoenZEYsIdnRNMl+wBBTdhxXCXhsB8kC4CxuVx r8WWMhZu1sZJgQ2KisxPPyYAKkxzgh7PJQdmLOMokhN7OjiNUShtSNrsZ28Gi4vu8nF4 G+CrHsKe0R5E782C3M5Xw9i/lN8rF2VP9aSpo7HAbfXMM+k236ioNTM5pl5SXfGqtQpI Iv1w== X-Gm-Message-State: ACgBeo3GxnE9WaLCcmezrEd7vZSLBInqx8zLeWgKFG6QOlR8QI7ZRjO+ hgfmdsxKhkJpUUHlBfU2DLRitQ== X-Google-Smtp-Source: AA6agR4bk82OZLIjKGxv61LXR9fE7Iqmvmc3giXZ2CUodzY2JdWIgqar/F3YzowFSpuFFbgRQ0T4tQ== X-Received: by 2002:a17:90b:35c8:b0:1fd:aef7:1ef6 with SMTP id nb8-20020a17090b35c800b001fdaef71ef6mr7851082pjb.60.1661777582743; Mon, 29 Aug 2022 05:53:02 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.81.110]) by smtp.gmail.com with ESMTPSA id a6-20020a170902ecc600b0016ed5266a5csm7517607plh.170.2022.08.29.05.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 05:53:02 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH 3/4] RISC-V: Implement arch specific PMEM APIs Date: Mon, 29 Aug 2022 18:22:25 +0530 Message-Id: <20220829125226.511564-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220829125226.511564-1-apatel@ventanamicro.com> References: <20220829125226.511564-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The NVDIMM PMEM driver expects arch specific APIs for cache maintenance and if arch does not provide these APIs then NVDIMM PMEM driver will always use MEMREMAP_WT to map persistent memory which in-turn maps as UC memory type defined by the RISC-V Svpbmt specification. Now that the Svpbmt and Zicbom support is available in RISC-V kernel, we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMM PMEM driver can use MEMREMAP_WB to map persistent memory. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/pmem.c | 21 +++++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/riscv/mm/pmem.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0ebd8da388d8..37d6370d29c3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -25,6 +25,7 @@ config RISCV select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_KCOV select ARCH_HAS_MMIOWB + select ARCH_HAS_PMEM_API select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index d76aabf4b94d..3b368e547f83 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -31,3 +31,4 @@ endif =20 obj-$(CONFIG_DEBUG_VIRTUAL) +=3D physaddr.o obj-$(CONFIG_RISCV_DMA_NONCOHERENT) +=3D dma-noncoherent.o +obj-$(CONFIG_ARCH_HAS_PMEM_API) +=3D pmem.o diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c new file mode 100644 index 000000000000..089df92ae876 --- /dev/null +++ b/arch/riscv/mm/pmem.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include + +#include + +void arch_wb_cache_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); + +void arch_invalidate_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_invalidate_pmem); --=20 2.34.1 From nobody Thu Apr 9 12:30:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F77EECAAD4 for ; Mon, 29 Aug 2022 13:02:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229948AbiH2NCA (ORCPT ); Mon, 29 Aug 2022 09:02:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229768AbiH2NBW (ORCPT ); Mon, 29 Aug 2022 09:01:22 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9535F4BA6A for ; Mon, 29 Aug 2022 05:53:07 -0700 (PDT) Received: by mail-pg1-x530.google.com with SMTP id 69so5965397pgb.13 for ; Mon, 29 Aug 2022 05:53:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Z/mBY2jgNDkWQ3lEWcoeCOwOWescKqJwUlwqGO5KuJY=; b=ZrXS+/PN7MjuqSu/+/xHyffxoijmukarDdtB/3TARKB7q3BLr1Vx7T/fs09i5kfugF IG3pbHjIj1TI+B5S/YOQM445Su0v1nateqtk6N7kYtOhsP3V5tr1fuC+doi9JHoSs3ip QKkcw0r9fSo7tD6i5+VV/UT9qzWyi4mPSrbcxqH2ufl8dvCiPGhUvpmgRKa6iB0pXDMj wPAwssvvOlhxuGtBoT0Z3eXyd53o0ZUdJUVSVQ3ClJse3sXsB0IY+smFNWvdap+CgkGt L4Tvs1C2aAVcXZTcyF1QbyeHX6DffONomhBO7oBimH0a3kUfzDwEM6K+5M6x7M5nKj6W gVRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Z/mBY2jgNDkWQ3lEWcoeCOwOWescKqJwUlwqGO5KuJY=; b=mHccEuqtAX4qBuWBpvQy8TFqUpdUF6SZEPg3xt/yRb8xcZMCUA+9gzJB3iME5dMTWm mIamnKPpb9wFpmfkdHPiZ7NBZO91BGj3OaPnZ6YlUmvBsts+62XlEto5aPnHJAIldCA9 OioIOJ3nUL9beak/SczCSlmETztiy36Ig4grQmW8NH5qCXy+AJDyM5x7XhfrZbrPjNnk F5q54tqyMzMxLq2q17ajlpBTNi735kP/T0dqQBg3CHZijP57O/alyFQ5ebcBZ6MA10oO jSFVVvuuoAC7dYXew8u571CTX1oPHFPwY6zgZvwguY01hDRJbCoSQg7Q3dT4Z5CpK4xn WDKw== X-Gm-Message-State: ACgBeo0wvyITS6IPP57WsJaoBUS80QTubl3Kv/YhjBTGzbcQUYp2w0SM 9V6058s7F4AUyMBhGbU7XXq59w== X-Google-Smtp-Source: AA6agR7EiSZno8PJhvukHxS/VfWScLMZXn5Vlfkr+Zp9Me2vZrYE8Ww3BqQJI+4eSdeYl9Ih2996hA== X-Received: by 2002:a65:6d0b:0:b0:42a:19dc:e76e with SMTP id bf11-20020a656d0b000000b0042a19dce76emr13623850pgb.6.1661777587046; Mon, 29 Aug 2022 05:53:07 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.81.110]) by smtp.gmail.com with ESMTPSA id a6-20020a170902ecc600b0016ed5266a5csm7517607plh.170.2022.08.29.05.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 05:53:06 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH 4/4] RISC-V: Enable PMEM drivers Date: Mon, 29 Aug 2022 18:22:26 +0530 Message-Id: <20220829125226.511564-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220829125226.511564-1-apatel@ventanamicro.com> References: <20220829125226.511564-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We now have PMEM arch support available in RISC-V kernel so let us enable relevant drivers in defconfig. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index aed332a9d4ea..010b673ebd11 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=3Dy CONFIG_RPMSG_CHAR=3Dy CONFIG_RPMSG_CTRL=3Dy CONFIG_RPMSG_VIRTIO=3Dy +CONFIG_LIBNVDIMM=3Dy CONFIG_EXT4_FS=3Dy CONFIG_EXT4_FS_POSIX_ACL=3Dy CONFIG_EXT4_FS_SECURITY=3Dy --=20 2.34.1