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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT083.mail.protection.outlook.com (10.13.173.97) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5566.15 via Frontend Transport; Mon, 29 Aug 2022 09:07:48 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 29 Aug 2022 04:07:47 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Mon, 29 Aug 2022 04:07:43 -0500 From: Sai Krishna Potthuri To: Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , "Vignesh Raghavendra" , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , Sai Krishna Potthuri Subject: [PATCH 2/2] mtd: spi-nor: Add support for flash reset Date: Mon, 29 Aug 2022 14:35:28 +0530 Message-ID: <20220829090528.21613-3-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220829090528.21613-1-sai.krishna.potthuri@amd.com> References: <20220829090528.21613-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3ba322f8-e52a-4681-12a9-08da899df1c0 X-MS-TrafficTypeDiagnostic: BN8PR12MB3249:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2022 09:07:48.4176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ba322f8-e52a-4681-12a9-08da899df1c0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT083.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3249 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spi-nor flash reset via GPIO controller by reading the reset-gpio property. If there is a valid GPIO specifier then reset will be performed by asserting and deasserting the GPIO using gpiod APIs otherwise it will not perform any operation. Signed-off-by: Sai Krishna Potthuri --- drivers/mtd/spi-nor/core.c | 50 +++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index f2c64006f8d7..d4703ff69ad0 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2401,12 +2401,8 @@ static void spi_nor_no_sfdp_init_params(struct spi_n= or *nor) */ static void spi_nor_init_flags(struct spi_nor *nor) { - struct device_node *np =3D spi_nor_get_flash_node(nor); const u16 flags =3D nor->info->flags; =20 - if (of_property_read_bool(np, "broken-flash-reset")) - nor->flags |=3D SNOR_F_BROKEN_RESET; - if (flags & SPI_NOR_SWP_IS_VOLATILE) nor->flags |=3D SNOR_F_SWP_IS_VOLATILE; =20 @@ -2933,9 +2929,47 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor) mtd->_put_device =3D spi_nor_put_device; } =20 +static int spi_nor_hw_reset(struct spi_nor *nor) +{ + struct gpio_desc *reset; + int ret; + + reset =3D devm_gpiod_get_optional(nor->dev, "reset", GPIOD_ASIS); + if (IS_ERR_OR_NULL(reset)) + return PTR_ERR_OR_ZERO(reset); + + /* Set the direction as output and enable the output */ + ret =3D gpiod_direction_output(reset, 1); + if (ret) + return ret; + + /* + * Experimental Minimum Chip select high to Reset delay value + * based on the flash device spec. + */ + usleep_range(1, 5); + gpiod_set_value(reset, 0); + + /* + * Experimental Minimum Reset pulse width value based on the + * flash device spec. + */ + usleep_range(10, 15); + gpiod_set_value(reset, 1); + + /* + * Experimental Minimum Reset recovery delay value based on the + * flash device spec. + */ + usleep_range(35, 40); + + return 0; +} + int spi_nor_scan(struct spi_nor *nor, const char *name, const struct spi_nor_hwcaps *hwcaps) { + struct device_node *np =3D spi_nor_get_flash_node(nor); const struct flash_info *info; struct device *dev =3D nor->dev; struct mtd_info *mtd =3D &nor->mtd; @@ -2965,6 +2999,14 @@ int spi_nor_scan(struct spi_nor *nor, const char *na= me, if (!nor->bouncebuf) return -ENOMEM; =20 + if (of_property_read_bool(np, "broken-flash-reset")) { + nor->flags |=3D SNOR_F_BROKEN_RESET; + } else { + ret =3D spi_nor_hw_reset(nor); + if (ret) + return ret; + } + info =3D spi_nor_get_flash_info(nor, name); if (IS_ERR(info)) return PTR_ERR(info); --=20 2.17.1