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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id mp10-20020a17090b190a00b001f333fab3d6sm5817972pjb.18.2022.08.28.23.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 23:22:11 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache Date: Mon, 29 Aug 2022 06:22:00 +0000 Message-Id: <20220829062202.3287-2-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220829062202.3287-1-zong.li@sifive.com> References: <20220829062202.3287-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since composible cache may be L3 cache if private L2 cache exists, it should use its original name composible cache to prevent confusion. Signed-off-by: Greentime Hu Signed-off-by: Zong Li --- .../riscv/{sifive-l2-cache.yaml =3D> sifive-ccache.yaml} | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml =3D> = sifive-ccache.yaml} (92%) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b= /Documentation/devicetree/bindings/riscv/sifive-ccache.yaml similarity index 92% rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml index 69cdab18d629..1a64a5384e36 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml @@ -12,8 +12,8 @@ maintainers: - Paul Walmsley =20 description: - The SiFive Level 2 Cache Controller is used to provide access to fast co= pies - of memory for masters in a Core Complex. The Level 2 Cache Controller al= so + The SiFive Composable Cache Controller is used to provide access to fast= copies + of memory for masters in a Core Complex. The Composable Cache Controller= also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this pl= atform. =20 @@ -27,6 +27,7 @@ select: enum: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - sifive,ccache0 =20 required: - compatible @@ -37,6 +38,7 @@ properties: - enum: - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - sifive,ccache0 - const: cache =20 cache-block-size: --=20 2.17.1 From nobody Tue Apr 7 10:40:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D370DECAAD4 for ; Mon, 29 Aug 2022 06:22:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229593AbiH2GWY (ORCPT ); Mon, 29 Aug 2022 02:22:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229754AbiH2GWR (ORCPT ); Mon, 29 Aug 2022 02:22:17 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD09F422E9 for ; Sun, 28 Aug 2022 23:22:15 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id l3so7008382plb.10 for ; Sun, 28 Aug 2022 23:22:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=b+Dj/bON9YWCztdnm4HWQ6GsSjE/m0eim3jpo/IdprA=; b=Vgag9ye8/cj8OQQ/WD3Xzj4cmkBHWbyAMZwLa6XYXsEU5LAHrt1TZ/+KRMKS2tjS+9 bMpASJMzHz5y0ZqT50cZEFFMUVy6SYkgUTmxPWbz0E79QfOf1lJFJE5mWxiE8JgaX0Cv jVshMDe26qCyV6LI+ZTc1YYtZIDVraQzAbI/uE+mjPRXJV26R/BrZwPINfQdxjh1a5NA qazDJoJaP4tNxIfD4LqUdZyD4UAv0W+3R0GngaNme7otbEYfc5Xyb2Tg8N6CO9bc3MHQ rG7r1AjV23mDM6P5WJ/y0WI4Q4jC0BNQ9ZqMuToRTQtvNIH1HLwHyHSW3c79bda+ZKG9 VIwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=b+Dj/bON9YWCztdnm4HWQ6GsSjE/m0eim3jpo/IdprA=; b=p3Q2ed32VTAVnZ4qziufos8cI3/a3rSeEZkQkcpqVTXVST4ccDNIc3i+Ij5TTBvaCi +XWyBPsGNrjIzMtn8mjP80DIxuh24u5kWgl2s9LZOa5v/hsOxkoO8N16ykwyDVxaXOfS 5dHJf9RYoIttcXRTtJ2w1O5HObuMvY2pPsvD1NdfGXwV+w06wyw92CC+GnA63msuxmJu Gm1ypm1UgRkRKrpj2W9p7hYctI1SkZ5nvf4jObpNrmT0P/U3nPdQOa78IT/3e/mZ6+aZ hXdDDnkac+sHJyviCUOvV8mJWkBd8xFATfIKWN3XjDpjDZiVs8tOG5QjUjRyFqHK/9EK XaJQ== X-Gm-Message-State: ACgBeo2l3RrexC1GdaCcu9dMhU3wU9346Yel1EXDh0x0ocBYUCzvg6pB bsosVkQbmanz+IFUZufqlrtsIA== X-Google-Smtp-Source: AA6agR42s0ebdoR2tjV0nFljUGrv+b/FZ0816d85HA0saeWsRNPNT4/cAeIS1CmrfOSjfLudNIua2g== X-Received: by 2002:a17:90a:474b:b0:1fd:62c3:62ef with SMTP id y11-20020a17090a474b00b001fd62c362efmr15286181pjg.8.1661754135316; Sun, 28 Aug 2022 23:22:15 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id mp10-20020a17090b190a00b001f333fab3d6sm5817972pjb.18.2022.08.28.23.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 23:22:14 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH 2/3] soc: sifive: l2 cache: Rename SiFive L2 cache to composible cache. Date: Mon, 29 Aug 2022 06:22:01 +0000 Message-Id: <20220829062202.3287-3-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220829062202.3287-1-zong.li@sifive.com> References: <20220829062202.3287-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Greentime Hu Since composible cache may be L3 cache if pL2 cache exists, we should use its original name composible cache to prevent confusion. Signed-off-by: Greentime Hu Signed-off-by: Zong Li --- drivers/soc/sifive/Kconfig | 7 +- drivers/soc/sifive/Makefile | 2 +- drivers/soc/sifive/sifive_ccache.c | 221 +++++++++++++++++++++++++ drivers/soc/sifive/sifive_l2_cache.c | 237 --------------------------- include/soc/sifive/sifive_ccache.h | 16 ++ include/soc/sifive/sifive_l2_cache.h | 16 -- 6 files changed, 242 insertions(+), 257 deletions(-) create mode 100644 drivers/soc/sifive/sifive_ccache.c delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c create mode 100644 include/soc/sifive/sifive_ccache.h delete mode 100644 include/soc/sifive/sifive_l2_cache.h diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index 58cf8c40d08d..3d65d2771f9a 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -2,9 +2,10 @@ =20 if SOC_SIFIVE =20 -config SIFIVE_L2 - bool "Sifive L2 Cache controller" +config SIFIVE_CCACHE + bool "Sifive composable Cache controller" + default y help - Support for the L2 cache controller on SiFive platforms. + Support for the composable cache controller on SiFive platforms. =20 endif diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile index b5caff77938f..1f5dc339bf82 100644 --- a/drivers/soc/sifive/Makefile +++ b/drivers/soc/sifive/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 =20 -obj-$(CONFIG_SIFIVE_L2) +=3D sifive_l2_cache.o +obj-$(CONFIG_SIFIVE_CCACHE) +=3D sifive_ccache.o diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive= _ccache.c new file mode 100644 index 000000000000..46ce33db7d30 --- /dev/null +++ b/drivers/soc/sifive/sifive_ccache.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SiFive composable cache controller Driver + * + * Copyright (C) 2018-2019 SiFive, Inc. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 +#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 +#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 + +#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 +#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 +#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 + +#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 +#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 +#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 + +#define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_WAYENABLE 0x08 +#define SIFIVE_CCACHE_ECCINJECTERR 0x40 + +#define SIFIVE_CCACHE_MAX_ECCINTR 3 + +static void __iomem *ccache_base; +static int level; +static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops ccache_cache_ops; + +enum { + DIR_CORR =3D 0, + DATA_CORR, + DATA_UNCORR, +}; + +#ifdef CONFIG_DEBUG_FS +static struct dentry *sifive_test; + +static ssize_t ccache_write(struct file *file, const char __user *data, + size_t count, loff_t *ppos) +{ + unsigned int val; + + if (kstrtouint_from_user(data, count, 0, &val)) + return -EINVAL; + if ((val < 0xFF) || (val >=3D 0x10000 && val < 0x100FF)) + writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); + else + return -EINVAL; + return count; +} + +static const struct file_operations ccache_fops =3D { + .owner =3D THIS_MODULE, + .open =3D simple_open, + .write =3D ccache_write +}; + +static void setup_sifive_debug(void) +{ + sifive_test =3D debugfs_create_dir("sifive_ccache_cache", NULL); + + debugfs_create_file("sifive_debug_inject_error", 0200, + sifive_test, NULL, &ccache_fops); +} +#endif + +static void ccache_config_read(void) +{ + u32 regval, val; + + regval =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG); + val =3D regval & 0xFF; + pr_info("CCACHE: No. of Banks in the cache: %d\n", val); + val =3D (regval & 0xFF00) >> 8; + pr_info("CCACHE: No. of ways per bank: %d\n", val); + val =3D (regval & 0xFF0000) >> 16; + pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); + val =3D (regval & 0xFF000000) >> 24; + pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); + + regval =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); +} + +static const struct of_device_id sifive_ccache_ids[] =3D { + { .compatible =3D "sifive,fu540-c000-ccache" }, + { .compatible =3D "sifive,ccache0" }, + { /* end of table */ }, +}; + +static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); + +int register_sifive_ccache_error_notifier(struct notifier_block *nb) +{ + return atomic_notifier_chain_register(&ccache_err_chain, nb); +} +EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); + +int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) +{ + return atomic_notifier_chain_unregister(&ccache_err_chain, nb); +} +EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); + +static int ccache_largest_wayenabled(void) +{ + return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; +} + +static ssize_t number_of_ways_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", ccache_largest_wayenabled()); +} + +static DEVICE_ATTR_RO(number_of_ways_enabled); + +static struct attribute *priv_attrs[] =3D { + &dev_attr_number_of_ways_enabled.attr, + NULL, +}; + +static const struct attribute_group priv_attr_group =3D { + .attrs =3D priv_attrs, +}; + +static const struct attribute_group *ccache_get_priv_group(struct cacheinf= o *this_leaf) +{ + /* We want to use private group for composable cache only */ + if (this_leaf->level =3D=3D level) + return &priv_attr_group; + else + return NULL; +} + +static irqreturn_t ccache_int_handler(int irq, void *device) +{ + unsigned int add_h, add_l; + + if (irq =3D=3D g_irq[DIR_CORR]) { + add_h =3D readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); + add_l =3D readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); + pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); + /* Reading this register clears the DirError interrupt sig */ + readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE, + "DirECCFix"); + } + if (irq =3D=3D g_irq[DATA_CORR]) { + add_h =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); + add_l =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); + pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); + /* Reading this register clears the DataError interrupt sig */ + readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE, + "DatECCFix"); + } + if (irq =3D=3D g_irq[DATA_UNCORR]) { + add_h =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); + add_l =3D readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); + pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); + /* Reading this register clears the DataFail interrupt sig */ + readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); + atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE, + "DatECCFail"); + } + + return IRQ_HANDLED; +} + +static int __init sifive_ccache_init(void) +{ + struct device_node *np; + struct resource res; + int i, rc; + + np =3D of_find_matching_node(NULL, sifive_ccache_ids); + if (!np) + return -ENODEV; + + if (of_address_to_resource(np, 0, &res)) + return -ENODEV; + + if (of_property_read_u32(np, "cache-level", &level)) + return -ENODEV; + + ccache_base =3D ioremap(res.start, resource_size(&res)); + if (!ccache_base) + return -ENOMEM; + + for (i =3D 0; i < SIFIVE_CCACHE_MAX_ECCINTR; i++) { + g_irq[i] =3D irq_of_parse_and_map(np, i); + rc =3D request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL); + if (rc) { + pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); + return rc; + } + } + + ccache_config_read(); + + ccache_cache_ops.get_priv_group =3D ccache_get_priv_group; + riscv_set_cacheinfo_ops(&ccache_cache_ops); + +#ifdef CONFIG_DEBUG_FS + setup_sifive_debug(); +#endif + return 0; +} +device_initcall(sifive_ccache_init); diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifi= ve_l2_cache.c deleted file mode 100644 index 59640a1d0b28..000000000000 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SiFive L2 cache controller Driver - * - * Copyright (C) 2018-2019 SiFive, Inc. - * - */ -#include -#include -#include -#include -#include -#include -#include - -#define SIFIVE_L2_DIRECCFIX_LOW 0x100 -#define SIFIVE_L2_DIRECCFIX_HIGH 0x104 -#define SIFIVE_L2_DIRECCFIX_COUNT 0x108 - -#define SIFIVE_L2_DIRECCFAIL_LOW 0x120 -#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124 -#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128 - -#define SIFIVE_L2_DATECCFIX_LOW 0x140 -#define SIFIVE_L2_DATECCFIX_HIGH 0x144 -#define SIFIVE_L2_DATECCFIX_COUNT 0x148 - -#define SIFIVE_L2_DATECCFAIL_LOW 0x160 -#define SIFIVE_L2_DATECCFAIL_HIGH 0x164 -#define SIFIVE_L2_DATECCFAIL_COUNT 0x168 - -#define SIFIVE_L2_CONFIG 0x00 -#define SIFIVE_L2_WAYENABLE 0x08 -#define SIFIVE_L2_ECCINJECTERR 0x40 - -#define SIFIVE_L2_MAX_ECCINTR 4 - -static void __iomem *l2_base; -static int g_irq[SIFIVE_L2_MAX_ECCINTR]; -static struct riscv_cacheinfo_ops l2_cache_ops; - -enum { - DIR_CORR =3D 0, - DATA_CORR, - DATA_UNCORR, - DIR_UNCORR, -}; - -#ifdef CONFIG_DEBUG_FS -static struct dentry *sifive_test; - -static ssize_t l2_write(struct file *file, const char __user *data, - size_t count, loff_t *ppos) -{ - unsigned int val; - - if (kstrtouint_from_user(data, count, 0, &val)) - return -EINVAL; - if ((val < 0xFF) || (val >=3D 0x10000 && val < 0x100FF)) - writel(val, l2_base + SIFIVE_L2_ECCINJECTERR); - else - return -EINVAL; - return count; -} - -static const struct file_operations l2_fops =3D { - .owner =3D THIS_MODULE, - .open =3D simple_open, - .write =3D l2_write -}; - -static void setup_sifive_debug(void) -{ - sifive_test =3D debugfs_create_dir("sifive_l2_cache", NULL); - - debugfs_create_file("sifive_debug_inject_error", 0200, - sifive_test, NULL, &l2_fops); -} -#endif - -static void l2_config_read(void) -{ - u32 regval, val; - - regval =3D readl(l2_base + SIFIVE_L2_CONFIG); - val =3D regval & 0xFF; - pr_info("L2CACHE: No. of Banks in the cache: %d\n", val); - val =3D (regval & 0xFF00) >> 8; - pr_info("L2CACHE: No. of ways per bank: %d\n", val); - val =3D (regval & 0xFF0000) >> 16; - pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val); - val =3D (regval & 0xFF000000) >> 24; - pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - - regval =3D readl(l2_base + SIFIVE_L2_WAYENABLE); - pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval); -} - -static const struct of_device_id sifive_l2_ids[] =3D { - { .compatible =3D "sifive,fu540-c000-ccache" }, - { .compatible =3D "sifive,fu740-c000-ccache" }, - { /* end of table */ }, -}; - -static ATOMIC_NOTIFIER_HEAD(l2_err_chain); - -int register_sifive_l2_error_notifier(struct notifier_block *nb) -{ - return atomic_notifier_chain_register(&l2_err_chain, nb); -} -EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier); - -int unregister_sifive_l2_error_notifier(struct notifier_block *nb) -{ - return atomic_notifier_chain_unregister(&l2_err_chain, nb); -} -EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); - -static int l2_largest_wayenabled(void) -{ - return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF; -} - -static ssize_t number_of_ways_enabled_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - return sprintf(buf, "%u\n", l2_largest_wayenabled()); -} - -static DEVICE_ATTR_RO(number_of_ways_enabled); - -static struct attribute *priv_attrs[] =3D { - &dev_attr_number_of_ways_enabled.attr, - NULL, -}; - -static const struct attribute_group priv_attr_group =3D { - .attrs =3D priv_attrs, -}; - -static const struct attribute_group *l2_get_priv_group(struct cacheinfo *t= his_leaf) -{ - /* We want to use private group for L2 cache only */ - if (this_leaf->level =3D=3D 2) - return &priv_attr_group; - else - return NULL; -} - -static irqreturn_t l2_int_handler(int irq, void *device) -{ - unsigned int add_h, add_l; - - if (irq =3D=3D g_irq[DIR_CORR]) { - add_h =3D readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH); - add_l =3D readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW); - pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DirError interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, - "DirECCFix"); - } - if (irq =3D=3D g_irq[DIR_UNCORR]) { - add_h =3D readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH); - add_l =3D readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW); - /* Reading this register clears the DirFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, - "DirECCFail"); - panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); - } - if (irq =3D=3D g_irq[DATA_CORR]) { - add_h =3D readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH); - add_l =3D readl(l2_base + SIFIVE_L2_DATECCFIX_LOW); - pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DataError interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE, - "DatECCFix"); - } - if (irq =3D=3D g_irq[DATA_UNCORR]) { - add_h =3D readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH); - add_l =3D readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW); - pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); - /* Reading this register clears the DataFail interrupt sig */ - readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT); - atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE, - "DatECCFail"); - } - - return IRQ_HANDLED; -} - -static int __init sifive_l2_init(void) -{ - struct device_node *np; - struct resource res; - int i, rc, intr_num; - - np =3D of_find_matching_node(NULL, sifive_l2_ids); - if (!np) - return -ENODEV; - - if (of_address_to_resource(np, 0, &res)) - return -ENODEV; - - l2_base =3D ioremap(res.start, resource_size(&res)); - if (!l2_base) - return -ENOMEM; - - intr_num =3D of_property_count_u32_elems(np, "interrupts"); - if (!intr_num) { - pr_err("L2CACHE: no interrupts property\n"); - return -ENODEV; - } - - for (i =3D 0; i < intr_num; i++) { - g_irq[i] =3D irq_of_parse_and_map(np, i); - rc =3D request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); - if (rc) { - pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); - return rc; - } - } - - l2_config_read(); - - l2_cache_ops.get_priv_group =3D l2_get_priv_group; - riscv_set_cacheinfo_ops(&l2_cache_ops); - -#ifdef CONFIG_DEBUG_FS - setup_sifive_debug(); -#endif - return 0; -} -device_initcall(sifive_l2_init); diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive= _ccache.h new file mode 100644 index 000000000000..16576d678ea8 --- /dev/null +++ b/include/soc/sifive/sifive_ccache.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SiFive composable Cache Controller header file + * + */ + +#ifndef __SOC_SIFIVE_CCACHE_H +#define __SOC_SIFIVE_CCACHE_H + +extern int register_sifive_ccache_error_notifier(struct notifier_block *nb= ); +extern int unregister_sifive_ccache_error_notifier(struct notifier_block *= nb); + +#define SIFIVE_CCACHE_ERR_TYPE_CE 0 +#define SIFIVE_CCACHE_ERR_TYPE_UE 1 + +#endif /* __SOC_SIFIVE_CCACHE_H */ diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifi= ve_l2_cache.h deleted file mode 100644 index 92ade10ed67e..000000000000 --- a/include/soc/sifive/sifive_l2_cache.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * SiFive L2 Cache Controller header file - * - */ - -#ifndef __SOC_SIFIVE_L2_CACHE_H -#define __SOC_SIFIVE_L2_CACHE_H - -extern int register_sifive_l2_error_notifier(struct notifier_block *nb); -extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); - -#define SIFIVE_L2_ERR_TYPE_CE 0 -#define SIFIVE_L2_ERR_TYPE_UE 1 - -#endif /* __SOC_SIFIVE_L2_CACHE_H */ --=20 2.17.1 From nobody Tue Apr 7 10:40:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 754CAECAAD2 for ; Mon, 29 Aug 2022 06:22:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229555AbiH2GW3 (ORCPT ); Mon, 29 Aug 2022 02:22:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229774AbiH2GWV (ORCPT ); Mon, 29 Aug 2022 02:22:21 -0400 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F13F049B61 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id mp10-20020a17090b190a00b001f333fab3d6sm5817972pjb.18.2022.08.28.23.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 23:22:17 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2 Date: Mon, 29 Aug 2022 06:22:02 +0000 Message-Id: <20220829062202.3287-4-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220829062202.3287-1-zong.li@sifive.com> References: <20220829062202.3287-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well Signed-off-by: Zong Li --- drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 17562cf1fe97..456602d373b7 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC =20 config EDAC_SIFIVE bool "Sifive platform EDAC driver" - depends on EDAC=3Dy && SIFIVE_L2 + depends on EDAC=3Dy && SIFIVE_CCACHE help Support for error detection and correction on the SiFive SoCs. =20 diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c index ee800aec7d47..b844e2626fd5 100644 --- a/drivers/edac/sifive_edac.c +++ b/drivers/edac/sifive_edac.c @@ -2,7 +2,7 @@ /* * SiFive Platform EDAC Driver * - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * * This driver is partially based on octeon_edac-pc.c * @@ -10,7 +10,7 @@ #include #include #include "edac_module.h" -#include +#include =20 #define DRVNAME "sifive_edac" =20 @@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned l= ong event, void *ptr) =20 p =3D container_of(this, struct sifive_edac_priv, notifier); =20 - if (event =3D=3D SIFIVE_L2_ERR_TYPE_UE) + if (event =3D=3D SIFIVE_CCACHE_ERR_TYPE_UE) edac_device_handle_ue(p->dci, 0, 0, msg); - else if (event =3D=3D SIFIVE_L2_ERR_TYPE_CE) + else if (event =3D=3D SIFIVE_CCACHE_ERR_TYPE_CE) edac_device_handle_ce(p->dci, 0, 0, msg); =20 return NOTIFY_OK; @@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev) goto err; } =20 - register_sifive_l2_error_notifier(&p->notifier); + register_sifive_ccache_error_notifier(&p->notifier); =20 return 0; =20 @@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev) { struct sifive_edac_priv *p =3D platform_get_drvdata(pdev); =20 - unregister_sifive_l2_error_notifier(&p->notifier); + unregister_sifive_ccache_error_notifier(&p->notifier); edac_device_del_device(&pdev->dev); edac_device_free_ctl_info(p->dci); =20 --=20 2.17.1 From nobody Tue Apr 7 10:40:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F5A3C0502A for ; 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Tue, 30 Aug 2022 05:51:35 -0700 (PDT) From: Ben Dooks To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org Cc: Ben Dooks Subject: [RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache Date: Tue, 30 Aug 2022 13:51:33 +0100 Message-Id: <20220830125133.1698781-1-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220829062202.3287-1-zong.li@sifive.com> References: <20220829062202.3287-1-zong.li@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With newer cores such as the p550, the SiFive composable cache can be a level 3 cache. Update the cache level to be one of 2 or 3. Signed-off-by: Ben Dooks Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/D= ocumentation/devicetree/bindings/riscv/sifive-ccache.yaml index 1a64a5384e36..6190deb65455 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml @@ -45,7 +45,7 @@ properties: const: 64 =20 cache-level: - const: 2 + enum: [2, 3] =20 cache-sets: enum: [1024, 2048] --=20 2.35.1 From nobody Tue Apr 7 10:40:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60B92ECAAA1 for ; Tue, 30 Aug 2022 08:26:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231450AbiH3I0b (ORCPT ); Tue, 30 Aug 2022 04:26:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230430AbiH3I00 (ORCPT ); Tue, 30 Aug 2022 04:26:26 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE41072FE7 for ; Tue, 30 Aug 2022 01:26:24 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id ay39-20020a05600c1e2700b003a5503a80cfso5690882wmb.2 for ; Tue, 30 Aug 2022 01:26:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=XM3hePWi4RDkuttssXrZ5VE24lNRdsy0rflErqQPY28=; b=bzJhyUUM5uZv8zprUMiOXaBrBVZ/UgJq0b0zOl6DqnXHgQojf+yPBZ5c8Z9vFqh5q0 2nQC93flygBxrmVG+ODrSWT/eSkSNRTcX2Y6vLp6UMgN3/WzkLhiHTMdoy6o6HA73hUW 7zxAcvoE2q3BvvO1sPktBzvhptHkN6EO0boN3qDwA5hFxGEbpZPabuYASBL9G8gR0zxJ YUfIkQ9wY2Dy2pgy+A+lXXGd5UaZkvFVPTtexArM1iN/Tpw8y+A3cUa1v1LaizfnEZDR Lq0pD5DIkVkFPgjzUP/wcrekf2b9g/c6OrRoDafImhR/ymh1Zr1j9JhaxlCfkVmB8cve YtQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=XM3hePWi4RDkuttssXrZ5VE24lNRdsy0rflErqQPY28=; b=mpBLZOqjN3QE8naj0HtaxtUFr2YCI3jpJXOiM9jWMJ3Jq5RGHkT3cA/OZ6U1rJLkcb 2UcyXimISTn951KfztWjYzmYTPsOpYd4fogX6Nz1tPf6Npob6FplP3CEHwkeBmcCJVr+ 7q30Y2ZQVa0B/zORzNKfMAHp5MpCxLFUrOUAd+W0+klyDn0vS/b4faCkyGJ05KmqCPnd rt151G17kSlp/f1hdhJ56Dgn9nfdMf/njE9vpI4X4yraK9mHigDiluPtu8UZe8MpM0va UuXoKeP7Y1pO87jRfn4JP2E00VuPb1v9NCYRSjzAKmEtX7VPy/xbLBlJWfNui817sEyN zjPQ== X-Gm-Message-State: ACgBeo2QKex087AumqZy8kYoIMFQPPgkoTK7YDjsDDZLXyPbXkPveTVr ZKAzfL2tRXn4u89+KiABv7dkWw== X-Google-Smtp-Source: AA6agR4t9yPdMnXaYpamc2su/lpj35tI/2NDGR0soqyjuxgixE2p5bvOVagi7BoSRqbqQcAVKeZZmA== X-Received: by 2002:a05:600c:1e05:b0:3a5:b441:e9c with SMTP id ay5-20020a05600c1e0500b003a5b4410e9cmr8915891wmb.24.1661847983138; Tue, 30 Aug 2022 01:26:23 -0700 (PDT) Received: from rainbowdash.office.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id bi26-20020a05600c3d9a00b003a5ea1cc63csm11051643wmb.39.2022.08.30.01.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 01:26:22 -0700 (PDT) From: Ben Dooks To: zong.li@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Ben Dooks Subject: [PATCH] soc: sifive: ccache: reduce printing on init Date: Tue, 30 Aug 2022 09:26:20 +0100 Message-Id: <20220830082620.1680602-1-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220829062202.3287-1-zong.li@sifive.com> References: <20220829062202.3287-1-zong.li@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks --- drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive= _ccache.c index 46ce33db7d30..65a10a6ee211 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -76,20 +76,17 @@ static void setup_sifive_debug(void) =20 static void ccache_config_read(void) { - u32 regval, val; - - regval =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG); - val =3D regval & 0xFF; - pr_info("CCACHE: No. of Banks in the cache: %d\n", val); - val =3D (regval & 0xFF00) >> 8; - pr_info("CCACHE: No. of ways per bank: %d\n", val); - val =3D (regval & 0xFF0000) >> 16; - pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); - val =3D (regval & 0xFF000000) >> 24; - pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); - - regval =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); - pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); + u32 cfg; + + cfg =3D readl(ccache_base + SIFIVE_CCACHE_CONFIG); + + pr_info("CCACHE: %u banks, %u ways, sets/bank=3D%llu, bytes/block=3D%llu\= n", + (cfg & 0xff), (cfg >> 8) & 0xff, + 1ULL << ((cfg >> 16) & 0xff), + 1ULL << ((cfg >> 24) & 0xff)); + + cfg =3D readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg); } =20 static const struct of_device_id sifive_ccache_ids[] =3D { --=20 2.35.1 From nobody Tue Apr 7 10:40:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9C19ECAAD4 for ; Tue, 30 Aug 2022 08:36:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231186AbiH3IgN (ORCPT ); Tue, 30 Aug 2022 04:36:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231449AbiH3IgL (ORCPT ); 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Tue, 30 Aug 2022 01:36:08 -0700 (PDT) From: Ben Dooks To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Ben Dooks Subject: [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache Date: Tue, 30 Aug 2022 09:36:06 +0100 Message-Id: <20220830083606.1681385-1-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220829062202.3287-1-zong.li@sifive.com> References: <20220829062202.3287-1-zong.li@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With newer cores such as the p550, the SiFive composable cache can be a level 3 cache. Update the cache level to be one of 2 or 3. Signed-off-by: Ben Dooks --- Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/D= ocumentation/devicetree/bindings/riscv/sifive-ccache.yaml index 1a64a5384e36..6190deb65455 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml @@ -45,7 +45,7 @@ properties: const: 64 =20 cache-level: - const: 2 + enum: [2, 3] =20 cache-sets: enum: [1024, 2048] --=20 2.35.1