From nobody Tue Apr 7 16:29:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28C8BECAAD4 for ; Fri, 26 Aug 2022 14:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344454AbiHZO3e (ORCPT ); Fri, 26 Aug 2022 10:29:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344447AbiHZO3M (ORCPT ); Fri, 26 Aug 2022 10:29:12 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB443A2D9F; Fri, 26 Aug 2022 07:29:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524149; x=1693060149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yKgAt3C7Fyh1kNQmbM/QmIH0uqeZcK+a+yeHIz/VQwU=; b=qT707EtRuByRfofyU4SUOeRSqZ4jfVgtL6qoFOT3WSOVTPJArWIYHPen IcVVdJmKKqwcOsbK5nSUNxWgIvDTclajQDbwLQkYUdgtoQ690EN8srNgk 1cEDic0jc8wu0LdrFc0QvMRz8nY4R9wT/5Kyq32gsIQqCzFh8az3AuQpM KbRcf6tKCC0fsL5OmrprtwqVGrzSekfu1R5wsyDKYuMnt9FzAZ6j29Ef/ Gdg7PnHrRfEKFf0z1e+yEXbG8CGuvPbdNg0Imc9+ZPGE1A2V6piFX7vBI 3wIZhJaKjYz6/SkCCj/SqIkdBFDE3I01GC18B/cFpqpvNda2qgje/YY2I Q==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="178024821" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:29:08 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:29:07 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:29:05 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Date: Fri, 26 Aug 2022 15:28:07 +0100 Message-ID: <20220826142806.3658434-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device trees for both configs used by the Aries Embedded M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM, featuring: - 2GB DDR4 SDRAM dedicated to the HMS - 512MB DDR4 SDRAM dedicated to the FPGA - 32 MB SPI NOR Flash - 4 GByte eMMC and a carrier board with: - 2x Gigabit Ethernet - USB - 2x UART - 2x CAN - TFT connector - HSMC extension connector - 3x PMOD extension connectors - microSD-card slot Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-s= om-mpfs025t-pcie-serdes Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchi= p-soc-fpga-m100pfsevp-riscv-hsmc-pmod Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFS= EVP-Schematics.pdf Co-developed-by: Wolfgang Grandegger Signed-off-by: Wolfgang Grandegger Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 2 + .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++ .../dts/microchip/mpfs-m100pfsevp-emmc.dts | 37 +++++ .../dts/microchip/mpfs-m100pfsevp-sdcard.dts | 37 +++++ .../boot/dts/microchip/mpfs-m100pfsevp.dtsi | 155 ++++++++++++++++++ 5 files changed, 276 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index f18477b2e86d..ea14afab0010 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp-emmc.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp-sdcard.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/= riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi new file mode 100644 index 000000000000..7b9ee13b6a3a --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts b/arch/= riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts new file mode 100644 index 000000000000..3a656c982781 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs-m100pfsevp.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + model =3D "Aries Embedded M100PFEVPS eMMC"; + compatible =3D "aries,m100pfsevp-emmc", "microchip,mpfs"; +}; + +&gpio0 { + emmc-sel-hog { + gpio-hog; + gpios =3D <12 0>; + output-low; + }; +}; + +&mmc { + max-frequency =3D <50000000>; + bus-width =3D <8>; + cap-mmc-highspeed; + no-1-8-v; + non-removable; + disable-wp; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts b/arc= h/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts new file mode 100644 index 000000000000..90fdeac22d24 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs-m100pfsevp.dtsi" + +/ { + model =3D "Aries Embedded M100PFEVPS sd-card"; + compatible =3D "aries,m100pfsevp-sdcard", "microchip,mpfs"; +}; + +&gpio0 { + sdcard-sel-hog { + gpio-hog; + gpios =3D <12 0>; + output-high; + }; +}; + +&mmc { + max-frequency =3D <50000000>; + bus-width =3D <4>; + no-1-8-v; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + disable-wp; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi b/arch/risc= v/boot/dts/microchip/mpfs-m100pfsevp.dtsi new file mode 100644 index 000000000000..e6b6b4647e42 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-m100pfs-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + aliases { + ethernet0 =3D &mac0; + ethernet1 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + gpio0 =3D &gpio0; + gpio1 =3D &gpio2; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + }; + ddrc_cache_hi: memory@1040000000 { + device_type =3D "memory"; + reg =3D <0x10 0x40000000 0x0 0x40000000>; + }; +}; + +&can0 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +&gpio0 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>; + ngpios =3D <14>; + status =3D "okay"; + + pmic-irq-hog { + gpio-hog; + gpios =3D <13 0>; + input; + }; +}; + +&gpio2 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>, <27>, <28>, + <29>, <30>, <31>, <32>, + <33>, <34>, <35>, <36>, + <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>; + status =3D "okay"; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy1>; + phy1: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&pcie { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "host"; +}; --=20 2.36.1