From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82F62ECAAD4 for ; Fri, 26 Aug 2022 14:28:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244032AbiHZO2z (ORCPT ); Fri, 26 Aug 2022 10:28:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230151AbiHZO2r (ORCPT ); Fri, 26 Aug 2022 10:28:47 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36DFFA1D34; Fri, 26 Aug 2022 07:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524126; x=1693060126; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ekaeoHamQzWRDEGag5x7p5HDua4LhMsX4qQRAr9Esd4=; b=GdWCq6TlzN+ga2amxKgEjvZ0uBxBRyZZUOdvaakOWEDCFw2Y9NeMqwbi aitJWRYvFfiNRtNKX5BGK6/48+9+cjVCm2uC92i1gTyn4d23cpXPXnR8o FNdomizDEO+HO+qGmcZgkHIAnsSaCzFBGjk9clp5jksDG9erUYvSjpecf 1YiAmpfhM1yzBG/LkcFzomIgsn4MpoUqCe34ubqs4CRK3e5FS/nKciCEH GY01+iArvt43EKCDOzjZlEGK8jKOAcsf9HHSDtmBiRatWW9dZMtZrzmhe NyzM/bwtnGkQEJGXLSHxlTQx60DjNNeO0VfVT6VZrcbwvDOQen2o4K6/p A==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="174335886" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:28:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:28:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:28:41 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 1/9] dt-bindings: riscv: microchip: document icicle reference design Date: Fri, 26 Aug 2022 15:27:59 +0100 Message-ID: <20220826142806.3658434-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The icicle kit reference design's v2022.09 release,made some changes to the memory map - including adding the ability to read the fabric clock controllers via the system controller bus & making the PCI controller work with upstream Linux. While the PCI was not working in the v2022.03 design, so nothing is broken there in terms of backwards compatibility, the fabric clocks used in the v2022.03 design were chosen by the individual run of the synthesis tool. In the v2022.09 reference design, the clocks are fixed to use the "north west" fabric Clock Conditioning Circuitry. Make use of a new compatible to denote that this is not backwards compatible. Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Krzysztof: you acked this patch in another series, but I moved it here and reworked the patch contents to make the relationship between the compatibles clearer. Since it is basically a new patch just with the same intent, I dropped your ack. --- .../devicetree/bindings/riscv/microchip.yaml | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 1aa7336a9672..7cfc96c21ab0 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -17,12 +17,17 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - microchip,mpfs-icicle-kit - - microchip,mpfs-icicle-reference-rtlv2203 - - sundance,polarberry - - const: microchip,mpfs + oneOf: + - items: + - enum: + - microchip,mpfs-icicle-reference-rtlv2203 + - microchip,mpfs-icicle-reference-rtlv2209 + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs + + - items: + - const: sundance,polarberry + - const: microchip,mpfs =20 additionalProperties: true =20 --=20 2.36.1 From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2362ECAAA3 for ; Fri, 26 Aug 2022 14:29:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344230AbiHZO3G (ORCPT ); Fri, 26 Aug 2022 10:29:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243240AbiHZO2w (ORCPT ); Fri, 26 Aug 2022 10:28:52 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 593CFA2D9F; Fri, 26 Aug 2022 07:28:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524131; x=1693060131; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7FfH98vN3G1c0zazEIRp+BvmsgR+SbY6HrQ2ERp2AsM=; b=uOgld4d0ubaPgW6miy7y2GWOWShytuPCkdWu0Gv7wGhYn/gJnqbke9Aw bDRcdgo1iEZA7qbZoIDWoFkciO2WYeT4YuNAE8a5rMuMyPL5y0n5yn3Vv EiVNZ/W7HIpgZxUoPKVWnwEmgvWfjFWBxEy0DLBvCefPJdUqrfxzAv1tS 9cCuiFl+6tzbeTAwV6VMq5OFZAHdrVDAfU4ykk2ZoC50tD4ItvHmjgYAW 85QWwSkzLBKul2sYnQIRqmE4VgGmxrm7szgllJ9KAuGBKpzoRA5+xa7cr LqgQXIOo0K1dXNdq1lPtumCxKjMiVA1DNnjnGkRVua9ygQK+vgaOj2Q6p w==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="110917571" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:28:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:28:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:28:44 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp Date: Fri, 26 Aug 2022 15:28:00 +0100 Message-ID: <20220826142806.3658434-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatibles for both configurations of the Aries Embedded M100PFSEVP SOM + EVK platform. Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-s= om-mpfs025t-pcie-serdes Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 7cfc96c21ab0..04ebd48caaa7 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -26,9 +26,13 @@ properties: - const: microchip,mpfs =20 - items: - - const: sundance,polarberry + - enum: + - aries,m100pfsevp-emmc + - aries,m100pfsevp-sdcard + - sundance,polarberry - const: microchip,mpfs =20 + additionalProperties: true =20 ... --=20 2.36.1 From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5A56ECAAD4 for ; Fri, 26 Aug 2022 14:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344242AbiHZO3D (ORCPT ); Fri, 26 Aug 2022 10:29:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242796AbiHZO2w (ORCPT ); Fri, 26 Aug 2022 10:28:52 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18B06A2202; Fri, 26 Aug 2022 07:28:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524131; x=1693060131; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dymLK74hLsKZYKnCiDdXxOUqxIzAIxjPdTu2h4+/Loo=; b=Jt+iAQ7wrb+xT+DXY9kzFcnBIdktVeFRbho/WGFz65qQ3nzQ8lXD/9Xa HUj+6FjG5Wzp6RlouIdwEVqK0iJqRBRt/rvFDFP7YT3pEjhjJlu+7EZw6 W0fMcRx3izu1ORkUqO34676cbDf/TkcLNK2TJGQPIHM35HrCnpCp+t5bR spJ/+zrUHYA8Bi5x1zAHG2BGdtCI4mWx0iinMVBuF84YgMf7iyFk5dQbj Rx3Q86APHLtXiG1SI4Ybuo3j/s3vA6SB1FuKjVaEUMsg9/JlCPDa7MPK2 vMA3sAyRqi2gAGmCY/qfSzJCTVgr7irjlTA2JjfPHv+eRGSXg5eOgbJEs Q==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="171133588" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:28:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:28:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:28:47 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 3/9] dt-bindings: riscv: microchip: document the sev kit Date: Fri, 26 Aug 2022 15:28:01 +0100 Message-ID: <20220826142806.3658434-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shravan Chippa Update devicetree bindings document with PolarFire SoC Video Kit, known by its "sev-kit" product code. Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77= E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Shravan Chippa Signed-off-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/riscv/microchip.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 04ebd48caaa7..f8b9a3288437 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -29,10 +29,10 @@ properties: - enum: - aries,m100pfsevp-emmc - aries,m100pfsevp-sdcard + - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs =20 - additionalProperties: true =20 ... --=20 2.36.1 From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F72EECAAD6 for ; Fri, 26 Aug 2022 14:29:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344446AbiHZO3L (ORCPT ); Fri, 26 Aug 2022 10:29:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243995AbiHZO2z (ORCPT ); Fri, 26 Aug 2022 10:28:55 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39007A0314; Fri, 26 Aug 2022 07:28:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524134; x=1693060134; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hyLDKbNNI38wXrC5Tei7bV2mB9uLlpphPD5ViUjlS80=; b=SnrudLFlDwc0QjtzkKew3HKXo9Lw65I44CmFMx9wNgV+emJG6fZ//eQq IR5uLx5U+zWUpv2EK8Gvd//cR6oVkCFB19sV0NX6PXquM3bOvhMQyUN/Q 4SIG4cmgBuVC9N7HBAGEDYJKimP0YmScn5sRxRVtqYwoZK7RFCIehj9zI uE+hYr8mus02X4f0njWfM/kLtgxNTWlVrVzEL82Yn96hd6Gm+z789d1V8 L3bIwnfjGyYwl3eQoT/CQsSp1mFM5P1r9MtZVqEEio81wwoeEJnX9mTBo ntQAXo/0RNCbiZhM9+XCuK7T5Ho6CAnQC7fohjK94t3Ud5kGA5njNP8YK Q==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="178024787" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:28:53 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:28:53 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:28:50 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit Date: Fri, 26 Aug 2022 15:28:02 +0100 Message-ID: <20220826142806.3658434-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The recently removed, accidentally included, "matr0" property was used in place of a dma-ranges property. The PCI controller is non-functional with mainline Linux in the v2022.02 or later reference designs and has not worked without configuration of address-translation since v2021.08. Add the address translation that will be used by the v2022.09 reference design & update the compatible used by the dts. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 7 ++++++- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..c0fb9dd7b2c8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,7 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { - compatible =3D "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpf= s"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; @@ -37,3 +38,7 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; }; + +&pcie { + dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index f3f87ed2007f..5e2b8aa2ff64 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -11,7 +11,8 @@ =20 / { model =3D "Microchip PolarFire-SoC Icicle Kit"; - compatible =3D "microchip,mpfs-icicle-kit", "microchip,mpfs"; + compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", + "microchip,mpfs"; =20 aliases { ethernet0 =3D &mac1; --=20 2.36.1 From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D55CCECAAD4 for ; Fri, 26 Aug 2022 14:29:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344246AbiHZO3O (ORCPT ); Fri, 26 Aug 2022 10:29:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343978AbiHZO3B (ORCPT ); Fri, 26 Aug 2022 10:29:01 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CBBAA3D3D; Fri, 26 Aug 2022 07:28:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524139; x=1693060139; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5en4qBuVzdeyn5IGKXiQxzbRqw1ndSal365HolbPArY=; b=fwNqXo62ByzQ/yvAVbv4ad/6DCUSiFEyO9hUKnuPrSo9JbbEoRIy4h/Q 6+lrKOQ282Ox8M3aWxF5fjMsHGhASR1Fe1pSt2ZoPM/WK/+RbOZ+WsUKs ps5HLIkrAiVA8PCcUD7rJeyqji3d/ZhgAOvyTcLlRRqYYoG0p+vHjUqf8 YXw6y79vWJJ1ClKjHMn4sYeQagpRuEzOlPeBBV65TXJxgunZlRoAiqpgQ 4mj12b52VJyPhBoFfHXyr6vAK4UlA0zu6zJBSazsyjBfIEHTBBPd4TXvS kTb44ctUSal+2PsQQZhC0WIgtIFZdOPbRFZMy4682TwcCIh+dQalQ5qkI w==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="110917604" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:28:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:28:56 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:28:53 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Date: Fri, 26 Aug 2022 15:28:03 +0100 Message-ID: <20220826142806.3658434-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In today's edition of moving things around: The PCIe root port on PolarFire SoC is more part of the FPGA than of the Core Complex. It is located on the other side of the chip and, apart from its interrupts, most of its configuration is determined by the FPGA bitstream rather. This includes: - address translation in both directions - the addresses at which the config and data regions appear to the core complex - the clocks used by the AXI bus - the plic interrupt used Moving the PCIe node to the -fabric.dtsi makes it clearer than a singular configuration for root port is not correct & allows the base SoC dtsi to be more easily included. Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 32 +++++++++++++++++-- .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 ----------------- 3 files changed, 58 insertions(+), 32 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index c0fb9dd7b2c8..a21440c8ee03 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -37,8 +37,34 @@ fabric_clk1: fabric-clk1 { #clock-cells =3D <0>; clock-frequency =3D <125000000>; }; -}; =20 -&pcie { - dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 49380c428ec9..67303bc0e451 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -13,4 +13,33 @@ fabric_clk1: fabric-clk1 { #clock-cells =3D <0>; clock-frequency =3D <125000000>; }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index a1176260086a..5974066298e1 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -464,35 +464,6 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - pcie: pcie@2000000000 { - compatible =3D "microchip,pcie-host-1.0"; - #address-cells =3D <0x3>; - #interrupt-cells =3D <0x1>; - #size-cells =3D <0x2>; - device_type =3D "pci"; - reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names =3D "cfg", "apb"; - bus-range =3D <0x0 0x7f>; - interrupt-parent =3D <&plic>; - interrupts =3D <119>; - interrupt-map =3D <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask =3D <0 0 0 7>; - clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names =3D "fic0", "fic1", "fic3"; - ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent =3D <&pcie>; - msi-controller; - status =3D "disabled"; - pcie_intc: interrupt-controller { - #address-cells =3D <0>; - #interrupt-cells =3D <1>; - interrupt-controller; - }; - }; - mbox: mailbox@37020000 { compatible =3D "microchip,mpfs-mailbox"; reg =3D <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; --=20 2.36.1 From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6239ECAAD6 for ; Fri, 26 Aug 2022 14:29:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344466AbiHZO3U (ORCPT ); Fri, 26 Aug 2022 10:29:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241450AbiHZO3D (ORCPT ); Fri, 26 Aug 2022 10:29:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B28E5A5C61; Fri, 26 Aug 2022 07:29:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524140; x=1693060140; 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Fri, 26 Aug 2022 07:28:56 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 6/9] riscv: dts: microchip: icicle: update pci address properties Date: Fri, 26 Aug 2022 15:28:04 +0100 Message-ID: <20220826142806.3658434-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index a21440c8ee03..32d51c4a5b0c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { + compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", "microchip,mpfs"; =20 @@ -38,13 +39,13 @@ fabric_clk1: fabric-clk1 { clock-frequency =3D <125000000>; }; =20 - pcie: pcie@2000000000 { + pcie: pcie@3000000000 { compatible =3D "microchip,pcie-host-1.0"; #address-cells =3D <0x3>; #interrupt-cells =3D <0x1>; #size-cells =3D <0x2>; device_type =3D "pci"; - reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg =3D <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; reg-names =3D "cfg", "apb"; bus-range =3D <0x0 0x7f>; interrupt-parent =3D <&plic>; @@ -54,9 +55,9 @@ pcie: pcie@2000000000 { <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask =3D <0 0 0 7>; - clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names =3D "fic0", "fic1", "fic3"; - ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + clocks =3D <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; dma-ranges =3D <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; msi-parent =3D <&pcie>; msi-controller; --=20 2.36.1 From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D3AECAAA3 for ; Fri, 26 Aug 2022 14:29:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344474AbiHZO3W (ORCPT ); Fri, 26 Aug 2022 10:29:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344426AbiHZO3E (ORCPT ); Fri, 26 Aug 2022 10:29:04 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C78FA2860; Fri, 26 Aug 2022 07:29:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524143; x=1693060143; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rZMihXhOLlKxYs0tCwQAUj7e9S0faqqljRoP4WeBM6o=; b=Uc3osrtrPpmBIyJRfd+YiFCj9LJF7t3p/uKItdOsmi1TYXYfDOBoLGG/ E3g0c/0JjGcnQi0akTPchPhMPGiwq+4zdeLEWUWQlOAhP023J4OQj6p7h OQY6HGZaRPWP96XwZRdaZeHIrrYACjxtyaT7f7LR64dpikxve8JrhyW9r QCJlxVtjrNp2Vl6ywyc7yq+663km3pISOWDPXAzYAjgZLeZVjJK+0VEqp VXa4HXMEksLGDYW0euwgQZjqHfTR2rWdKbkUYNIE9SYZu+eFKb2d89rXD r7y76Z1YZ/domnJ2FpwlTjqokJfBSR/i4zGNzHmy13Q29BczH6gdY7CBp Q==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="188209210" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:29:02 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:29:02 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:28:59 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Date: Fri, 26 Aug 2022 15:28:05 +0100 Message-ID: <20220826142806.3658434-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When users try to add onto the reference design, they find that the current addresses that peripherals connected to Fabric InterConnect (FIC) 3 use are restrictive. For the v2022.09 reference design, the peripherals have been shifted down, leaving more contiguous address space for their custom IP/peripherals. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 32d51c4a5b0c..98f04be0dc6b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -6,18 +6,18 @@ / { compatible =3D "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpf= s-icicle-kit", "microchip,mpfs"; =20 - core_pwm0: pwm@41000000 { + core_pwm0: pwm@40000000 { compatible =3D "microchip,corepwm-rtl-v4"; - reg =3D <0x0 0x41000000 0x0 0xF0>; + reg =3D <0x0 0x40000000 0x0 0xF0>; microchip,sync-update-mask =3D /bits/ 32 <0>; #pwm-cells =3D <2>; clocks =3D <&fabric_clk3>; status =3D "disabled"; }; =20 - i2c2: i2c@44000000 { + i2c2: i2c@40000200 { compatible =3D "microchip,corei2c-rtl-v7"; - reg =3D <0x0 0x44000000 0x0 0x1000>; + reg =3D <0x0 0x40000200 0x0 0x1000>; #address-cells =3D <1>; #size-cells =3D <0>; clocks =3D <&fabric_clk3>; --=20 2.36.1 From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1333ECAAD4 for ; Fri, 26 Aug 2022 14:29:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344517AbiHZO3m (ORCPT ); Fri, 26 Aug 2022 10:29:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344429AbiHZO3O (ORCPT ); Fri, 26 Aug 2022 10:29:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46209A74EE; Fri, 26 Aug 2022 07:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661524150; x=1693060150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wYLnJ/r2/6cv7cgLTA2f55BdTU7OBp01DEfsGbye9PI=; b=fcrFjlL95wxOnAeTyDviVw2S8dUAiJGl8H71zEAfW6OtmzeJpPvWO7S6 HoznQka5QKD5TPBS/LZDplcJhAUxPwn0/Y7Mlef6dNvgE+OTnCDo/FTeo 9pkMyl6Ft8RUW6SkWWpvv675yRuADQLIDQnUN1iYiwSrNSryvgp57pR03 Rf2BYfJntI3tyMEussFHP/wwYlpPyN/tYzstPkhylAyIty+UbZnmWQUG/ MuVO8wjG4k91RgrlLRzn6mpfYE7ilSf68Zu31hOIT2RUKHTmTBkET3sr7 KmOqo/DpicMSg0P6SbZTo3XZXFK1Dyfyy2HqdszFTia4mDwncXbx/sXcr A==; X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="174335928" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:29:08 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:29:05 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:29:02 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 8/9] riscv: dts: microchip: add sevkit device tree Date: Fri, 26 Aug 2022 15:28:06 +0100 Message-ID: <20220826142806.3658434-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vattipalli Praveen Add a basic dts for the Microchip Smart Embedded Vision dev kit. The SEV kit is an upcoming first party board, featuring an MPFS250T and: - Dual Sony Camera Sensors (IMX334) - IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi - Bluetooth 5 Low Energy - 4 GB DDR4 x64 - 2 GB LPDDR4 x32 - 1 GB SPI Flash - 8 GB eMMC flash & SD card slot (multiplexed) - HDMI2.0 Video Input/Output - MIPI DSI Output - MIPI CSI-2 Input Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77= E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Vattipalli Praveen Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 ++++++ .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index 39aae7b04f1c..f18477b2e86d 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi b/arch/= riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi new file mode 100644 index 000000000000..8545baf4d129 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/bo= ot/dts/microchip/mpfs-sev-kit.dts new file mode 100644 index 000000000000..e810ad453452 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-sev-kit-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "Microchip PolarFire-SoC SEV Kit"; + compatible =3D "microchip,mpfs-sev-kit", "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + fabricbuf0ddrc: buffer@80000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x80000000 0x0 0x2000000>; + }; + + fabricbuf1ddrnc: buffer@c4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0xc4000000 0x0 0x4000000>; + }; + + fabricbuf2ddrncwcb: buffer@d4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0xd4000000 0x0 0x4000000>; + }; + }; + + ddrc_cache: memory@1000000000 { + device_type =3D "memory"; + reg =3D <0x10 0x0 0x0 0x76000000>; + }; +}; + +&i2c0 { + status =3D "okay"; +}; + +&gpio2 { + interrupts =3D <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status =3D "okay"; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; + phy1: ethernet-phy@9 { + reg =3D <9>; + }; + phy0: ethernet-phy@8 { + reg =3D <8>; + }; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy1>; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + status =3D "okay"; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "otg"; +}; --=20 2.36.1 From nobody Tue Apr 7 14:52:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28C8BECAAD4 for ; Fri, 26 Aug 2022 14:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344454AbiHZO3e (ORCPT ); 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X-IronPort-AV: E=Sophos;i="5.93,265,1654585200"; d="scan'208";a="178024821" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 07:29:08 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 07:29:07 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 07:29:05 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , , , Subject: [PATCH 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Date: Fri, 26 Aug 2022 15:28:07 +0100 Message-ID: <20220826142806.3658434-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220826142806.3658434-1-conor.dooley@microchip.com> References: <20220826142806.3658434-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device trees for both configs used by the Aries Embedded M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM, featuring: - 2GB DDR4 SDRAM dedicated to the HMS - 512MB DDR4 SDRAM dedicated to the FPGA - 32 MB SPI NOR Flash - 4 GByte eMMC and a carrier board with: - 2x Gigabit Ethernet - USB - 2x UART - 2x CAN - TFT connector - HSMC extension connector - 3x PMOD extension connectors - microSD-card slot Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-s= om-mpfs025t-pcie-serdes Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchi= p-soc-fpga-m100pfsevp-riscv-hsmc-pmod Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFS= EVP-Schematics.pdf Co-developed-by: Wolfgang Grandegger Signed-off-by: Wolfgang Grandegger Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 2 + .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++ .../dts/microchip/mpfs-m100pfsevp-emmc.dts | 37 +++++ .../dts/microchip/mpfs-m100pfsevp-sdcard.dts | 37 +++++ .../boot/dts/microchip/mpfs-m100pfsevp.dtsi | 155 ++++++++++++++++++ 5 files changed, 276 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index f18477b2e86d..ea14afab0010 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp-emmc.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-m100pfsevp-sdcard.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/= riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi new file mode 100644 index 000000000000..7b9ee13b6a3a --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + pcie: pcie@2000000000 { + compatible =3D "microchip,pcie-host-1.0"; + #address-cells =3D <0x3>; + #interrupt-cells =3D <0x1>; + #size-cells =3D <0x2>; + device_type =3D "pci"; + reg =3D <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names =3D "cfg", "apb"; + bus-range =3D <0x0 0x7f>; + interrupt-parent =3D <&plic>; + interrupts =3D <119>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + clocks =3D <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names =3D "fic0", "fic1", "fic3"; + ranges =3D <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent =3D <&pcie>; + msi-controller; + status =3D "disabled"; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts b/arch/= riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts new file mode 100644 index 000000000000..3a656c982781 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs-m100pfsevp.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + model =3D "Aries Embedded M100PFEVPS eMMC"; + compatible =3D "aries,m100pfsevp-emmc", "microchip,mpfs"; +}; + +&gpio0 { + emmc-sel-hog { + gpio-hog; + gpios =3D <12 0>; + output-low; + }; +}; + +&mmc { + max-frequency =3D <50000000>; + bus-width =3D <8>; + cap-mmc-highspeed; + no-1-8-v; + non-removable; + disable-wp; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts b/arc= h/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts new file mode 100644 index 000000000000..90fdeac22d24 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs-m100pfsevp.dtsi" + +/ { + model =3D "Aries Embedded M100PFEVPS sd-card"; + compatible =3D "aries,m100pfsevp-sdcard", "microchip,mpfs"; +}; + +&gpio0 { + sdcard-sel-hog { + gpio-hog; + gpios =3D <12 0>; + output-high; + }; +}; + +&mmc { + max-frequency =3D <50000000>; + bus-width =3D <4>; + no-1-8-v; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + disable-wp; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi b/arch/risc= v/boot/dts/microchip/mpfs-m100pfsevp.dtsi new file mode 100644 index 000000000000..e6b6b4647e42 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-m100pfs-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + aliases { + ethernet0 =3D &mac0; + ethernet1 =3D &mac1; + serial0 =3D &mmuart0; + serial1 =3D &mmuart1; + serial2 =3D &mmuart2; + serial3 =3D &mmuart3; + serial4 =3D &mmuart4; + gpio0 =3D &gpio0; + gpio1 =3D &gpio2; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x40000000>; + }; + ddrc_cache_hi: memory@1040000000 { + device_type =3D "memory"; + reg =3D <0x10 0x40000000 0x0 0x40000000>; + }; +}; + +&can0 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +&gpio0 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>; + ngpios =3D <14>; + status =3D "okay"; + + pmic-irq-hog { + gpio-hog; + gpios =3D <13 0>; + input; + }; +}; + +&gpio2 { + interrupts =3D <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>, <27>, <28>, + <29>, <30>, <31>, <32>, + <33>, <34>, <35>, <36>, + <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>; + status =3D "okay"; +}; + +&mac0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy1>; + phy1: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmuart1 { + status =3D "okay"; +}; + +&mmuart2 { + status =3D "okay"; +}; + +&mmuart3 { + status =3D "okay"; +}; + +&mmuart4 { + status =3D "okay"; +}; + +&pcie { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; +}; + +&spi1 { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + dr_mode =3D "host"; +}; --=20 2.36.1