From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4542BECAAD2 for ; Fri, 26 Aug 2022 08:37:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245757AbiHZIh0 (ORCPT ); Fri, 26 Aug 2022 04:37:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343675AbiHZIhN (ORCPT ); Fri, 26 Aug 2022 04:37:13 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 850E2D3451; Fri, 26 Aug 2022 01:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661503032; x=1693039032; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Vdr3+Nsguq4PGVOxtmLngGRI+Gao0SjewAh2bRon6EQ=; b=qm9qQVeYqEvKmMeupsFBz+VgYIcc/qosdLzZaBMabuylPKqxAmq/LTPu BrIAe14dDLJ6/Jcr8lsoITldCrAVjfWpxoZCl7rdAvIkkdvG/1CmDGUGA zY6xdPu5/+Ca14qEoorpY3+5rTBSat5GhFnoBUoeHy2M/x1ypR9GSqxLp 44OSkgPUdb44kfrerDebl2vi1iHrzE3fm2LYR7wxwzWTfJWn+sGTxP6HM 4fJomyEPZ8MFsofNHF51/DDPxLQPUm3zK4UPd+k/whEvFytTrhi9CWYQD ySmB10pTa9JgFElC7UcLCA4q5iKXFTdtkmpS2O2dAUOlWkyHtDmU9MaEM Q==; X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="174284213" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:12 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:10 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:08 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 1/9] ARM: configs: at91: remove CONFIG_MICROCHIP_PIT64B Date: Fri, 26 Aug 2022 11:39:19 +0300 Message-ID: <20220826083927.3107272-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since commit f611af4c3bfa ("ARM: at91: Kconfig: implement PIT64B selection") there is no need to explicitly select PIT64B. Fixes: f611af4c3bfa ("ARM: at91: Kconfig: implement PIT64B selection") Signed-off-by: Claudiu Beznea --- This is based on patch at [1]. [1] https://lore.kernel.org/all/20220818135522.3143514-2-arnd@kernel.org/ arch/arm/configs/at91_dt_defconfig | 1 - arch/arm/configs/sama7_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_= defconfig index 5cc72266eaff..9ea08337b174 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -196,7 +196,6 @@ CONFIG_RTC_DRV_AT91SAM9=3Dy CONFIG_DMADEVICES=3Dy CONFIG_AT_HDMAC=3Dy CONFIG_AT_XDMAC=3Dy -CONFIG_MICROCHIP_PIT64B=3Dy # CONFIG_IOMMU_SUPPORT is not set CONFIG_IIO=3Dy CONFIG_AT91_ADC=3Dy diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defc= onfig index 8803536854c6..72af50d9e48a 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -188,7 +188,6 @@ CONFIG_RTC_DRV_AT91SAM9=3Dy CONFIG_DMADEVICES=3Dy CONFIG_AT_XDMAC=3Dy CONFIG_STAGING=3Dy -CONFIG_MICROCHIP_PIT64B=3Dy # CONFIG_IOMMU_SUPPORT is not set CONFIG_IIO=3Dy CONFIG_IIO_SW_TRIGGER=3Dy --=20 2.34.1 From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3FABECAAA3 for ; Fri, 26 Aug 2022 08:37:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245282AbiHZIha (ORCPT ); Fri, 26 Aug 2022 04:37:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343679AbiHZIhR (ORCPT ); Fri, 26 Aug 2022 04:37:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B89F0D5700; Fri, 26 Aug 2022 01:37:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661503035; x=1693039035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R+ZXodYH0NjgQV+jNwarfE1Vs8mAKES25AbetN8LplY=; b=2LkRQ/vcglasjXx+CsFkoM/wGiX2wbJci3BvNuvCVo3aQOr1eZqTq/MR 2bqt6UHjzMZnkBdQ4MKcTVXxVQCyAJ9xr04eTfJuol3gJuxyK8Ktb/awg EGB9Llrlz5Gcz5qbECKbTpMIYfs6hVa06hDzI5vhddtbfLo8QwqFg1nDW fB0jYY3a9Er70L9vwtgbYVk8abmmGceXHIjVjdQoqHUk/hHzLoqpF2gqr MPPjWox4AxMmUzE7bT7aa8U3YiU0SsfFtfKYxnrTP7ULRg13k7fSIheth AfyCVWb8lIdWlc7eqIyCEO/Oxk+SHKpNaGnA6kOkmm8mF7bZlyIOzxY7i A==; X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="174284217" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:15 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:13 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:11 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , "Frederic Schumacher" Subject: [PATCH 2/9] ARM: at91: pm: fix self-refresh for sama7g5 Date: Fri, 26 Aug 2022 11:39:20 +0300 Message-ID: <20220826083927.3107272-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It has been discovered that on some parts, from time to time, self-refresh procedure doesn't work as expected. Debugging and investigating it proved that disabling AC DLL introduce glitches in RAM controllers which leads to unexpected behavior. This is confirmed as a hardware bug. DLL bypass disables 3 DLLs: 2 DX DLLs and AC DLL. Thus, keep only DX DLLs disabled. This introduce 6mA extra current consumption on VDDCORE when switching ot any ULP mode or standby mode but the self-refresh procedure still works. Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") Suggested-by: Frederic Schumacher Signed-off-by: Claudiu Beznea Tested-by: Cristian Birsan --- arch/arm/mach-at91/pm_suspend.S | 24 +++++++++++++++++------- include/soc/at91/sama7-ddr.h | 4 ++++ 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspen= d.S index abe4ced33eda..ffed4d949042 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -172,9 +172,15 @@ sr_ena_2: /* Put DDR PHY's DLL in bypass mode for non-backup modes. */ cmp r7, #AT91_PM_BACKUP beq sr_ena_3 - ldr tmp1, [r3, #DDR3PHY_PIR] - orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP - str tmp1, [r3, #DDR3PHY_PIR] + + /* Disable DX DLLs. */ + ldr tmp1, [r3, #DDR3PHY_DX0DLLCR] + orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS + str tmp1, [r3, #DDR3PHY_DX0DLLCR] + + ldr tmp1, [r3, #DDR3PHY_DX1DLLCR] + orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS + str tmp1, [r3, #DDR3PHY_DX1DLLCR] =20 sr_ena_3: /* Power down DDR PHY data receivers. */ @@ -221,10 +227,14 @@ sr_ena_3: bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 str tmp1, [r3, #DDR3PHY_DSGCR] =20 - /* Take DDR PHY's DLL out of bypass mode. */ - ldr tmp1, [r3, #DDR3PHY_PIR] - bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP - str tmp1, [r3, #DDR3PHY_PIR] + /* Enable DX DLLs. */ + ldr tmp1, [r3, #DDR3PHY_DX0DLLCR] + bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS + str tmp1, [r3, #DDR3PHY_DX0DLLCR] + + ldr tmp1, [r3, #DDR3PHY_DX1DLLCR] + bic tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS + str tmp1, [r3, #DDR3PHY_DX1DLLCR] =20 /* Enable quasi-dynamic programming. */ mov tmp1, #0 diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index 9e17247474fa..2706bc48c076 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -39,6 +39,10 @@ =20 #define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */ =20 +#define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register = */ +#define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register = */ +#define DDR3PHY_DXDLLCR_DLLDIS (1 << 31) /* DLL Disable */ + /* UDDRC */ #define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */ #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-re= fresh */ --=20 2.34.1 From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 348C0ECAAA3 for ; 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X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="177981552" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:17 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:16 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:14 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , "Frederic Schumacher" Subject: [PATCH 3/9] ARM: at91: pm: fix DDR recalibration when resuming from backup and self-refresh Date: Fri, 26 Aug 2022 11:39:21 +0300 Message-ID: <20220826083927.3107272-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On SAMA7G5, when resuming from backup and self-refresh, the bootloader performs DDR PHY recalibration by restoring the value of ZQ0SR0 (stored in RAM by Linux before going to backup and self-refresh). It has been discovered that the current procedure doesn't work for all possible values that might go to ZQ0SR0 due to hardware bug. The workaround to this is to avoid storing some values in ZQ0SR0. Thus Linux will read the ZQ0SR0 register and cache its value in RAM after processing it (using modified_gray_code array). The bootloader will restore the processed value. Fixes: d2d4716d8384 ("ARM: at91: pm: save ddr phy calibration data to secur= am") Suggested-by: Frederic Schumacher Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 36 ++++++++++++++++++++++++++++++++---- include/soc/at91/sama7-ddr.h | 4 ++++ 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index df6d673e83d5..f4501dea98b0 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -541,9 +541,41 @@ extern u32 at91_pm_suspend_in_sram_sz; =20 static int at91_suspend_finish(unsigned long val) { + unsigned char modified_gray_code[] =3D { + 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, + 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, + 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, + 0x10, 0x11, + }; + unsigned int tmp, index; int i; =20 if (soc_pm.data.mode =3D=3D AT91_PM_BACKUP && soc_pm.data.ramc_phy) { + /* + * Bootloader will perform DDR recalibration and will try to + * restore the ZQ0SR0 with the value saved here. But the + * calibration is buggy and restoring some values from ZQ0SR0 + * is forbidden and risky thus we need to provide processed + * values for these (modified gray code values). + */ + tmp =3D readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); + + /* Store pull-down output impedance select. */ + index =3D (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; + soc_pm.bu->ddr_phy_calibration[0] =3D modified_gray_code[index]; + + /* Store pull-up output impedance select. */ + index =3D (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + + /* Store pull-down on-die termination impedance select. */ + index =3D (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + + /* Store pull-up on-die termination impedance select. */ + index =3D (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + /* * The 1st 8 words of memory might get corrupted in the process * of DDR PHY recalibration; it is saved here in securam and it @@ -1066,10 +1098,6 @@ static int __init at91_pm_backup_init(void) of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); if (!located) goto securam_fail; - - /* DDR3PHY_ZQ0SR0 */ - soc_pm.bu->ddr_phy_calibration[0] =3D readl(soc_pm.data.ramc_phy + - 0x188); } =20 return 0; diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index 2706bc48c076..6ce3bd22f6c6 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -38,6 +38,10 @@ #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */ =20 #define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */ +#define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select= offset */ +#define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select o= ffset */ +#define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination im= pedance select offset */ +#define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impe= dance select offset */ =20 #define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register = */ #define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register = */ --=20 2.34.1 From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F32A2ECAAD6 for ; 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X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="171082251" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:19 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:16 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 4/9] ARM: dts: at91: sama5d27_wlsom1: specify proper regulator output ranges Date: Fri, 26 Aug 2022 11:39:22 +0300 Message-ID: <20220826083927.3107272-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Min and max output ranges of regulators need to satisfy board requirements not PMIC requirements. Thus adjust device tree to cope with this. Fixes: 5d4c3cfb63fe ("ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 = and wlsom1-ek") Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dt= s/at91-sama5d27_wlsom1.dtsi index 76b2025c67b4..342fcfd974d7 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -76,8 +76,8 @@ mcp16502@5b { regulators { vdd_3v3: VDD_IO { regulator-name =3D "VDD_IO"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <3700000>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -95,8 +95,8 @@ regulator-state-mem { =20 vddio_ddr: VDD_DDR { regulator-name =3D "VDD_DDR"; - regulator-min-microvolt =3D <600000>; - regulator-max-microvolt =3D <1850000>; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -118,8 +118,8 @@ regulator-state-mem { =20 vdd_core: VDD_CORE { regulator-name =3D "VDD_CORE"; - regulator-min-microvolt =3D <600000>; - regulator-max-microvolt =3D <1850000>; + regulator-min-microvolt =3D <1250000>; + regulator-max-microvolt =3D <1250000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -160,8 +160,8 @@ regulator-state-mem { =20 LDO1 { regulator-name =3D "LDO1"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <3700000>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; regulator-always-on; =20 regulator-state-standby { @@ -175,8 +175,8 @@ regulator-state-mem { =20 LDO2 { regulator-name =3D "LDO2"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <3700000>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; regulator-always-on; =20 regulator-state-standby { --=20 2.34.1 From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BCDDECAAD2 for ; Fri, 26 Aug 2022 08:37:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245539AbiHZIhn (ORCPT ); Fri, 26 Aug 2022 04:37:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245079AbiHZIhf (ORCPT ); Fri, 26 Aug 2022 04:37:35 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72296D2E9B; Fri, 26 Aug 2022 01:37:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661503044; x=1693039044; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+r0teR5Z05cLjaJ2Oi+EBrUZGdwZdyE4dwfYDD+PJTE=; b=RPOcBPkFCfKz8MnhnvOPcFynQ3Ja7bzwpi2fKJ4rvqsdGJ0Tac9i3+iN 8iE++0F0whSDGTG3VkUF6acZS7SmUnLOBwv14sz7WmVGKw563RikRCiy0 5+GkPWaHWsfaoDtheto8mIUY4MhoZEJ70w0qgMO4sxf26csXyEuKstaNk JoVxa8ilLXcgb97qgNhBei1AggAOyiye6eOJJh/5+x1+mm3ujg2+LJsGv QoVerXvzo2yeoq40zwMMUwic50F2V8Yl1vJBJvrxEfYpVCCvPzbU4LTG2 kqi6mDsj2pVDxiUKqiU/CNYC4KAHt8+wI9NUZRT9Vs/bsbGYRWoesPF2I w==; X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="171082261" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:23 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:22 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:19 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 5/9] ARM: dts: at91: sama5d2_icp: specify proper regulator output ranges Date: Fri, 26 Aug 2022 11:39:23 +0300 Message-ID: <20220826083927.3107272-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Min and max output ranges of regulators need to satisfy board requirements not PMIC requirements. Thus adjust device tree to cope with this. Fixes: 68a95ef72cef ("ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP") Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama5d2_icp.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at9= 1-sama5d2_icp.dts index 6865be8d7787..6296e3ffd303 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -196,8 +196,8 @@ mcp16502@5b { regulators { vdd_io_reg: VDD_IO { regulator-name =3D "VDD_IO"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <3700000>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -215,8 +215,8 @@ regulator-state-mem { =20 VDD_DDR { regulator-name =3D "VDD_DDR"; - regulator-min-microvolt =3D <600000>; - regulator-max-microvolt =3D <1850000>; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -234,8 +234,8 @@ regulator-state-mem { =20 VDD_CORE { regulator-name =3D "VDD_CORE"; - regulator-min-microvolt =3D <600000>; - regulator-max-microvolt =3D <1850000>; + regulator-min-microvolt =3D <1250000>; + regulator-max-microvolt =3D <1250000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -272,8 +272,8 @@ regulator-state-mem { =20 LDO1 { regulator-name =3D "LDO1"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <3700000>; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; regulator-always-on; =20 regulator-state-standby { @@ -287,8 +287,8 @@ regulator-state-mem { =20 LDO2 { regulator-name =3D "LDO2"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <3700000>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; regulator-always-on; =20 regulator-state-standby { --=20 2.34.1 From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3FADECAAA3 for ; Fri, 26 Aug 2022 08:37:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343715AbiHZIhs (ORCPT ); Fri, 26 Aug 2022 04:37:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245512AbiHZIhg (ORCPT ); Fri, 26 Aug 2022 04:37:36 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 020B2A027F; Fri, 26 Aug 2022 01:37:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661503045; x=1693039045; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6WB5xv8fShPUTYldpC0cO1DPSAbcvBwlaP8AS0LK/Y8=; b=Q7GsPAA4yRSGaq2Hn4plk+gmAv7oCUdYEr3WxvQl+CMfWx0Y0NJTumdt R5ek8shQ3WkevCA+R3f/wHZ0+LLQ/mEEotBql6F/FWikJfOkfvtZ6rYPn QXNTAUP+JdJv40t18q8pXwdLBhBIL2femK0WqVB7n44dLf/ipM3JP17L7 emDEYM79yWsMtnH6JuTbreH9YvQIDAIJTLdT2MoSA3YZtAn2wZzyh95C+ F8rr6icICV1SNmsSomj6tBwfQOn74d/Kk6+SeojsRSGuRwYDA+zTm1jwJ KehLwCJf8sCOn82LUAzpkyNmkRvpOQTrMcLrQf1uzhzJ73ubCIcJiHH4j w==; X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="188164706" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:24 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:24 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:22 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 6/9] ARM: dts: at91: sama7g5ek: specify proper regulator output ranges Date: Fri, 26 Aug 2022 11:39:24 +0300 Message-ID: <20220826083927.3107272-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Min and max output ranges of regulators need to satisfy board requirements not PMIC requirements. Thus adjust device tree to cope with this. Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama7g5ek.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-= sama7g5ek.dts index de44da2e4aae..3b25c67795dd 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -244,8 +244,8 @@ mcp16502@5b { regulators { vdd_3v3: VDD_IO { regulator-name =3D "VDD_IO"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <3700000>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -264,8 +264,8 @@ regulator-state-mem { =20 vddioddr: VDD_DDR { regulator-name =3D "VDD_DDR"; - regulator-min-microvolt =3D <1300000>; - regulator-max-microvolt =3D <1450000>; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -285,8 +285,8 @@ regulator-state-mem { =20 vddcore: VDD_CORE { regulator-name =3D "VDD_CORE"; - regulator-min-microvolt =3D <1100000>; - regulator-max-microvolt =3D <1850000>; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-always-on; @@ -306,7 +306,7 @@ regulator-state-mem { vddcpu: VDD_OTHER { regulator-name =3D "VDD_OTHER"; regulator-min-microvolt =3D <1050000>; - regulator-max-microvolt =3D <1850000>; + regulator-max-microvolt =3D <1250000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; regulator-ramp-delay =3D <3125>; @@ -326,8 +326,8 @@ regulator-state-mem { =20 vldo1: LDO1 { regulator-name =3D "LDO1"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <3700000>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; regulator-always-on; =20 regulator-state-standby { --=20 2.34.1 From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0005BECAAA3 for ; Fri, 26 Aug 2022 08:38:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343743AbiHZIh5 (ORCPT ); Fri, 26 Aug 2022 04:37:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343516AbiHZIhh (ORCPT ); Fri, 26 Aug 2022 04:37:37 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 770D8D570B; Fri, 26 Aug 2022 01:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661503048; x=1693039048; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v4zsensQQvholXim790vjmpC9/l/eE/p7Tv+g5+KkXg=; b=WNwwA196fP1+tSlJ/W+Nl1XjeLs1dxq2S+PRFdKXo+bWzlYxQPeIwLBr XUh9ynFy8VXHUWZFxfHqnh4Ke8pZQngt30c+z+LFT00Gau/FBUnas6/FG DTJDRmHaS5GKi6Oz5G9MQYcb8UCWYNe/pw/9rz8ZLA5WbhZr4kmSdi06B JuBvq4+rNTc8LQBoeQVhXLk+nlhS3RY+7luMI0lkMNDC4souFJEUfJY1h r3dChjvZwMCBaFpoKT8TugSKgO1tWpfgE2Y0NFGm3LG4R107EalWTCtMX M5uOxV6t2iNNuYW2VNL7qAEXpdPzea2bL6w1Ko+iMp5JNuCJQ80COoATE A==; X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="188164712" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:27 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:27 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:25 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 7/9] ARM: dts: at91: sama5d27_wlsom1: don't keep ldo2 enabled all the time Date: Fri, 26 Aug 2022 11:39:25 +0300 Message-ID: <20220826083927.3107272-8-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ldo2 is not used by any consumer on sama5d27_wlsom1 board, thus don't keep it enabled all the time. Fixes: 5d4c3cfb63fe ("ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 = and wlsom1-ek") Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dt= s/at91-sama5d27_wlsom1.dtsi index 342fcfd974d7..83bcf9fe0152 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -177,7 +177,6 @@ LDO2 { regulator-name =3D "LDO2"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <3300000>; - regulator-always-on; =20 regulator-state-standby { regulator-on-in-suspend; --=20 2.34.1 From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5828AECAAD2 for ; Fri, 26 Aug 2022 08:38:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245110AbiHZIiD (ORCPT ); Fri, 26 Aug 2022 04:38:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245610AbiHZIhj (ORCPT ); Fri, 26 Aug 2022 04:37:39 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07866D571B; Fri, 26 Aug 2022 01:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661503052; x=1693039052; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NhTYybz8cFKXvPDczCL3sDgZh+OWnjOmY+XsBCIQazs=; b=dz3bGmMHvCzh1UO4U+PzOThni5f13jYBdJ6lKoFJXvldCk91T3vhjrw+ cqZ3jlx5/LC3NXqU7F9ui2m3sbnLjoTf4qLEyfiYnEGR5S4er3HTyw005 SL+7gGU+esV2TbVOndsPcPOvpXXU1XHniBoUx8YoAlSlAHmklFywSBoyZ UDoYn73TWLSkk3fzHo3Gd74k83tLyIsEPpPa453gwe4h4tDCtJaTBuXFk h7tBN8t9JBuSZjWhaChZzDRGw0VZWnDEOMd7cgkBrZeDWWqckK416vWq2 GQALTCfS4aLl5uFQUpzhzYng7blFm5ryWSP26pN9J6zsvcqo4tx4X7ld/ w==; X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="188164732" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:32 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:30 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:27 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 8/9] ARM: dts: at91: sama5d2_icp: don't keep vdd_other enabled all the time Date: Fri, 26 Aug 2022 11:39:26 +0300 Message-ID: <20220826083927.3107272-9-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" VDD_OTHER is not connected to any on board consumer thus it is not needed to keep it enabled all the time. Fixes: 68a95ef72cef ("ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP") Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama5d2_icp.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at9= 1-sama5d2_icp.dts index 6296e3ffd303..dd1dec9d4e07 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -257,7 +257,6 @@ VDD_OTHER { regulator-max-microvolt =3D <1850000>; regulator-initial-mode =3D <2>; regulator-allowed-modes =3D <2>, <4>; - regulator-always-on; =20 regulator-state-standby { regulator-on-in-suspend; --=20 2.34.1 From nobody Tue Apr 7 16:32:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB72FECAAD2 for ; Fri, 26 Aug 2022 08:38:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343754AbiHZIiH (ORCPT ); Fri, 26 Aug 2022 04:38:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241853AbiHZIhl (ORCPT ); Fri, 26 Aug 2022 04:37:41 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25AD7D2E8A; Fri, 26 Aug 2022 01:37:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661503056; x=1693039056; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v/GMC8+uXpbJ05sehOG56CNutF0wXIfUIa6mE5Vt65Y=; b=Q6MxTT9EmDA6Bywn7OyxNvawqbqjVTh15P430xTCtHO2N1Ok3GhPaD84 zp2vK58zOkjB6lQtPiatcpfqc4VX8IsNwfyZ+TL1ULdsWNI+T9ZIplfob IbYKUeo+lgdOa42EhCsdIApGOKeMuGKkp6OIrhT4vQ923DClnwvF019aK GIUDr73okpnBRPKkF5tLqWyMnUrhBpyopzeTId4X4OOF3juKC0EPavrl5 wNhN0TCGRqX0QdHpzEtIumjUkDX6jUCxJ0Vm0tw5nB/mAg4H35Jv8BE1K fuBrYVn/Q5jt52JRS2eBQK5wAb9F5J55Dro+ZmC+RFZ0V8kBrAPvqKIP5 w==; X-IronPort-AV: E=Sophos;i="5.93,264,1654585200"; d="scan'208";a="188164749" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Aug 2022 01:37:35 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 26 Aug 2022 01:37:33 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 26 Aug 2022 01:37:30 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Subject: [PATCH 9/9] ARM: dts: at91: sam9x60ek: remove simple-bus for regulators Date: Fri, 26 Aug 2022 11:39:27 +0300 Message-ID: <20220826083927.3107272-10-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220826083927.3107272-1-claudiu.beznea@microchip.com> References: <20220826083927.3107272-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Keep regulators as individual devices. There is no need to have them under simple bus. This will throw compilation warnings like: - unnecessary #address-cells/#size-cells without "ranges" or child "reg" property. - node has a unit name, but no reg or ranges property. While at it move it down a bit in the file to keep entries sorted alphabetically. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sam9x60ek.dts | 78 +++++++++++++--------------- 1 file changed, 36 insertions(+), 42 deletions(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-= sam9x60ek.dts index 81c38e101f58..7ade9979e1c6 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -34,48 +34,6 @@ main_xtal { }; }; =20 - regulators: regulators { - compatible =3D "simple-bus"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - vdd_1v8: fixed-regulator-vdd_1v8@0 { - compatible =3D "regulator-fixed"; - regulator-name =3D "VDD_1V8"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-always-on; - status =3D "okay"; - }; - - vdd_1v15: fixed-regulator-vdd_1v15@1 { - compatible =3D "regulator-fixed"; - regulator-name =3D "VDD_1V15"; - regulator-min-microvolt =3D <1150000>; - regulator-max-microvolt =3D <1150000>; - regulator-always-on; - status =3D "okay"; - }; - - vdd1_3v3: fixed-regulator-vdd1_3v3@2 { - compatible =3D "regulator-fixed"; - regulator-name =3D "VDD1_3V3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - status =3D "okay"; - }; - - vdd2_3v3: regulator-fixed-vdd2_3v3@3 { - compatible =3D "regulator-fixed"; - regulator-name =3D "VDD2_3V3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - status =3D "okay"; - }; - }; - gpio-keys { compatible =3D "gpio-keys"; pinctrl-names =3D "default"; @@ -111,6 +69,42 @@ blue { linux,default-trigger =3D "heartbeat"; }; }; + + vdd_1v8: fixed-regulator-vdd_1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + status =3D "okay"; + }; + + vdd_1v15: fixed-regulator-vdd_1v15 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_1V15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + regulator-always-on; + status =3D "okay"; + }; + + vdd1_3v3: fixed-regulator-vdd1_3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD1_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + status =3D "okay"; + }; + + vdd2_3v3: regulator-fixed-vdd2_3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD2_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + status =3D "okay"; + }; }; =20 &adc { --=20 2.34.1