From nobody Sat Apr 11 15:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F21D7ECAAA2 for ; Thu, 25 Aug 2022 23:54:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244430AbiHYXyU (ORCPT ); Thu, 25 Aug 2022 19:54:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244200AbiHYXyM (ORCPT ); Thu, 25 Aug 2022 19:54:12 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 865CAC59E0 for ; Thu, 25 Aug 2022 16:54:11 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id m34-20020a634c62000000b0042aff6dff12so4058253pgl.14 for ; Thu, 25 Aug 2022 16:54:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc; bh=tygyO2PFYuXfHZyst5i+EgaagTYAQzq4it8NYXlV8yE=; b=TNTdH/vcnr1azAqTc4UnDItuLwArV7U663pOgFTWZP1TEkiNOgBKF7Q+Tm4j0k4YP7 8uCEE4BgoJLlFI8w/NmSq0urroZG6wu/Kqo3JqkMx+P00IDv3LaImwz4qAWrF/gqFlfu hCL/0qEC4fX1EQmoeLpToGHMsf/8OFOl2pKwh8A9TYltlhYewqws6me8Pk/iYAdbTDmL DbkelJ6Ct7+LDeTIVUF2YG2W92/av3TI0nU6EMDFYCNvliIw3sZd3S4mVZf3Ea1wrgXw 2CiXvblz2DHKOQ6NACcQnHtXPvx+dyYQrbJpbggdTfgnAT9csSNR0jh0FLQYmRhc8Han 9OPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc; bh=tygyO2PFYuXfHZyst5i+EgaagTYAQzq4it8NYXlV8yE=; b=UjS+fAQHcJd13hdRgt55bY53P3XJ9jfWfA7T+MrNC0hYpo1YC/BgxI5Zzv2EOfnsL+ 6w0hvJJPlBFOQ4bn9YOa8PsaxHuDjDsrWGRxfXPsT/X1Km0pynOWR9HZLBTJAW2WlKtI OTfdUt/ueyUY1vZbqE1n9XEVL6dPv9Pcfz2vUEAZ6JzKNIhY+ndIfx/JSCc/erwU4OdE wT9MdNT+JT116Rz+8YsFHE8JSilL+nCwaNamjnzq30ytvMck9fX1UB+x8Q87b8Lk3UMS /keO9HAgGXSez3UKuYiMGLq0+sR2q7ov/quA5o7xCxTjSD5E0LtXNjUrk4BX+yhnzDmh yaeg== X-Gm-Message-State: ACgBeo1fkuvqHsss7uZF61zBcp2MWWvo0Hc5JRZ36enF4VQLafGJJCv0 nw1iH2LqEamq4afLdNvpvHdIVgryyFKesSWXUDM= X-Google-Smtp-Source: AA6agR66Ef/rjMhqWVcBhDQTJkwW+HndjqAueSvfGx9h6HPfdBzfubtsbOn8V5UByZqJQSoZJYyfQxRKjDaajpJ5zNw= X-Received: from wmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5ebe]) (user=willmcvicker job=sendgmr) by 2002:a17:90a:e558:b0:1fb:c4b7:1a24 with SMTP id ei24-20020a17090ae55800b001fbc4b71a24mr84011pjb.1.1661471650555; Thu, 25 Aug 2022 16:54:10 -0700 (PDT) Date: Thu, 25 Aug 2022 23:54:02 +0000 In-Reply-To: <20220825235404.4132818-1-willmcvicker@google.com> Mime-Version: 1.0 References: <20220825235404.4132818-1-willmcvicker@google.com> X-Mailer: git-send-email 2.37.2.672.g94769d06f0-goog Message-ID: <20220825235404.4132818-2-willmcvicker@google.com> Subject: [PATCH v6 1/2] PCI: dwc: Drop dependency on ZONE_DMA32 From: Will McVicker To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Rob Herring , "=?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?=" , Bjorn Helgaas , Will McVicker Cc: kernel-team@android.com, Vidya Sagar , Christoph Hellwig , Robin Murphy , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, "Isaac J . Manjarres" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Re-work the msi_msg DMA allocation logic to use dmam_alloc_coherent() which uses the coherent DMA mask to try to return an allocation within the DMA mask limits. With that, we now can drop the msi_page parameter in struct dw_pcie_rp. This allows kernel configurations that disable ZONE_DMA32 to continue supporting a 32-bit DMA mask. Without this patch, the PCIe host device will fail to probe when ZONE_DMA32 is disabled. Fixes: 35797e672ff0 ("PCI: dwc: Fix MSI msi_msg DMA mapping") Reported-by: Isaac J. Manjarres Signed-off-by: Will McVicker Acked-by: Jingoo Han Reviewed-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 28 +++++-------------- drivers/pci/controller/dwc/pcie-designware.h | 1 - 2 files changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 7746f94a715f..39f3b37d4033 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -267,15 +267,6 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp) =20 irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); - - if (pp->msi_data) { - struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - struct device *dev =3D pci->dev; - - dma_unmap_page(dev, pp->msi_data, PAGE_SIZE, DMA_FROM_DEVICE); - if (pp->msi_page) - __free_page(pp->msi_page); - } } =20 static void dw_pcie_msi_init(struct dw_pcie_rp *pp) @@ -336,6 +327,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct device *dev =3D pci->dev; struct platform_device *pdev =3D to_platform_device(dev); + u64 *msi_vaddr; int ret; u32 ctrl, num_ctrls; =20 @@ -375,22 +367,16 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *p= p) dw_chained_msi_isr, pp); } =20 - ret =3D dma_set_mask(dev, DMA_BIT_MASK(32)); + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bi= t MSI support may not work properly\n"); =20 - pp->msi_page =3D alloc_page(GFP_DMA32); - pp->msi_data =3D dma_map_page(dev, pp->msi_page, 0, - PAGE_SIZE, DMA_FROM_DEVICE); - ret =3D dma_mapping_error(dev, pp->msi_data); - if (ret) { - dev_err(pci->dev, "Failed to map MSI data\n"); - __free_page(pp->msi_page); - pp->msi_page =3D NULL; - pp->msi_data =3D 0; + msi_vaddr =3D dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, + GFP_KERNEL); + if (!msi_vaddr) { + dev_err(dev, "Failed to alloc and map MSI data\n"); dw_pcie_free_msi(pp); - - return ret; + return -ENOMEM; } =20 return 0; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 09b887093a84..a871ae7eb59e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -243,7 +243,6 @@ struct dw_pcie_rp { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; - struct page *msi_page; struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS]; --=20 2.37.2.672.g94769d06f0-goog From nobody Sat Apr 11 15:26:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33D69ECAAA2 for ; Thu, 25 Aug 2022 23:54:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233894AbiHYXyb (ORCPT ); Thu, 25 Aug 2022 19:54:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244298AbiHYXyR (ORCPT ); Thu, 25 Aug 2022 19:54:17 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4CEBC59EC for ; Thu, 25 Aug 2022 16:54:14 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-33d9f6f4656so122013817b3.21 for ; Thu, 25 Aug 2022 16:54:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc; bh=vUz6Nust5yp1gNz4Uf4QGDc0k3EwgdmOYN4sE8meqr8=; b=CtiHcgKrviWMX2NGBRZS+VHzmzJeYi1IOF/PRhdjReTqmrqfKTalpa5giNXz57jOEs BDpLTR6o9NZ4FLZfd4EiKm9qk5MAnCkrolAfSryscZe0QkOuJ+IO72uNA1441vmtHXL5 Sla99irAya3PYuJ+MGxhQHK9Yh/DX9VN0DteGBje8rNSsy8d+pRB9LkYisJz6jG57ZE1 cUg/N4mgDmaB18+oLKTAHr3Zk6MVQhsFS5z+Vfkbsc9LAKkqom45Zg1fLgA5C8nbPTa3 Y+FOrtNZPkArsS84DRE8y3jUIJabboBOUyRavyx7VBcPqHNwYINKq+fPmDMQcW7jwC/l W/Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc; bh=vUz6Nust5yp1gNz4Uf4QGDc0k3EwgdmOYN4sE8meqr8=; b=qgZAvru5ieSqY9uIpqCvl9l/+s58IWRXu1ZmxS9mL4mTTTIfcmlohqjx2H+QRDsITD S9ymH4Tw9rt+KpsxZsGzwgVSod3468Ur1kO70gZaUfxaKpDWFS4U2bRbMvIB+ZVvvGSM AIOmyJg4pdGRHKw1HCW5/KUpfDsUUPd0Ctder3xmUhLX19sNmd8FYA5ffVUsfyQ8qYtG RI76deirkikrcB2rNPMk5gcDN64Aoa4Izes/S3RFfAMlkfGUJ27Ca0k65fif2FT17ppy VNXf/G5OmdvqgvS2HrdRXlqPcXN0NP6Lgs3irP8ymBA6eCwNmN/+WplxyBYioiXhmbpW EGTA== X-Gm-Message-State: ACgBeo05eoMoFxKtqV0q1uF1NO4NG9Xf1AuI9MxB5A71UOX4EvrlrEKR OeOejHjXKFB1HvrxvrJjQL4+Iz5oy/Q07mNA+P0= X-Google-Smtp-Source: AA6agR7iHLfntJEAqSMbg5WG2yYoh67fS0C1ycJi2Z3X+HvBvRFPJ3qx35cuYPmJAraW943ihfv/i4z791j6aUS2tTk= X-Received: from wmcvicker.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5ebe]) (user=willmcvicker job=sendgmr) by 2002:a0d:cad1:0:b0:335:8273:e9fd with SMTP id m200-20020a0dcad1000000b003358273e9fdmr6347676ywd.154.1661471654046; Thu, 25 Aug 2022 16:54:14 -0700 (PDT) Date: Thu, 25 Aug 2022 23:54:03 +0000 In-Reply-To: <20220825235404.4132818-1-willmcvicker@google.com> Mime-Version: 1.0 References: <20220825235404.4132818-1-willmcvicker@google.com> X-Mailer: git-send-email 2.37.2.672.g94769d06f0-goog Message-ID: <20220825235404.4132818-3-willmcvicker@google.com> Subject: [PATCH v6 2/2] PCI: dwc: Add support for 64-bit MSI target address From: Will McVicker To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Rob Herring , "=?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?=" , Bjorn Helgaas , Will McVicker Cc: kernel-team@android.com, Vidya Sagar , Christoph Hellwig , Robin Murphy , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since not all devices require a 32-bit MSI address, add support to the PCIe host driver to allow setting the DMA mask to 64-bits if the 32-bit allocation fails. This allows kernels to disable ZONE_DMA32 and bounce buffering (swiotlb) without risking not being able to get a 32-bit address during DMA allocation. Basically, in the slim chance that there are no 32-bit allocations available, the current PCIe host driver will fail to allocate the msi_msg page due to a DMA address overflow (seen in [1]). With this patch, the PCIe host can retry the allocation with a 64-bit DMA mask if the current PCIe device advertises 64-bit support via its MSI capabilities. [1] https://lore.kernel.org/all/Yo0soniFborDl7+C@google.com/ Reported-by: kernel test robot Signed-off-by: Will McVicker Reviewed-by: Rob Herring Acked-by: Jingoo Han --- .../pci/controller/dwc/pcie-designware-host.c | 19 ++++++++++++++++--- drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 39f3b37d4033..7e0352861bcb 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -374,9 +374,22 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) msi_vaddr =3D dmam_alloc_coherent(dev, sizeof(u64), &pp->msi_data, GFP_KERNEL); if (!msi_vaddr) { - dev_err(dev, "Failed to alloc and map MSI data\n"); - dw_pcie_free_msi(pp); - return -ENOMEM; + u16 msi_capabilities; + + /* Retry the allocation with a 64-bit mask if supported. */ + msi_capabilities =3D dw_pcie_msi_capabilities(pci); + if ((msi_capabilities & PCI_MSI_FLAGS_ENABLE) && + (msi_capabilities & PCI_MSI_FLAGS_64BIT)) { + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + msi_vaddr =3D dmam_alloc_coherent(dev, sizeof(u64), + &pp->msi_data, + GFP_KERNEL); + } + if (!msi_vaddr) { + dev_err(dev, "Failed to alloc and map MSI data\n"); + dw_pcie_free_msi(pp); + return -ENOMEM; + } } =20 return 0; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c6725c519a47..650a7f22f9d0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -82,6 +82,14 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); =20 +u16 dw_pcie_msi_capabilities(struct dw_pcie *pci) +{ + u8 offset; + + offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); + return dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); +} + static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, u8 cap) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index a871ae7eb59e..45fcdfc8c035 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -332,6 +332,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); =20 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +u16 dw_pcie_msi_capabilities(struct dw_pcie *pci); =20 int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); --=20 2.37.2.672.g94769d06f0-goog