From nobody Sat Sep 21 15:31:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40A6AC04AA5 for ; Thu, 25 Aug 2022 08:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238769AbiHYIYA (ORCPT ); Thu, 25 Aug 2022 04:24:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238831AbiHYIXu (ORCPT ); Thu, 25 Aug 2022 04:23:50 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19019A572E; Thu, 25 Aug 2022 01:23:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661415798; cv=none; d=zohomail.com; s=zohoarc; b=Q4NsZdlp0PPYf6Y5oln8AWAGrH4eDRWjF6zy5nyNF0fjs9NSJuis1L6v6fRIOSEP/YXywkIPZdfLzlOZceKJllAjB5ccyg0Ig3n+gqQqXtlbq9CboP4R5vyCKbPonvvcoIM0U025Jmv2Es5CinAFzSvgpW0QZoOy4hb73pKD2Uo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661415798; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=WgdOW7ryOZz5p4feBiY6z2PhhWL00d5o0elsMpsRC4I=; b=SUprM0ZIgWGOdXEqhk0Pdk/qYMFMauCZ5JEc0b0ms1djj4CuoNZ00Ag8UmluxN/E57z+j/TpFB7BjeSeWyopPk3ir09Yio0CP1fWmuJBht+XomaQTkBuk7Pfqv+KqI7fRNIdYHYnp/0e1gVZJYfwcIsAHlRXExLLdc4wZKowxXQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1661415798; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=WgdOW7ryOZz5p4feBiY6z2PhhWL00d5o0elsMpsRC4I=; b=goSE6zIhEp9Ejgy8m4bYMvZ3/vrnuDZcccwDRjn6RLJeTQ1WQTHOHatHAK04TpoN vWWgKNnRa6NPQ1S3AdpZFnpaVohATOGqD81Ro2LZAmMjB0DF2guheTWzR45HtPt3Ldw f3CeAooirAOucrh7jNcSwymNbsDbtJpvf3hJUTUY= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1661415796720114.84929287702482; Thu, 25 Aug 2022 01:23:16 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Subject: [PATCH v6 1/6] dt-bindings: net: dsa: mediatek,mt7530: make trivial changes Date: Thu, 25 Aug 2022 11:22:56 +0300 Message-Id: <20220825082301.409450-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825082301.409450-1-arinc.unal@arinc9.com> References: <20220825082301.409450-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make trivial changes on the binding. - Update title to include MT7531 switch. - Add me as a maintainer. List maintainers in alphabetical order by first name. - Add description to compatible strings. - Stretch descriptions up to the 80 character limit. - Remove lists for single items. - Remove requiring reg as it's already required by dsa-port.yaml. - Define acceptable reg values for the CPU ports. - Remove quotes from $ref: "dsa.yaml#". Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/net/dsa/mediatek,mt7530.yaml | 50 ++++++++++++------- 1 file changed, 31 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 17ab6c69ecc7..c1dc712706c4 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -4,12 +4,13 @@ $id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT7530 Ethernet switch +title: Mediatek MT7530 and MT7531 Ethernet Switches =20 maintainers: - - Sean Wang + - Ar=C4=B1n=C3=A7 =C3=9CNAL - Landen Chao - DENG Qingfang + - Sean Wang =20 description: | Port 5 of mt7530 and mt7621 switch is muxed between: @@ -61,10 +62,18 @@ description: | =20 properties: compatible: - enum: - - mediatek,mt7530 - - mediatek,mt7531 - - mediatek,mt7621 + oneOf: + - description: + Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC + const: mediatek,mt7530 + + - description: + Standalone MT7531 + const: mediatek,mt7531 + + - description: + Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + const: mediatek,mt7621 =20 reg: maxItems: 1 @@ -79,7 +88,7 @@ properties: gpio-controller: type: boolean description: - if defined, MT7530's LED controller will run on GPIO mode. + If defined, MT7530's LED controller will run on GPIO mode. =20 "#interrupt-cells": const: 1 @@ -92,8 +101,8 @@ properties: io-supply: description: Phandle to the regulator node necessary for the I/O power. - See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt - for details for the regulator setup on these boards. + See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt= for + details for the regulator setup on these boards. =20 mediatek,mcm: type: boolean @@ -110,8 +119,8 @@ properties: =20 resets: description: - Phandle pointing to the system reset controller with line index for - the ethsys. + Phandle pointing to the system reset controller with line index for = the + ethsys. maxItems: 1 =20 patternProperties: @@ -128,27 +137,31 @@ patternProperties: properties: reg: description: - Port address described must be 5 or 6 for CPU port and from 0 - to 5 for user ports. + Port address described must be 5 or 6 for CPU port and from = 0 to 5 + for user ports. =20 allOf: - $ref: dsa-port.yaml# - if: properties: label: - items: - - const: cpu + const: cpu then: required: - - reg - phy-mode =20 + properties: + reg: + enum: + - 5 + - 6 + required: - compatible - reg =20 allOf: - - $ref: "dsa.yaml#" + - $ref: dsa.yaml# - if: required: - mediatek,mcm @@ -163,8 +176,7 @@ allOf: - if: properties: compatible: - items: - - const: mediatek,mt7530 + const: mediatek,mt7530 then: required: - core-supply --=20 2.34.1 From nobody Sat Sep 21 15:31:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61873C28D13 for ; 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Thu, 25 Aug 2022 01:23:23 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Krzysztof Kozlowski Subject: [PATCH v6 2/6] dt-bindings: net: dsa: mediatek,mt7530: fix description of mediatek,mcm Date: Thu, 25 Aug 2022 11:22:57 +0300 Message-Id: <20220825082301.409450-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825082301.409450-1-arinc.unal@arinc9.com> References: <20220825082301.409450-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix the description of mediatek,mcm. mediatek,mcm is not used on MT7623NI. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index c1dc712706c4..35a3039825bd 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -107,9 +107,8 @@ properties: mediatek,mcm: type: boolean description: - if defined, indicates that either MT7530 is the part on multi-chip - module belong to MT7623A has or the remotely standalone chip as the - function MT7623N reference board provided for. + Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the M= T7530 + switch is a part of the multi-chip module. =20 reset-gpios: maxItems: 1 --=20 2.34.1 From nobody Sat Sep 21 15:31:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A123FC04AA5 for ; Thu, 25 Aug 2022 08:24:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240015AbiHYIY0 (ORCPT ); Thu, 25 Aug 2022 04:24:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239835AbiHYIYM (ORCPT ); Thu, 25 Aug 2022 04:24:12 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC8D5A61D5; Thu, 25 Aug 2022 01:24:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661415812; cv=none; d=zohomail.com; s=zohoarc; b=MtJ7qO+Xey0OqUrFcFlQLD/MFV94IDDljpcDonYCDi+xJR7JLP3ZGbJn4HSz1sR09qYKtRUP9jrqtc3z6EpUFGHDG0WRGHgNXkxV1vUT80x5dwmy5rls0dBLAiq5K4cHEZDD1sEGSGzdGqAtjjq8POkFrARtIJTs1I+5YIFY9e8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661415812; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=I5bq6j8LEU8gFq5ov2kLQDkOrcDe7wXqTnM+mc70qTY=; b=n/Kug+OgPMP+2t7a82U9d0RXGa2v8GMcARaf3Mxa2+VuZ/eBWQvX7rXEAlLDaymfdn7d0iqlYjP9LAxa90RJmLWxm82DaOcDCUE504DAaE3xTAJI+a12Qn6LYqFPlXtCui3HA7zKb/LsPcYvWE6nKKDx+SWvBCQGTcFUvtVEfi4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1661415812; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=I5bq6j8LEU8gFq5ov2kLQDkOrcDe7wXqTnM+mc70qTY=; b=A34toTrjpjQZRer5OVay2c+cscs6M5rMuNr1niupaMk5klthplykFKgvtBiqEeEz zCDHdPYiYTS5uPif+2znv9Kc2ACXWGUW9VAJSeTKJO60FsM8R++POhlg0OwveZbMaL7 tSi/lBE7XISI4zroArUjcqLgQoLDK+PpMZFwquPw= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1661415810501649.5584786900944; Thu, 25 Aug 2022 01:23:30 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Krzysztof Kozlowski Subject: [PATCH v6 3/6] dt-bindings: net: dsa: mediatek,mt7530: fix reset lines Date: Thu, 25 Aug 2022 11:22:58 +0300 Message-Id: <20220825082301.409450-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825082301.409450-1-arinc.unal@arinc9.com> References: <20220825082301.409450-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Add description for reset-gpios. - Invalidate reset-gpios if mediatek,mcm is used. We cannot use multiple reset lines at the same time. - Invalidate mediatek,mcm if the compatible device is mediatek,mt7531. There is no multi-chip module version of mediatek,mt7531. - Require mediatek,mcm for mediatek,mt7621 as the compatible string is only used for the multi-chip module version of MT7530. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/dsa/mediatek,mt7530.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 35a3039825bd..16ddda314b5c 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -111,6 +111,11 @@ properties: switch is a part of the multi-chip module. =20 reset-gpios: + description: + GPIO to reset the switch. Use this if mediatek,mcm is not used. + This property is optional because some boards share the reset line w= ith + other components which makes it impossible to probe the switch if the + reset line is used. maxItems: 1 =20 reset-names: @@ -165,6 +170,9 @@ allOf: required: - mediatek,mcm then: + properties: + reset-gpios: false + required: - resets - reset-names @@ -181,6 +189,22 @@ allOf: - core-supply - io-supply =20 + - if: + properties: + compatible: + const: mediatek,mt7531 + then: + properties: + mediatek,mcm: false + + - if: + properties: + compatible: + const: mediatek,mt7621 + then: + required: + - mediatek,mcm + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Sat Sep 21 15:31:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37D14C32774 for ; Thu, 25 Aug 2022 08:24:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238939AbiHYIYu (ORCPT ); Thu, 25 Aug 2022 04:24:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239817AbiHYIYX (ORCPT ); Thu, 25 Aug 2022 04:24:23 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03B9FA59B3; Thu, 25 Aug 2022 01:24:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661415820; cv=none; d=zohomail.com; s=zohoarc; b=Mb/fkCxenUAqdFk+tmcu52nRqx3BIfj9SR/US9kyR2wMlHRiZNFODEGzUT52O8qRU9Zt79xl9HjYeQAV0bm1M+E+UaPD6G5qmL+CWU5IMUFBkXpao1kh+KGZdWvbpAYX1867FLBqvvVGLkKozNX4LSW+rlK3fpnEXr76DGWgMFo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661415820; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=NDsnxls+oOuuu0L1onGF6H3pSNX7sZLktEqGSNXnztI=; b=l5EQGz4hynONuk1XgnpnElLH06Yd4+1aZ2aU64Q/t1RnpcybO3mprSJY0wRXed+OjX4IKf+us+9PWPJkdKDhDlPa4p+vhHeYMREStWrrh0dwdFdxK5Aug5lVg7G8dJoPgJ0GPPjbYoVGmMRa+hm9A05+vt97pk3pG2Btxohg3L8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1661415820; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=NDsnxls+oOuuu0L1onGF6H3pSNX7sZLktEqGSNXnztI=; b=grzOVlq88Am3+tSnOQ+7KmqdzqjYcymWLb8SywM7qnAz2fBhByGGGb+uRMOGPhMv J48ZstOxpCklmMGvZmqjcyngeMHibLN/hYvFb0gRma9aKLPkMsPT4dCOUeFfv+2pjNv VHgM30Joc2uhPZ8SOtxMeqaMKdNuyVPzq2PqCB88= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 166141581766988.72998549995748; Thu, 25 Aug 2022 01:23:37 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Krzysztof Kozlowski Subject: [PATCH v6 4/6] dt-bindings: net: dsa: mediatek,mt7530: update examples Date: Thu, 25 Aug 2022 11:22:59 +0300 Message-Id: <20220825082301.409450-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825082301.409450-1-arinc.unal@arinc9.com> References: <20220825082301.409450-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the examples on the binding. - Add examples which include a wide variation of configurations. - Make example comments YAML comment instead of DT binding comment. - Add interrupt controller to the examples. Include header file for interrupt. - Change reset line for MT7621 examples. - Pretty formatting for the examples. - Change switch reg to 0. - Change port labels to fit the example, change port 4 label to wan. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/dsa/mediatek,mt7530.yaml | 402 +++++++++++++++--- 1 file changed, 347 insertions(+), 55 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 16ddda314b5c..e81b3dce874b 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -208,42 +208,111 @@ allOf: unevaluatedProperties: false =20 examples: + # Example 1: Standalone MT7530 - | #include + mdio { #address-cells =3D <1>; #size-cells =3D <0>; + switch@0 { compatible =3D "mediatek,mt7530"; reg =3D <0>; =20 + reset-gpios =3D <&pio 33 0>; + core-supply =3D <&mt6323_vpa_reg>; io-supply =3D <&mt6323_vemc3v3_reg>; - reset-gpios =3D <&pio 33 GPIO_ACTIVE_HIGH>; =20 ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; + port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "rgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 2: MT7530 in MT7623AI SoC + - | + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch@0 { + compatible =3D "mediatek,mt7530"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names =3D "mcm"; + + core-supply =3D <&mt6323_vpa_reg>; + io-supply =3D <&mt6323_vemc3v3_reg>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; label =3D "lan3"; }; =20 + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + port@4 { reg =3D <4>; label =3D "wan"; @@ -254,85 +323,219 @@ examples: label =3D "cpu"; ethernet =3D <&gmac0>; phy-mode =3D "trgmii"; + fixed-link { speed =3D <1000>; full-duplex; + pause; }; }; }; }; }; =20 + # Example 3: Standalone MT7531 - | - //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY por= t 4. + #include + #include =20 - ethernet { + mdio { #address-cells =3D <1>; #size-cells =3D <0>; - gmac0: mac@0 { - compatible =3D "mediatek,eth-mac"; + + switch@0 { + compatible =3D "mediatek,mt7531"; reg =3D <0>; - phy-mode =3D "rgmii"; =20 - fixed-link { - speed =3D <1000>; - full-duplex; - pause; + reset-gpios =3D <&pio 54 0>; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <53 IRQ_TYPE_LEVEL_HIGH>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "2500base-x"; + + fixed-link { + speed =3D <2500>; + full-duplex; + pause; + }; + }; }; }; + }; + + # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + - | + #include + #include =20 - gmac1: mac@1 { + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + switch@0 { + compatible =3D "mediatek,mt7621"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; + reset-names =3D "mcm"; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; + + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 + - | + #include + #include + + ethernet { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mac@1 { compatible =3D "mediatek,eth-mac"; reg =3D <1>; - phy-mode =3D "rgmii-txid"; - phy-handle =3D <&phy4>; + + phy-mode =3D "rgmii"; + phy-handle =3D <&example5_ethphy4>; }; =20 - mdio: mdio-bus { + mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - /* Internal phy */ - phy4: ethernet-phy@4 { + /* MT7530's phy4 */ + example5_ethphy4: ethernet-phy@4 { reg =3D <4>; }; =20 - mt7530: switch@1f { + switch@0 { compatible =3D "mediatek,mt7621"; - reg =3D <0x1f>; - mediatek,mcm; + reg =3D <0>; =20 - resets =3D <&rstctrl 2>; + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; reset-names =3D "mcm"; =20 + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; - label =3D "lan3"; + label =3D "lan4"; }; =20 - /* Commented out. Port 4 is handled by 2nd GMAC. + /* Commented out, phy4 is muxed to gmac1. port@4 { reg =3D <4>; - label =3D "lan4"; + label =3D "wan"; }; */ =20 @@ -340,7 +543,7 @@ examples: reg =3D <6>; label =3D "cpu"; ethernet =3D <&gmac0>; - phy-mode =3D "rgmii"; + phy-mode =3D "trgmii"; =20 fixed-link { speed =3D <1000>; @@ -353,82 +556,171 @@ examples: }; }; =20 + # Example 6: MT7621: mux external phy to SoC's gmac1 - | - //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> ex= ternal PHY. + #include + #include =20 ethernet { #address-cells =3D <1>; #size-cells =3D <0>; - gmac_0: mac@0 { + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mac@1 { compatible =3D "mediatek,eth-mac"; - reg =3D <0>; + reg =3D <1>; + phy-mode =3D "rgmii"; + phy-handle =3D <&example6_ethphy7>; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* External PHY */ + example6_ethphy7: ethernet-phy@7 { + reg =3D <7>; + phy-mode =3D "rgmii"; + }; + + switch@0 { + compatible =3D "mediatek,mt7621"; + reg =3D <0>; + + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; + reset-names =3D "mcm"; + + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + label =3D "lan1"; + }; + + port@1 { + reg =3D <1>; + label =3D "lan2"; + }; + + port@2 { + reg =3D <2>; + label =3D "lan3"; + }; + + port@3 { + reg =3D <3>; + label =3D "lan4"; + }; + + port@4 { + reg =3D <4>; + label =3D "wan"; + }; =20 - fixed-link { - speed =3D <1000>; - full-duplex; - pause; + port@6 { + reg =3D <6>; + label =3D "cpu"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; + + fixed-link { + speed =3D <1000>; + full-duplex; + pause; + }; + }; + }; }; }; + }; =20 - mdio0: mdio-bus { + # Example 7: MT7621: mux external phy to MT7530's port 5 + - | + #include + #include + + ethernet { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii2_pins>; + + mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - /* External phy */ - ephy5: ethernet-phy@7 { + /* External PHY */ + example7_ethphy7: ethernet-phy@7 { reg =3D <7>; + phy-mode =3D "rgmii"; }; =20 - switch@1f { + switch@0 { compatible =3D "mediatek,mt7621"; - reg =3D <0x1f>; - mediatek,mcm; + reg =3D <0>; =20 - resets =3D <&rstctrl 2>; + mediatek,mcm; + resets =3D <&sysc MT7621_RST_MCM>; reset-names =3D "mcm"; =20 + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 port@0 { reg =3D <0>; - label =3D "lan0"; + label =3D "lan1"; }; =20 port@1 { reg =3D <1>; - label =3D "lan1"; + label =3D "lan2"; }; =20 port@2 { reg =3D <2>; - label =3D "lan2"; + label =3D "lan3"; }; =20 port@3 { reg =3D <3>; - label =3D "lan3"; + label =3D "lan4"; }; =20 port@4 { reg =3D <4>; - label =3D "lan4"; + label =3D "wan"; }; =20 port@5 { reg =3D <5>; - label =3D "lan5"; - phy-mode =3D "rgmii"; - phy-handle =3D <&ephy5>; + label =3D "extphy"; + phy-mode =3D "rgmii-txid"; + phy-handle =3D <&example7_ethphy7>; }; =20 - cpu_port0: port@6 { + port@6 { reg =3D <6>; label =3D "cpu"; - ethernet =3D <&gmac_0>; - phy-mode =3D "rgmii"; + ethernet =3D <&gmac0>; + phy-mode =3D "trgmii"; =20 fixed-link { speed =3D <1000>; --=20 2.34.1 From nobody Sat Sep 21 15:31:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C03E3C28D13 for ; Thu, 25 Aug 2022 08:24:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236885AbiHYIY5 (ORCPT ); Thu, 25 Aug 2022 04:24:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240022AbiHYIYe (ORCPT ); Thu, 25 Aug 2022 04:24:34 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED5DAA5C4D; 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h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=WvQp7bofDc+fmpM/tGQGKX7I9TFzZ3zUHUUzYvkJ6AQ=; b=YvB4hsneKkf+RiFfnFHgFZCezZFXhNS80tp6iYXSonONhV0OAZCuid/6t9G8+5cW jU8A22KEnfM5a0L4Z8UBvPzf2dRaoirROfkagY+H3HRBn1QjWawaZvRQviwXk20H9X0 mqmT0cCbn4DAxtSVS4ig7/osLQ/xgnWW2CkeEG9o= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1661415824124307.4653486511912; Thu, 25 Aug 2022 01:23:44 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Subject: [PATCH v6 5/6] dt-bindings: net: dsa: mediatek,mt7530: define phy-mode per switch Date: Thu, 25 Aug 2022 11:23:00 +0300 Message-Id: <20220825082301.409450-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825082301.409450-1-arinc.unal@arinc9.com> References: <20220825082301.409450-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define acceptable phy-mode values for the CPU ports of mt7530 and mt7531 switches. Remove relevant information from the description of the binding. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/dsa/mediatek,mt7530.yaml | 73 ++++++++++++++++--- 1 file changed, 62 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index e81b3dce874b..fe8ecaf60240 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -49,17 +49,6 @@ description: | * mt7621: phy-mode =3D "rgmii-txid"; * mt7623: phy-mode =3D "rgmii"; =20 - CPU-Ports need a phy-mode property: - Allowed values on mt7530 and mt7621: - - "rgmii" - - "trgmii" - On mt7531: - - "1000base-x" - - "2500base-x" - - "rgmii" - - "sgmii" - - properties: compatible: oneOf: @@ -164,6 +153,65 @@ required: - compatible - reg =20 +$defs: + mt7530-dsa-port: + patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + if: + properties: + label: + const: cpu + then: + if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - gmii + - mii + - rgmii + else: + properties: + phy-mode: + enum: + - rgmii + - trgmii + + mt7531-dsa-port: + patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + if: + properties: + label: + const: cpu + then: + if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - rgmii + - sgmii + else: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - sgmii + allOf: - $ref: dsa.yaml# - if: @@ -185,6 +233,7 @@ allOf: compatible: const: mediatek,mt7530 then: + $ref: "#/$defs/mt7530-dsa-port" required: - core-supply - io-supply @@ -194,6 +243,7 @@ allOf: compatible: const: mediatek,mt7531 then: + $ref: "#/$defs/mt7531-dsa-port" properties: mediatek,mcm: false =20 @@ -202,6 +252,7 @@ allOf: compatible: const: mediatek,mt7621 then: + $ref: "#/$defs/mt7530-dsa-port" required: - mediatek,mcm =20 --=20 2.34.1 From nobody Sat Sep 21 15:31:16 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AFCAC04AA5 for ; Thu, 25 Aug 2022 08:25:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239880AbiHYIZN (ORCPT ); Thu, 25 Aug 2022 04:25:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237975AbiHYIYh (ORCPT ); Thu, 25 Aug 2022 04:24:37 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 476E2A6AEA; Thu, 25 Aug 2022 01:24:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661415833; cv=none; d=zohomail.com; s=zohoarc; b=HnRx4Bkx6TCRsv/FgLgZBpYA9bs1BqDUM+YPR7AvsbVOHjy+kdDfkoTmM87eqt41lO8ALhGmeyikh+RCXmsCsGTZls9305O7uvaqBcStUj7DhQnAbdlixyQhsb/HhrPqQXG5zpOUmRgjgSsIU3cmNsF6xh4wsCzM4tD2s3rHXw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661415833; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=4iatfibaEkRjc+jLuqjlHdBTrArLyKAAD70kGaPgXv8=; b=hZifc1bBl3vpVa5KYYky7lyUe5hoBsI2riI9HbDrlbLlrco9zRuZB5KouaXckYNNWq3Y1T5bfI3z+eADbuV1MKb7S9408GR7mw297vQtiOBW8JTJP6+j7FwzziFAGCnmLmwi+gE53/BqC6YLd+YM6Uq+VgsH09Clor9bstW2ve4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1661415833; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=4iatfibaEkRjc+jLuqjlHdBTrArLyKAAD70kGaPgXv8=; b=FLt744MEU/IoMd97w4eXxByxmfH2ZqisXGRT71jke8n8Tq3gmlS+rZTHBZN4JZkt UZQ9zQdzl1QfVCG0h7DrcsgeMqlJIqL6WXMl+pp+aew1jDdZeVSUtcaCpcmyLLa7z9r nQTSk6F0nha98+megiwU5mMHl401AneUzDfpl3N8= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1661415830692840.2140356682969; Thu, 25 Aug 2022 01:23:50 -0700 (PDT) From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Krzysztof Kozlowski Subject: [PATCH v6 6/6] dt-bindings: net: dsa: mediatek,mt7530: update binding description Date: Thu, 25 Aug 2022 11:23:01 +0300 Message-Id: <20220825082301.409450-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220825082301.409450-1-arinc.unal@arinc9.com> References: <20220825082301.409450-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the description of the binding. - Describe the switches, which SoCs they are in, or if they are standalone. - Explain the various ways of configuring MT7530's port 5. - Remove phy-mode =3D "rgmii-txid" from description. Same code path is followed for delayed rgmii and rgmii phy-mode on mtk_eth_soc.c. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Krzysztof Kozlowski --- .../bindings/net/dsa/mediatek,mt7530.yaml | 97 ++++++++++++------- 1 file changed, 62 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml= b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index fe8ecaf60240..f9e7b6e20b35 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -13,41 +13,68 @@ maintainers: - Sean Wang =20 description: | - Port 5 of mt7530 and mt7621 switch is muxed between: - 1. GMAC5: GMAC5 can interface with another external MAC or PHY. - 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd= GMAC - of the SOC. Used in many setups where port 0/4 becomes the WAN port. - Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only conne= cted to - GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not - connected to external component! - - Port 5 modes/configurations: - 1. Port 5 is disabled and isolated: An external phy can interface to the= 2nd - GMAC of the SOC. - In the case of a build-in MT7530 switch, port 5 shares the RGMII bus = with 2nd - GMAC and an optional external phy. Mind the GPIO/pinctl settings of t= he SOC! - 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. - It is a simple MAC to PHY interface, port 5 needs to be setup for xMI= I mode - and RGMII delay. - 3. Port 5 is muxed to GMAC5 and can interface to an external phy. - Port 5 becomes an extra switch port. - Only works on platform where external phy TX<->RX lines are swapped. - Like in the Ubiquiti ER-X-SFP. - 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU = port. - Currently a 2nd CPU port is not supported by DSA code. - - Depending on how the external PHY is wired: - 1. normal: The PHY can only connect to 2nd GMAC but not to the switch - 2. swapped: RGMII TX, RX are swapped; external phy interface with the sw= itch as - a ethernet port. But can't interface to the 2nd GMAC. - - Based on the DT the port 5 mode is configured. - - Driver tries to lookup the phy-handle of the 2nd GMAC of the master devi= ce. - When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. - phy-mode must be set, see also example 2 below! - * mt7621: phy-mode =3D "rgmii-txid"; - * mt7623: phy-mode =3D "rgmii"; + There are two versions of MT7530, standalone and in a multi-chip module. + + MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620D= AN, + MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. + + MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100= PHYs + and the switch registers are directly mapped into SoC's memory map rathe= r than + using MDIO. The DSA driver currently doesn't support this. + + There is only the standalone version of MT7531. + + Port 5 on MT7530 has got various ways of configuration. + + For standalone MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the = SoC + which port 5 is wired to. Usually used for connecting the wan port + directly to the CPU to achieve 2 Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-h= andle + property refers to on the gmac node to mux the specified phy. + + The driver requires the gmac of the SoC to have "mediatek,eth-mac" a= s the + compatible string and the reg must be 1. So, for now, only gmac1 of = an + MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. + Check out example 5 for a similar configuration. + + - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. + Check out example 7 for a similar configuration. + + For multi-chip module MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. + Usually used for connecting the wan port directly to the CPU to achi= eve 2 + Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-h= andle + property refers to on the gmac node to mux the specified phy. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 functi= on. + Check out example 5. + + - In case of an external phy wired to gmac1 of the SoC, port 5 must no= t be + enabled. + + In case of muxing PHY 0 or 4, the external phy must not be enabled. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 functi= on. + Check out example 6. + + - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. + The external phy must be wired TX to TX to gmac1 of the SoC for this= to + work. Ubiquiti EdgeRouter X SFP is wired this way. + + Muxing PHY 0 or 4 won't work when the external phy is connected TX t= o TX. + + For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. + Check out example 7. =20 properties: compatible: --=20 2.34.1