From nobody Mon Sep 15 23:26:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80C31C54EBD for ; Mon, 9 Jan 2023 19:27:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237513AbjAIT1W (ORCPT ); Mon, 9 Jan 2023 14:27:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237260AbjAIT1B (ORCPT ); Mon, 9 Jan 2023 14:27:01 -0500 Received: from mail-oi1-f171.google.com (mail-oi1-f171.google.com [209.85.167.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1151F63389; Mon, 9 Jan 2023 11:26:46 -0800 (PST) Received: by mail-oi1-f171.google.com with SMTP id s66so7408095oib.7; Mon, 09 Jan 2023 11:26:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jYXNYZPoEZW+cpasaK2qS1x4BldwPdfg2ohHEnkw8tk=; b=kQGO3iEdLoOWs1SkqSU9Cp/VYjVBTvd+VIr8HmRaTSUPZCW5GqMXqKJZUPQJubbR34 jv1L743ZNUo0h61t6euXLvC8+Y6/wrMCthMfZzKBirZ6x/9yK3AOQpsBC8zyORUXVGCU oazwsjOvJCGHhKgKtEMBloVVYj49Ur7ZMmGbQVjrX7G8iTzrHfHl+gtvaEBGgHUj64Vg eL0ItaEvQiSJmJ0zvSTcQvvo1inOqX5INbKbgqBojb6Z6FJw4ghLwdWnICzFzkPFpZO/ pnKLmXlI20mM1bryGAz8whINnJBj/dz5mg96FgHO7KaKFWP9/mGYuDZdluh9NxFjm+z6 LHIg== X-Gm-Message-State: AFqh2kp4p6LtxSWvNI+ktJtLFPVGf9kp9gXLGJTZuTDz91ZMdyWd7Gqf 4aNuFry6JlG5vhBVdDsYSWCRgoF3Yg== X-Google-Smtp-Source: AMrXdXuWN6s2Ip6alGnEK9Y77CLyDy7KYWq7dZYuDLZi9RmEcarrAkz9gBXHZpKxv9AwTjYuASRn7g== X-Received: by 2002:a05:6808:190e:b0:35c:b79:8cf8 with SMTP id bf14-20020a056808190e00b0035c0b798cf8mr38989203oib.6.1673292405102; Mon, 09 Jan 2023 11:26:45 -0800 (PST) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id bg31-20020a056808179f00b00363b5a6bc9esm4343635oib.12.2023.01.09.11.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:26:44 -0800 (PST) Received: (nullmailer pid 1483616 invoked by uid 1000); Mon, 09 Jan 2023 19:26:31 -0000 From: Rob Herring Date: Mon, 09 Jan 2023 13:26:22 -0600 Subject: [PATCH v4 6/8] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20220825-arm-spe-v8-7-v4-6-327f860daf28@kernel.org> References: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v4-0-327f860daf28@kernel.org> To: Peter Zijlstra , Will Deacon , Mark Rutland , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Cc: Mark Brown , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, James Clark X-Mailer: b4 0.12-dev Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the additional event. Tested-by: James Clark Signed-off-by: Rob Herring Reviewed-by: Anshuman Khandual --- v4: - Rebase on v6.2-rc1 v3: - No change v2: - Update for v6.1 sysreg generated header changes --- arch/arm64/include/asm/sysreg.h | 2 ++ drivers/perf/arm_spe_pmu.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index db269eda7c1c..fc8787727792 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -221,6 +221,8 @@ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P2 \ + (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) =20 /* Buffer error reporting */ #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index af6d3867c3e7..82f67e941bc4 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_EL1_PMSVer_IMP: return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: + return PMSEVFR_EL1_RES0_V1P1; + case ID_AA64DFR0_EL1_PMSVer_V1P2: /* Return the highest version we support in default */ default: - return PMSEVFR_EL1_RES0_V1P1; + return PMSEVFR_EL1_RES0_V1P2; } } =20 --=20 2.39.0